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Groups > linux.kernel > #1510192 > unrolled thread
| Started by | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| First post | 2016-10-27 16:00 +0200 |
| Last post | 2016-10-27 18:00 +0200 |
| Articles | 9 — 3 participants |
Back to article view | Back to linux.kernel
[RFC PATCH 0/5] add support for DMO embedded controller Zahari Doychev <zahari.doychev@linux.com> - 2016-10-27 16:00 +0200
[RFC PATCH 5/5] rtm-dmec: running time meter support Zahari Doychev <zahari.doychev@linux.com> - 2016-10-27 16:10 +0200
[RFC PATCH 3/5] gpio-dmec: gpio support for dmec Zahari Doychev <zahari.doychev@linux.com> - 2016-10-27 16:10 +0200
Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec Linus Walleij <linus.walleij@linaro.org> - 2016-10-29 11:10 +0200
Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec Zahari Doychev <zahari.doychev@linux.com> - 2016-10-31 10:00 +0100
Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec Linus Walleij <linus.walleij@linaro.org> - 2016-10-31 13:30 +0100
[RFC PATCH 1/5] dmec: add DMO mfd driver Zahari Doychev <zahari.doychev@linux.com> - 2016-10-27 16:10 +0200
Re: [RFC PATCH 0/5] add support for DMO embedded controller Greg KH <gregkh@linuxfoundation.org> - 2016-10-27 17:20 +0200
Re: [RFC PATCH 0/5] add support for DMO embedded controller Zahari Doychev <zahari.doychev@linux.com> - 2016-10-27 18:00 +0200
| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-27 16:00 +0200 |
| Subject | [RFC PATCH 0/5] add support for DMO embedded controller |
| Message-ID | <swTnP-2Bn-21@gated-at.bofh.it> |
This patch series adds support for the Data Modul Embedded Controller(dmec) which is implemented within an on board FPGA found on Data Modul embedded CPU modules. The dmec is connected to the host through the LPC bus and its registers are mapped into the host I/O space. The controller supports two addressing modes: linear and indexed. The driver adds support for the following functionality: - i2c - gpio - watchdog - running time meter (rtm) Zahari Doychev (5): dmec: add DMO mfd driver i2c-dmec: add i2c bus support for dmec gpio-dmec: gpio support for dmec wdt-dmec: watchdog support for dmec rtm-dmec: running time meter support drivers/staging/Kconfig | 2 +- drivers/staging/Makefile | 1 +- drivers/staging/dmec/Kconfig | 50 +++- drivers/staging/dmec/Makefile | 5 +- drivers/staging/dmec/dmec-core.c | 500 ++++++++++++++++++++++++++++- drivers/staging/dmec/dmec.h | 20 +- drivers/staging/dmec/gpio-dmec.c | 390 ++++++++++++++++++++++- drivers/staging/dmec/i2c-dmec.c | 524 +++++++++++++++++++++++++++++- drivers/staging/dmec/rtm-dmec.c | 203 +++++++++++- drivers/staging/dmec/wdt-dmec.c | 569 ++++++++++++++++++++++++++++++++- 10 files changed, 2264 insertions(+), 0 deletions(-) create mode 100644 drivers/staging/dmec/Kconfig create mode 100644 drivers/staging/dmec/Makefile create mode 100644 drivers/staging/dmec/dmec-core.c create mode 100644 drivers/staging/dmec/dmec.h create mode 100644 drivers/staging/dmec/gpio-dmec.c create mode 100644 drivers/staging/dmec/i2c-dmec.c create mode 100644 drivers/staging/dmec/rtm-dmec.c create mode 100644 drivers/staging/dmec/wdt-dmec.c base-commit: 9fe68cad6e74967b88d0c6aeca7d9cd6b6e91942 -- git-series 0.8.10
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| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-27 16:10 +0200 |
| Subject | [RFC PATCH 5/5] rtm-dmec: running time meter support |
| Message-ID | <swTxw-2VB-25@gated-at.bofh.it> |
| In reply to | #1510192 |
This is support for the running time meter(RTM) found on the Data Modul
embedded boards.
Signed-off-by: Zahari Doychev <zahari.doychev@linux.com>
---
drivers/staging/dmec/Kconfig | 10 ++-
drivers/staging/dmec/Makefile | 1 +-
drivers/staging/dmec/rtm-dmec.c | 203 +++++++++++++++++++++++++++++++++-
3 files changed, 214 insertions(+), 0 deletions(-)
create mode 100644 drivers/staging/dmec/rtm-dmec.c
diff --git a/drivers/staging/dmec/Kconfig b/drivers/staging/dmec/Kconfig
index eddf0bb..f6f4146 100644
--- a/drivers/staging/dmec/Kconfig
+++ b/drivers/staging/dmec/Kconfig
@@ -38,3 +38,13 @@ config WDT_DMEC
To compile this driver as a module, say M here: the module will be
called wdt-dmec
+
+config RTM_DMEC
+ tristate "Data Modul RTM"
+ depends on MFD_DMEC
+ help
+ Say Y to enable support for a running time meter(RTM) on a Data Modul
+ embedded controllers.
+
+ To compile this driver as a module, say M here: the module will be
+ called wdt-dmec
diff --git a/drivers/staging/dmec/Makefile b/drivers/staging/dmec/Makefile
index 8b363cc..b55d56f 100644
--- a/drivers/staging/dmec/Makefile
+++ b/drivers/staging/dmec/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_MFD_DMEC) += dmec-core.o
obj-$(CONFIG_I2C_DMEC) += i2c-dmec.o
obj-$(CONFIG_GPIO_DMEC) += gpio-dmec.o
obj-$(CONFIG_WDT_DMEC) += wdt-dmec.o
+obj-$(CONFIG_RTM_DMEC) += rtm-dmec.o
diff --git a/drivers/staging/dmec/rtm-dmec.c b/drivers/staging/dmec/rtm-dmec.c
new file mode 100644
index 0000000..cd32536
--- /dev/null
+++ b/drivers/staging/dmec/rtm-dmec.c
@@ -0,0 +1,203 @@
+/*
+ * Running time meter for Data Modul AG Embedded Controller
+ *
+ * Copyright (C) 2016 Data Modul AG
+ *
+ * Author: Sebastian Wezel <sebastian@torvus-musica.de>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mutex.h>
+
+#include "dmec.h"
+
+#define DMEC_RTM_RTM_OFFSET 0x60
+#define DMEC_RTM_RTMREV_OFFSET 0x63
+#define DMEC_RTM_OOSRTM_OFFSET 0x64
+#define DMEC_RTM_BTCNT_OFFSET 0x68
+#define DMEC_RTM_BBCTNT_OFFSET 0x6c
+
+static DEFINE_MUTEX(rtm_lock);
+static struct regmap *regmap;
+static bool enable_reset;
+
+static unsigned int dmec_rtm_get_three_byte(unsigned int reg,
+ struct device *dev)
+{
+ unsigned int low = 0, mid = 0, high = 0, val = 0;
+
+ regmap_read(regmap, reg, &low);
+ regmap_read(regmap, reg + 1, &mid);
+ regmap_read(regmap, reg + 2, &high);
+
+ val = ((high << 16) | (mid << 8) | (low & 0x0000ff));
+ return val;
+}
+
+static ssize_t dmec_rtm_time_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned int val = 0;
+
+ val = dmec_rtm_get_three_byte(DMEC_RTM_RTM_OFFSET, dev);
+ return scnprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static ssize_t dmec_rtm_time_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ unsigned int low = 0, mid = 0, high = 0, higher = 0;
+ long val = 0, ret = -EPERM;
+ int reg = DMEC_RTM_RTM_OFFSET;
+
+ mutex_lock(&rtm_lock);
+ if (enable_reset && !kstrtol(buf, 10, &val)) {
+ higher = (val >> 24) & 0xff;
+ high = (val >> 16) & 0xff;
+ mid = (val >> 8) & 0xff;
+ low = val & 0xff;
+
+ regmap_write(regmap, reg, low);
+ regmap_write(regmap, reg + 1, mid);
+ regmap_write(regmap, reg + 2, high);
+ regmap_write(regmap, reg + 3, higher);
+ enable_reset = false;
+ ret = count;
+ }
+ mutex_unlock(&rtm_lock);
+
+ return ret;
+}
+
+static ssize_t dmec_rtm_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned int val = 0;
+
+ regmap_read(regmap, DMEC_RTM_RTMREV_OFFSET, &val);
+ return scnprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static ssize_t dmec_rtm_out_of_spec_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ unsigned int val = 0;
+
+ val = dmec_rtm_get_three_byte(DMEC_RTM_OOSRTM_OFFSET, dev);
+ return scnprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static ssize_t dmec_rtm_boot_count_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ unsigned int val = 0;
+
+ val = dmec_rtm_get_three_byte(DMEC_RTM_BTCNT_OFFSET, dev);
+ return scnprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static ssize_t dmec_rtm_bios_boot_count_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ unsigned int val = 0;
+
+ val = dmec_rtm_get_three_byte(DMEC_RTM_BBCTNT_OFFSET, dev);
+ return scnprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static ssize_t dmec_rtm_enable_reset_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return scnprintf(buf, PAGE_SIZE, "%d\n", enable_reset);
+}
+
+static ssize_t dmec_rtm_enable_reset_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ long val = 0;
+
+ mutex_lock(&rtm_lock);
+ if (kstrtol(buf, 10, &val) != 0)
+ enable_reset = false;
+
+ /* The enable should only work if the value is 1 */
+ if (val == 1)
+ enable_reset = true;
+ mutex_unlock(&rtm_lock);
+ return count;
+}
+
+static DEVICE_ATTR(rtm_time, 0664, dmec_rtm_time_show, dmec_rtm_time_store);
+static DEVICE_ATTR(rtm_version, 0444, dmec_rtm_version_show, NULL);
+static DEVICE_ATTR(rtm_out_of_spec, 0444, dmec_rtm_out_of_spec_show, NULL);
+static DEVICE_ATTR(rtm_boot_count, 0444, dmec_rtm_boot_count_show, NULL);
+static DEVICE_ATTR(rtm_bios_boot_count, 0444, dmec_rtm_bios_boot_count_show,
+ NULL);
+static DEVICE_ATTR(rtm_enable_reset, 0664, dmec_rtm_enable_reset_show,
+ dmec_rtm_enable_reset_store);
+
+static struct attribute *rtm_attribute[] = {
+ &dev_attr_rtm_time.attr,
+ &dev_attr_rtm_version.attr,
+ &dev_attr_rtm_out_of_spec.attr,
+ &dev_attr_rtm_boot_count.attr,
+ &dev_attr_rtm_bios_boot_count.attr,
+ &dev_attr_rtm_enable_reset.attr,
+ NULL
+};
+
+static const struct attribute_group rtm_attr_group = {
+ .attrs = rtm_attribute,
+};
+
+static int dmec_rtm_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ regmap = dmec_get_regmap(pdev->dev.parent);
+ enable_reset = 0;
+
+ ret = sysfs_create_group(&pdev->dev.kobj, &rtm_attr_group);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int dmec_rtm_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &rtm_attr_group);
+
+ return 0;
+}
+
+static struct platform_driver dmec_rtm_driver = {
+ .driver = {
+ .name = "dmec-rtm",
+ .owner = THIS_MODULE,
+ },
+ .probe = dmec_rtm_probe,
+ .remove = dmec_rtm_remove,
+};
+
+module_platform_driver(dmec_rtm_driver);
+
+MODULE_DESCRIPTION("dmec rtm driver");
+MODULE_AUTHOR("Sebastian Wezel <sebastian@torvus-musica.de>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dmec-rtm");
--
git-series 0.8.10
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| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-27 16:10 +0200 |
| Subject | [RFC PATCH 3/5] gpio-dmec: gpio support for dmec |
| Message-ID | <swTxx-2VB-63@gated-at.bofh.it> |
| In reply to | #1510192 |
This is support for the gpio functionality found on the Data Modul embedded
controllers
Signed-off-by: Zahari Doychev <zahari.doychev@linux.com>
---
drivers/staging/dmec/Kconfig | 10 +-
drivers/staging/dmec/Makefile | 1 +-
drivers/staging/dmec/dmec.h | 5 +-
drivers/staging/dmec/gpio-dmec.c | 390 ++++++++++++++++++++++++++++++++-
4 files changed, 406 insertions(+), 0 deletions(-)
create mode 100644 drivers/staging/dmec/gpio-dmec.c
diff --git a/drivers/staging/dmec/Kconfig b/drivers/staging/dmec/Kconfig
index 0067b0b..9c4a8e5 100644
--- a/drivers/staging/dmec/Kconfig
+++ b/drivers/staging/dmec/Kconfig
@@ -17,3 +17,13 @@ config I2C_DMEC
To compile this driver as a module, say M here: the module will be
called i2c-dmec
+
+config GPIO_DMEC
+ tristate "Data Modul GPIO"
+ depends on MFD_DMEC && GPIOLIB
+ help
+ Say Y here to enable support for a GPIOs on a Data Module embedded
+ controller.
+
+ To compile this driver as a module, say M here: the module will be
+ called gpio-dmec
diff --git a/drivers/staging/dmec/Makefile b/drivers/staging/dmec/Makefile
index c51a37e..b71b27b 100644
--- a/drivers/staging/dmec/Makefile
+++ b/drivers/staging/dmec/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MFD_DMEC) += dmec-core.o
obj-$(CONFIG_I2C_DMEC) += i2c-dmec.o
+obj-$(CONFIG_GPIO_DMEC) += gpio-dmec.o
diff --git a/drivers/staging/dmec/dmec.h b/drivers/staging/dmec/dmec.h
index 178937d..cc42926 100644
--- a/drivers/staging/dmec/dmec.h
+++ b/drivers/staging/dmec/dmec.h
@@ -1,6 +1,11 @@
#ifndef _LINUX_MFD_DMEC_H
#define _LINUX_MFD_DMEC_H
+struct dmec_gpio_platform_data {
+ int gpio_base;
+ int chip_num;
+};
+
struct dmec_i2c_platform_data {
u32 reg_shift; /* register offset shift value */
u32 reg_io_width; /* register io read/write width */
diff --git a/drivers/staging/dmec/gpio-dmec.c b/drivers/staging/dmec/gpio-dmec.c
new file mode 100644
index 0000000..4cefbbf
--- /dev/null
+++ b/drivers/staging/dmec/gpio-dmec.c
@@ -0,0 +1,390 @@
+/*
+ * GPIO driver for Data Modul AG Embedded Controller
+ *
+ * Copyright (C) 2016 Data Modul AG
+ *
+ * Authors: Zahari Doychev <zahari.doychev@linux.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/acpi.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/gpio.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+
+#include "dmec.h"
+
+#define DMEC_GPIO_BANKS 2
+#define DMEC_GPIO_MAX_NUM 8
+#define DMEC_GPIO_BASE(x) (0x40 + 0x10 * ((x)->chip_num))
+#define DMEC_GPIO_SET_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x1)
+#define DMEC_GPIO_GET_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x1)
+#define DMEC_GPIO_CLR_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x2)
+#define DMEC_GPIO_VER_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x2)
+#define DMEC_GPIO_DIR_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x3)
+#define DMEC_GPIO_IRQTYPE_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x4)
+#define DMEC_GPIO_EVTSTA_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x6)
+#define DMEC_GPIO_IRQCFG_OFFSET(x) (DMEC_GPIO_BASE(x) + 0x8)
+#define DMEC_GPIO_NOPS_OFFSET(x) (DMEC_GPIO_BASE(x) + 0xa)
+#define DMEC_GPIO_IRQSTA_OFFSET(x) (DMEC_GPIO_BASE(x) + 0xb)
+
+#ifdef CONFIG_PM
+struct dmec_reg_ctx {
+ u32 dat;
+ u32 dir;
+ u32 imask;
+ u32 icfg[2];
+ u32 emask[2];
+};
+#endif
+
+struct dmec_gpio_priv {
+ struct regmap *regmap;
+ struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ unsigned int chip_num;
+ unsigned int irq;
+ u8 ver;
+#ifdef CONFIG_PM
+ struct dmec_reg_ctx regs;
+#endif
+};
+
+static int dmec_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ unsigned int val;
+
+ /* read get register */
+ regmap_read(regmap, DMEC_GPIO_GET_OFFSET(priv), &val);
+
+ return !!(val & BIT(offset));
+}
+
+static void dmec_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+
+ if (value)
+ regmap_write(regmap, DMEC_GPIO_SET_OFFSET(priv), BIT(offset));
+ else
+ regmap_write(regmap, DMEC_GPIO_CLR_OFFSET(priv), BIT(offset));
+}
+
+static int dmec_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+
+ /* set pin as input */
+ regmap_update_bits(regmap, DMEC_GPIO_DIR_OFFSET(priv), BIT(offset), 0);
+
+ return 0;
+}
+
+static int dmec_gpio_direction_output(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ unsigned int val = BIT(offset);
+
+ if (value)
+ regmap_write(regmap, DMEC_GPIO_SET_OFFSET(priv), val);
+ else
+ regmap_write(regmap, DMEC_GPIO_CLR_OFFSET(priv), val);
+
+ /* set pin as output */
+ regmap_update_bits(regmap, DMEC_GPIO_DIR_OFFSET(priv), val, val);
+
+ return 0;
+}
+
+static int dmec_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ unsigned int val;
+
+ regmap_read(regmap, DMEC_GPIO_DIR_OFFSET(priv), &val);
+
+ return !(val & BIT(offset));
+}
+
+static int dmec_gpio_pincount(struct dmec_gpio_priv *priv)
+{
+ struct regmap *regmap = priv->regmap;
+ unsigned int val;
+
+ regmap_read(regmap, DMEC_GPIO_NOPS_OFFSET(priv), &val);
+
+ /* number of pins is val + 1 */
+ return val == 0xff ? 0 : (val & 7) + 1;
+}
+
+static int dmec_gpio_get_version(struct gpio_chip *gc)
+{
+ struct device *dev = gc->parent;
+ struct dmec_gpio_priv *p = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ unsigned int v;
+
+ regmap_read(p->regmap, DMEC_GPIO_VER_OFFSET(p), &v);
+ p->ver = v;
+ dev_info(dev, "chip%u v%u.%u\n", p->chip_num, (v >> 4) & 0xf, v & 0xf);
+
+ return 0;
+}
+
+static void dmec_gpio_irq_enable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ int offset, mask;
+
+ offset = DMEC_GPIO_IRQCFG_OFFSET(priv) + (d->hwirq >> 2);
+ mask = BIT((d->hwirq & 3) << 1);
+
+ regmap_update_bits(regmap, offset, mask, mask);
+}
+
+static void dmec_gpio_irq_disable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ int offset, mask;
+
+ offset = DMEC_GPIO_IRQCFG_OFFSET(priv) + (d->hwirq >> 2);
+ mask = 3 << ((d->hwirq & 3) << 1);
+
+ regmap_update_bits(regmap, offset, mask, 0);
+}
+
+static int dmec_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
+ gpio_chip);
+ struct regmap *regmap = priv->regmap;
+ unsigned int offset, mask, val;
+
+ offset = DMEC_GPIO_IRQTYPE_OFFSET(priv) + (d->hwirq >> 2);
+ mask = ((d->hwirq & 3) << 1);
+
+ regmap_read(regmap, offset, &val);
+
+ val &= ~(3 << mask);
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_LEVEL_LOW:
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ val |= (1 << mask);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ val |= (2 << mask);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ val |= (3 << mask);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write(regmap, offset, val);
+
+ return 0;
+}
+
+static irqreturn_t dmec_gpio_irq_handler(int irq, void *dev_id)
+{
+ struct dmec_gpio_priv *p = dev_id;
+ struct irq_domain *d = p->gpio_chip.irqdomain;
+ unsigned int irqs_handled = 0;
+ unsigned int val = 0, stat = 0;
+
+ regmap_read(p->regmap, DMEC_GPIO_IRQSTA_OFFSET(p), &val);
+ stat = val;
+ while (stat) {
+ int line = __ffs(stat);
+ int child_irq = irq_find_mapping(d, line);
+
+ handle_nested_irq(child_irq);
+ stat &= ~(BIT(line));
+ irqs_handled++;
+ }
+ regmap_write(p->regmap, DMEC_GPIO_EVTSTA_OFFSET(p), val);
+
+ return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static int dmec_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dmec_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
+ struct dmec_gpio_priv *priv;
+ struct gpio_chip *gpio_chip;
+ struct irq_chip *irq_chip;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->regmap = dmec_get_regmap(pdev->dev.parent);
+ priv->chip_num = pdata->chip_num;
+
+ gpio_chip = &priv->gpio_chip;
+ gpio_chip->label = "gpio-dmec";
+ gpio_chip->owner = THIS_MODULE;
+ gpio_chip->parent = dev;
+ gpio_chip->label = dev_name(dev);
+ gpio_chip->can_sleep = true;
+
+ gpio_chip->base = pdata->gpio_base;
+
+ gpio_chip->direction_input = dmec_gpio_direction_input;
+ gpio_chip->direction_output = dmec_gpio_direction_output;
+ gpio_chip->get_direction = dmec_gpio_get_direction;
+ gpio_chip->get = dmec_gpio_get;
+ gpio_chip->set = dmec_gpio_set;
+ gpio_chip->ngpio = dmec_gpio_pincount(priv);
+ if (gpio_chip->ngpio == 0) {
+ dev_err(dev, "No GPIOs detected\n");
+ return -ENODEV;
+ }
+
+ dmec_gpio_get_version(gpio_chip);
+
+ irq_chip = &priv->irq_chip;
+ irq_chip->name = dev_name(dev);
+ irq_chip->irq_mask = dmec_gpio_irq_disable;
+ irq_chip->irq_unmask = dmec_gpio_irq_enable;
+ irq_chip->irq_set_type = dmec_gpio_irq_set_type;
+
+ ret = devm_gpiochip_add_data(&pdev->dev, gpio_chip, priv);
+ if (ret) {
+ dev_err(dev, "Could not register GPIO chip\n");
+ return ret;
+ }
+
+ ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0,
+ handle_simple_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(dev, "cannot add irqchip\n");
+ return ret;
+ }
+
+ priv->irq = platform_get_irq(pdev, 0);
+ ret = devm_request_threaded_irq(dev, priv->irq,
+ NULL, dmec_gpio_irq_handler,
+ IRQF_ONESHOT | IRQF_SHARED,
+ dev_name(dev), priv);
+ if (ret) {
+ dev_err(dev, "unable to get irq: %d\n", ret);
+ return ret;
+ }
+
+ gpiochip_set_chained_irqchip(gpio_chip, irq_chip, priv->irq, NULL);
+
+ platform_set_drvdata(pdev, priv);
+
+ return 0;
+}
+
+static int dmec_gpio_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int dmec_gpio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
+ struct regmap *regmap = p->regmap;
+ struct dmec_reg_ctx *ctx = &p->regs;
+
+ regmap_read(regmap, DMEC_GPIO_BASE(p), &ctx->dat);
+ regmap_read(regmap, DMEC_GPIO_DIR_OFFSET(p), &ctx->dir);
+ regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->imask);
+ regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), &ctx->emask[0]);
+ regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, &ctx->emask[1]);
+ regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->icfg[0]);
+ regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, &ctx->icfg[1]);
+
+ devm_free_irq(&pdev->dev, p->irq, p);
+
+ return 0;
+}
+
+static int dmec_gpio_resume(struct platform_device *pdev)
+{
+ struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
+ struct regmap *regmap = p->regmap;
+ struct dmec_reg_ctx *ctx = &p->regs;
+ int ret;
+
+ regmap_write(regmap, DMEC_GPIO_BASE(p), ctx->dat);
+ regmap_write(regmap, DMEC_GPIO_DIR_OFFSET(p), ctx->dir);
+ regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->icfg[0]);
+ regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, ctx->icfg[1]);
+ regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), ctx->emask[0]);
+ regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, ctx->emask[1]);
+ regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->imask);
+ regmap_write(regmap, DMEC_GPIO_EVTSTA_OFFSET(p), 0xff);
+
+ ret = devm_request_threaded_irq(&pdev->dev, p->irq,
+ NULL, dmec_gpio_irq_handler,
+ IRQF_ONESHOT | IRQF_SHARED,
+ dev_name(&pdev->dev), p);
+ if (ret)
+ dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
+
+ return ret;
+}
+#else
+#define dmec_gpio_suspend NULL
+#define dmec_gpio_resume NULL
+#endif
+
+static struct platform_driver dmec_gpio_driver = {
+ .driver = {
+ .name = "dmec-gpio",
+ .owner = THIS_MODULE,
+ },
+ .probe = dmec_gpio_probe,
+ .remove = dmec_gpio_remove,
+ .suspend = dmec_gpio_suspend,
+ .resume = dmec_gpio_resume,
+};
+
+module_platform_driver(dmec_gpio_driver);
+
+MODULE_DESCRIPTION("dmec gpio driver");
+MODULE_AUTHOR("Zahari Doychev <zahari.doychev@linux.com");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dmec-gpio");
--
git-series 0.8.10
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-10-29 11:10 +0200 |
| Subject | Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec |
| Message-ID | <sxxOh-4cz-1@gated-at.bofh.it> |
| In reply to | #1510217 |
On Thu, Oct 27, 2016 at 12:47 PM, Zahari Doychev
<zahari.doychev@linux.com> wrote:
> This is support for the gpio functionality found on the Data Modul embedded
> controllers
>
> Signed-off-by: Zahari Doychev <zahari.doychev@linux.com>
> ---
> drivers/staging/dmec/Kconfig | 10 +-
> drivers/staging/dmec/Makefile | 1 +-
> drivers/staging/dmec/dmec.h | 5 +-
> drivers/staging/dmec/gpio-dmec.c | 390 ++++++++++++++++++++++++++++++++-
I guess Greg has already asked, but why is this in staging?
The driver doesn't seem very complex or anything, it would not
be overly troublesome to get it into the proper kernel subsystems.
> +config GPIO_DMEC
> + tristate "Data Modul GPIO"
> + depends on MFD_DMEC && GPIOLIB
So the depends on GPIOLIB can go away if you just put it into
drivers/gpio with the rest.
> +struct dmec_gpio_platform_data {
> + int gpio_base;
NAK, always use -1. No hardcoding the GPIO base other than on
legacy systems.
> + int chip_num;
I suspect you may not need this either. struct platform_device
already contains a ->id field, just use that when instantiating
your driver if you need an instance number.
So I think you need zero platform data for this.
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/errno.h>
> +#include <linux/acpi.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/gpio.h>
You should only need <linux/gpio/driver.h>
> +#ifdef CONFIG_PM
> +struct dmec_reg_ctx {
> + u32 dat;
> + u32 dir;
> + u32 imask;
> + u32 icfg[2];
> + u32 emask[2];
> +};
> +#endif
> +
> +struct dmec_gpio_priv {
> + struct regmap *regmap;
> + struct gpio_chip gpio_chip;
> + struct irq_chip irq_chip;
> + unsigned int chip_num;
> + unsigned int irq;
> + u8 ver;
> +#ifdef CONFIG_PM
> + struct dmec_reg_ctx regs;
> +#endif
> +};
The #ifdef for saving the state is a bit kludgy. Can't you just have it there
all the time? Or is this a footprint-sensitive system?
> +static int dmec_gpio_get(struct gpio_chip *gc, unsigned int offset)
> +{
> + struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
> + gpio_chip);
Use the new pattern with
struct dmec_gpio_priv *priv = gpiochip_get_data(gc);
This needs you to use devm_gpiochip_add_data() below.
> +static int dmec_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> + struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
> + gpio_chip);
> + struct regmap *regmap = priv->regmap;
> + unsigned int offset, mask, val;
> +
> + offset = DMEC_GPIO_IRQTYPE_OFFSET(priv) + (d->hwirq >> 2);
> + mask = ((d->hwirq & 3) << 1);
> +
> + regmap_read(regmap, offset, &val);
> +
> + val &= ~(3 << mask);
> + switch (type & IRQ_TYPE_SENSE_MASK) {
> + case IRQ_TYPE_LEVEL_LOW:
> + break;
> + case IRQ_TYPE_EDGE_RISING:
> + val |= (1 << mask);
> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + val |= (2 << mask);
> + break;
> + case IRQ_TYPE_EDGE_BOTH:
> + val |= (3 << mask);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + regmap_write(regmap, offset, val);
> +
> + return 0;
> +}
This chip uses handle_simple_irq() which is fine if the chip really has no
edge detector ACK register.
What some chips have is a special register to clearing (ACK:ing) the edge
IRQ which makes it possible for a new IRQ to be handled as soon as
that has happened, and those need to use handle_edge_irq() for edge IRQs
and handle_level_irq() for level IRQs, with the side effect that the edge
IRQ path will additionally call the .irq_ack() callback on the irqchip
when handle_edge_irq() is used. In this case we set handle_bad_irq()
as default handler and set up the right handler i .set_type().
Look at drivers/gpio/gpio-pl061.c for an example.
If you DON'T have a special edge ACK register, keep it like this.
> +static irqreturn_t dmec_gpio_irq_handler(int irq, void *dev_id)
> +{
> + struct dmec_gpio_priv *p = dev_id;
> + struct irq_domain *d = p->gpio_chip.irqdomain;
> + unsigned int irqs_handled = 0;
> + unsigned int val = 0, stat = 0;
> +
> + regmap_read(p->regmap, DMEC_GPIO_IRQSTA_OFFSET(p), &val);
> + stat = val;
> + while (stat) {
> + int line = __ffs(stat);
> + int child_irq = irq_find_mapping(d, line);
> +
> + handle_nested_irq(child_irq);
> + stat &= ~(BIT(line));
> + irqs_handled++;
> + }
I think you should re-read the status register in the loop. An IRQ may
appear while you are reading.
> +static int dmec_gpio_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct dmec_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct dmec_gpio_priv *priv;
> + struct gpio_chip *gpio_chip;
> + struct irq_chip *irq_chip;
> + int ret = 0;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->regmap = dmec_get_regmap(pdev->dev.parent);
Do you really need a special accessor function to get the regmap like this?
If you just use syscon you get these kind of helpers for free. I don't know
if you can use syscon though, just a suggestion.
> + priv->chip_num = pdata->chip_num;
As mentioned, why not just use pdev->id
> + gpio_chip = &priv->gpio_chip;
> + gpio_chip->label = "gpio-dmec";
You set the label
> + gpio_chip->owner = THIS_MODULE;
> + gpio_chip->parent = dev;
> + gpio_chip->label = dev_name(dev);
You set the label again?
> + gpio_chip->can_sleep = true;
> +
> + gpio_chip->base = pdata->gpio_base;
NAK. Use -1
> +#ifdef CONFIG_PM
> +static int dmec_gpio_suspend(struct platform_device *pdev, pm_message_t state)
> +{
> + struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
> + struct regmap *regmap = p->regmap;
> + struct dmec_reg_ctx *ctx = &p->regs;
> +
> + regmap_read(regmap, DMEC_GPIO_BASE(p), &ctx->dat);
> + regmap_read(regmap, DMEC_GPIO_DIR_OFFSET(p), &ctx->dir);
> + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->imask);
> + regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), &ctx->emask[0]);
> + regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, &ctx->emask[1]);
> + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->icfg[0]);
> + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, &ctx->icfg[1]);
> +
> + devm_free_irq(&pdev->dev, p->irq, p);
That seems a bit violent.
> +static int dmec_gpio_resume(struct platform_device *pdev)
> +{
> + struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
> + struct regmap *regmap = p->regmap;
> + struct dmec_reg_ctx *ctx = &p->regs;
> + int ret;
> +
> + regmap_write(regmap, DMEC_GPIO_BASE(p), ctx->dat);
> + regmap_write(regmap, DMEC_GPIO_DIR_OFFSET(p), ctx->dir);
> + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->icfg[0]);
> + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, ctx->icfg[1]);
> + regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), ctx->emask[0]);
> + regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, ctx->emask[1]);
> + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->imask);
> + regmap_write(regmap, DMEC_GPIO_EVTSTA_OFFSET(p), 0xff);
> +
> + ret = devm_request_threaded_irq(&pdev->dev, p->irq,
> + NULL, dmec_gpio_irq_handler,
> + IRQF_ONESHOT | IRQF_SHARED,
> + dev_name(&pdev->dev), p);
> + if (ret)
> + dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
Re-requesting the IRQ for every suspend/resume cycle?
That's not right.
Look into the wakeup API. You need to tell the core whether this IRQ
should be masked during suspend or not, the default is to mask it I think.
This is too big hammer to solve that.
> +static struct platform_driver dmec_gpio_driver = {
> + .driver = {
> + .name = "dmec-gpio",
> + .owner = THIS_MODULE,
> + },
> + .probe = dmec_gpio_probe,
> + .remove = dmec_gpio_remove,
> + .suspend = dmec_gpio_suspend,
> + .resume = dmec_gpio_resume,
> +};
Don't use the legacy suspend/resume callbacks.
Use the DEV_PM_OPS directly in .pm in .driver above. It should
work the same.
(You probably need to fix this on the other patches too.)
Yours,
Linus Walleij
[toc] | [prev] | [next] | [standalone]
| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-31 10:00 +0100 |
| Subject | Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec |
| Message-ID | <sygBI-8tq-11@gated-at.bofh.it> |
| In reply to | #1511605 |
On Sat, Oct 29, 2016 at 11:05:29AM +0200, Linus Walleij wrote:
> On Thu, Oct 27, 2016 at 12:47 PM, Zahari Doychev
> <zahari.doychev@linux.com> wrote:
>
> > This is support for the gpio functionality found on the Data Modul embedded
> > controllers
> >
> > Signed-off-by: Zahari Doychev <zahari.doychev@linux.com>
> > ---
> > drivers/staging/dmec/Kconfig | 10 +-
> > drivers/staging/dmec/Makefile | 1 +-
> > drivers/staging/dmec/dmec.h | 5 +-
> > drivers/staging/dmec/gpio-dmec.c | 390 ++++++++++++++++++++++++++++++++-
>
Thanks for the review.
> I guess Greg has already asked, but why is this in staging?
> The driver doesn't seem very complex or anything, it would not
> be overly troublesome to get it into the proper kernel subsystems.
I was unsure what was the right way to go with this. Next time I will move it
out of staging.
>
> > +config GPIO_DMEC
> > + tristate "Data Modul GPIO"
> > + depends on MFD_DMEC && GPIOLIB
>
> So the depends on GPIOLIB can go away if you just put it into
> drivers/gpio with the rest.
>
> > +struct dmec_gpio_platform_data {
> > + int gpio_base;
>
> NAK, always use -1. No hardcoding the GPIO base other than on
> legacy systems.
>
> > + int chip_num;
>
> I suspect you may not need this either. struct platform_device
> already contains a ->id field, just use that when instantiating
> your driver if you need an instance number.
>
> So I think you need zero platform data for this.
>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/io.h>
> > +#include <linux/slab.h>
> > +#include <linux/errno.h>
> > +#include <linux/acpi.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/gpio.h>
>
> You should only need <linux/gpio/driver.h>
>
> > +#ifdef CONFIG_PM
> > +struct dmec_reg_ctx {
> > + u32 dat;
> > + u32 dir;
> > + u32 imask;
> > + u32 icfg[2];
> > + u32 emask[2];
> > +};
> > +#endif
> > +
> > +struct dmec_gpio_priv {
> > + struct regmap *regmap;
> > + struct gpio_chip gpio_chip;
> > + struct irq_chip irq_chip;
> > + unsigned int chip_num;
> > + unsigned int irq;
> > + u8 ver;
> > +#ifdef CONFIG_PM
> > + struct dmec_reg_ctx regs;
> > +#endif
> > +};
>
> The #ifdef for saving the state is a bit kludgy. Can't you just have it there
> all the time? Or is this a footprint-sensitive system?
It will be no problem to have it always there.
>
> > +static int dmec_gpio_get(struct gpio_chip *gc, unsigned int offset)
> > +{
> > + struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
> > + gpio_chip);
>
> Use the new pattern with
>
> struct dmec_gpio_priv *priv = gpiochip_get_data(gc);
>
> This needs you to use devm_gpiochip_add_data() below.
>
> > +static int dmec_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> > +{
> > + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> > + struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
> > + gpio_chip);
> > + struct regmap *regmap = priv->regmap;
> > + unsigned int offset, mask, val;
> > +
> > + offset = DMEC_GPIO_IRQTYPE_OFFSET(priv) + (d->hwirq >> 2);
> > + mask = ((d->hwirq & 3) << 1);
> > +
> > + regmap_read(regmap, offset, &val);
> > +
> > + val &= ~(3 << mask);
> > + switch (type & IRQ_TYPE_SENSE_MASK) {
> > + case IRQ_TYPE_LEVEL_LOW:
> > + break;
> > + case IRQ_TYPE_EDGE_RISING:
> > + val |= (1 << mask);
> > + break;
> > + case IRQ_TYPE_EDGE_FALLING:
> > + val |= (2 << mask);
> > + break;
> > + case IRQ_TYPE_EDGE_BOTH:
> > + val |= (3 << mask);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + regmap_write(regmap, offset, val);
> > +
> > + return 0;
> > +}
>
> This chip uses handle_simple_irq() which is fine if the chip really has no
> edge detector ACK register.
>
> What some chips have is a special register to clearing (ACK:ing) the edge
> IRQ which makes it possible for a new IRQ to be handled as soon as
> that has happened, and those need to use handle_edge_irq() for edge IRQs
> and handle_level_irq() for level IRQs, with the side effect that the edge
> IRQ path will additionally call the .irq_ack() callback on the irqchip
> when handle_edge_irq() is used. In this case we set handle_bad_irq()
> as default handler and set up the right handler i .set_type().
>
> Look at drivers/gpio/gpio-pl061.c for an example.
>
> If you DON'T have a special edge ACK register, keep it like this.
What is the difference between this special edge ACK register and the normal
interrupt ACK register? I think I do not have such dedicated register
but I will have to check this again.
>
> > +static irqreturn_t dmec_gpio_irq_handler(int irq, void *dev_id)
> > +{
> > + struct dmec_gpio_priv *p = dev_id;
> > + struct irq_domain *d = p->gpio_chip.irqdomain;
> > + unsigned int irqs_handled = 0;
> > + unsigned int val = 0, stat = 0;
> > +
> > + regmap_read(p->regmap, DMEC_GPIO_IRQSTA_OFFSET(p), &val);
> > + stat = val;
> > + while (stat) {
> > + int line = __ffs(stat);
> > + int child_irq = irq_find_mapping(d, line);
> > +
> > + handle_nested_irq(child_irq);
> > + stat &= ~(BIT(line));
> > + irqs_handled++;
> > + }
>
> I think you should re-read the status register in the loop. An IRQ may
> appear while you are reading.
The irqs are signalled over the SERIRQ of the LPC bus. Wnen irq comes in, it
should be acknowledged then the embedded controller can trigger the next one.
Nevertheless I will look at it and fix it if necessary.
>
> > +static int dmec_gpio_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct dmec_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > + struct dmec_gpio_priv *priv;
> > + struct gpio_chip *gpio_chip;
> > + struct irq_chip *irq_chip;
> > + int ret = 0;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->regmap = dmec_get_regmap(pdev->dev.parent);
>
> Do you really need a special accessor function to get the regmap like this?
> If you just use syscon you get these kind of helpers for free. I don't know
> if you can use syscon though, just a suggestion.
The I/O memory is mapped in the mfd driver. The addresing mode is also set
there which should be the same for all child devices. So in this way I have
dependcy between the mfd and the rest of the drivers. I am not sure that I
can use syscon as the driver is getting its resources from acpi.
>
> > + priv->chip_num = pdata->chip_num;
>
> As mentioned, why not just use pdev->id
>
> > + gpio_chip = &priv->gpio_chip;
> > + gpio_chip->label = "gpio-dmec";
>
> You set the label
>
> > + gpio_chip->owner = THIS_MODULE;
> > + gpio_chip->parent = dev;
> > + gpio_chip->label = dev_name(dev);
>
> You set the label again?
>
> > + gpio_chip->can_sleep = true;
> > +
> > + gpio_chip->base = pdata->gpio_base;
>
> NAK. Use -1
>
> > +#ifdef CONFIG_PM
> > +static int dmec_gpio_suspend(struct platform_device *pdev, pm_message_t state)
> > +{
> > + struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
> > + struct regmap *regmap = p->regmap;
> > + struct dmec_reg_ctx *ctx = &p->regs;
> > +
> > + regmap_read(regmap, DMEC_GPIO_BASE(p), &ctx->dat);
> > + regmap_read(regmap, DMEC_GPIO_DIR_OFFSET(p), &ctx->dir);
> > + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->imask);
> > + regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), &ctx->emask[0]);
> > + regmap_read(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, &ctx->emask[1]);
> > + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), &ctx->icfg[0]);
> > + regmap_read(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, &ctx->icfg[1]);
> > +
> > + devm_free_irq(&pdev->dev, p->irq, p);
>
> That seems a bit violent.
>
> > +static int dmec_gpio_resume(struct platform_device *pdev)
> > +{
> > + struct dmec_gpio_priv *p = platform_get_drvdata(pdev);
> > + struct regmap *regmap = p->regmap;
> > + struct dmec_reg_ctx *ctx = &p->regs;
> > + int ret;
> > +
> > + regmap_write(regmap, DMEC_GPIO_BASE(p), ctx->dat);
> > + regmap_write(regmap, DMEC_GPIO_DIR_OFFSET(p), ctx->dir);
> > + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->icfg[0]);
> > + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p) + 1, ctx->icfg[1]);
> > + regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p), ctx->emask[0]);
> > + regmap_write(regmap, DMEC_GPIO_IRQTYPE_OFFSET(p) + 1, ctx->emask[1]);
> > + regmap_write(regmap, DMEC_GPIO_IRQCFG_OFFSET(p), ctx->imask);
> > + regmap_write(regmap, DMEC_GPIO_EVTSTA_OFFSET(p), 0xff);
> > +
> > + ret = devm_request_threaded_irq(&pdev->dev, p->irq,
> > + NULL, dmec_gpio_irq_handler,
> > + IRQF_ONESHOT | IRQF_SHARED,
> > + dev_name(&pdev->dev), p);
> > + if (ret)
> > + dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
>
> Re-requesting the IRQ for every suspend/resume cycle?
>
> That's not right.
>
> Look into the wakeup API. You need to tell the core whether this IRQ
> should be masked during suspend or not, the default is to mask it I think.
>
> This is too big hammer to solve that.
>
> > +static struct platform_driver dmec_gpio_driver = {
> > + .driver = {
> > + .name = "dmec-gpio",
> > + .owner = THIS_MODULE,
> > + },
> > + .probe = dmec_gpio_probe,
> > + .remove = dmec_gpio_remove,
> > + .suspend = dmec_gpio_suspend,
> > + .resume = dmec_gpio_resume,
> > +};
>
> Don't use the legacy suspend/resume callbacks.
>
> Use the DEV_PM_OPS directly in .pm in .driver above. It should
> work the same.
>
> (You probably need to fix this on the other patches too.)
>
Thanks I will change this.
Regards Zahari
> Yours,
> Linus Walleij
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-10-31 13:30 +0100 |
| Subject | Re: [RFC PATCH 3/5] gpio-dmec: gpio support for dmec |
| Message-ID | <syjSV-2kD-17@gated-at.bofh.it> |
| In reply to | #1512411 |
On Mon, Oct 31, 2016 at 9:50 AM, Zahari Doychev
<zahari.doychev@linux.com> wrote:
> On Sat, Oct 29, 2016 at 11:05:29AM +0200, Linus Walleij wrote:
>> > +static int dmec_gpio_irq_set_type(struct irq_data *d, unsigned int type)
>> > +{
>> > + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
>> > + struct dmec_gpio_priv *priv = container_of(gc, struct dmec_gpio_priv,
>> > + gpio_chip);
>> > + struct regmap *regmap = priv->regmap;
>> > + unsigned int offset, mask, val;
>> > +
>> > + offset = DMEC_GPIO_IRQTYPE_OFFSET(priv) + (d->hwirq >> 2);
>> > + mask = ((d->hwirq & 3) << 1);
>> > +
>> > + regmap_read(regmap, offset, &val);
>> > +
>> > + val &= ~(3 << mask);
>> > + switch (type & IRQ_TYPE_SENSE_MASK) {
>> > + case IRQ_TYPE_LEVEL_LOW:
>> > + break;
>> > + case IRQ_TYPE_EDGE_RISING:
>> > + val |= (1 << mask);
>> > + break;
>> > + case IRQ_TYPE_EDGE_FALLING:
>> > + val |= (2 << mask);
>> > + break;
>> > + case IRQ_TYPE_EDGE_BOTH:
>> > + val |= (3 << mask);
>> > + break;
>> > + default:
>> > + return -EINVAL;
>> > + }
>> > +
>> > + regmap_write(regmap, offset, val);
>> > +
>> > + return 0;
>> > +}
>>
>> This chip uses handle_simple_irq() which is fine if the chip really has no
>> edge detector ACK register.
>>
>> What some chips have is a special register to clearing (ACK:ing) the edge
>> IRQ which makes it possible for a new IRQ to be handled as soon as
>> that has happened, and those need to use handle_edge_irq() for edge IRQs
>> and handle_level_irq() for level IRQs, with the side effect that the edge
>> IRQ path will additionally call the .irq_ack() callback on the irqchip
>> when handle_edge_irq() is used. In this case we set handle_bad_irq()
>> as default handler and set up the right handler i .set_type().
>>
>> Look at drivers/gpio/gpio-pl061.c for an example.
>>
>> If you DON'T have a special edge ACK register, keep it like this.
>
> What is the difference between this special edge ACK register and the normal
> interrupt ACK register?
With level interrupts there is seldom use of any ACK register.
They will by definition just hold the line low until the clients stop
asserting their IRQs.
With edge triggered interrupts, you can have a transient event so
that you need an ACK register to tell the hardware that you have
seen and acknowledged this IRQ, so it can go ahead and fire a
second IRQ on the same line while you are still processing the
first one.
> I think I do not have such dedicated register
> but I will have to check this again.
Read the documentation for the register(s) and see what the
use case is.
>> > +static int dmec_gpio_probe(struct platform_device *pdev)
>> > +{
>> > + struct device *dev = &pdev->dev;
>> > + struct dmec_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
>> > + struct dmec_gpio_priv *priv;
>> > + struct gpio_chip *gpio_chip;
>> > + struct irq_chip *irq_chip;
>> > + int ret = 0;
>> > +
>> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> > + if (!priv)
>> > + return -ENOMEM;
>> > +
>> > + priv->regmap = dmec_get_regmap(pdev->dev.parent);
>>
>> Do you really need a special accessor function to get the regmap like this?
>> If you just use syscon you get these kind of helpers for free. I don't know
>> if you can use syscon though, just a suggestion.
>
> The I/O memory is mapped in the mfd driver. The addresing mode is also set
> there which should be the same for all child devices. So in this way I have
> dependcy between the mfd and the rest of the drivers. I am not sure that I
> can use syscon as the driver is getting its resources from acpi.
OK.
Yours,
Linus Walleij
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| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-27 16:10 +0200 |
| Subject | [RFC PATCH 1/5] dmec: add DMO mfd driver |
| Message-ID | <swTxx-2VB-49@gated-at.bofh.it> |
| In reply to | #1510192 |
This is a core mfd driver for the on board embedded controllers found on the
Data Modul embedded CPU modules. The embedded controller may provide the
following functions: i2c bus, gpio, watchdog, uart and rtm.
Signed-off-by: Zahari Doychev <zahari.doychev@linux.com>
---
drivers/staging/Kconfig | 2 +-
drivers/staging/Makefile | 1 +-
drivers/staging/dmec/Kconfig | 9 +-
drivers/staging/dmec/Makefile | 1 +-
drivers/staging/dmec/dmec-core.c | 500 ++++++++++++++++++++++++++++++++-
drivers/staging/dmec/dmec.h | 6 +-
6 files changed, 519 insertions(+), 0 deletions(-)
create mode 100644 drivers/staging/dmec/Kconfig
create mode 100644 drivers/staging/dmec/Makefile
create mode 100644 drivers/staging/dmec/dmec-core.c
create mode 100644 drivers/staging/dmec/dmec.h
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 58a7b35..d95bee2 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -106,4 +106,6 @@ source "drivers/staging/greybus/Kconfig"
source "drivers/staging/vc04_services/Kconfig"
+source "drivers/staging/dmec/Kconfig"
+
endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 2fa9745..73b4833 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_ISDN_I4L) += i4l/
obj-$(CONFIG_KS7010) += ks7010/
obj-$(CONFIG_GREYBUS) += greybus/
obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/
+obj-$(CONFIG_MFD_DMEC) += dmec/
diff --git a/drivers/staging/dmec/Kconfig b/drivers/staging/dmec/Kconfig
new file mode 100644
index 0000000..3641907
--- /dev/null
+++ b/drivers/staging/dmec/Kconfig
@@ -0,0 +1,9 @@
+config MFD_DMEC
+ tristate "Data Modul Embedded Controller MFD"
+ select MFD_CORE
+ help
+ Say Y here to enable support for a Data Module embedded controller
+ found on Data Module CPU Modules
+
+ To compile this driver as a module, say M here: the module will be
+ called dmec
diff --git a/drivers/staging/dmec/Makefile b/drivers/staging/dmec/Makefile
new file mode 100644
index 0000000..859163b
--- /dev/null
+++ b/drivers/staging/dmec/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MFD_DMEC) += dmec-core.o
diff --git a/drivers/staging/dmec/dmec-core.c b/drivers/staging/dmec/dmec-core.c
new file mode 100644
index 0000000..40f5481
--- /dev/null
+++ b/drivers/staging/dmec/dmec-core.c
@@ -0,0 +1,500 @@
+/*
+ * dmec-core: Data Modul AG mfd embedded controller driver
+ *
+ * Zahari Doychev <zahari.doychev@linux.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <linux/platform_device.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/dmi.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <linux/acpi.h>
+#include <linux/nls.h>
+#include "dmec.h"
+
+#define DMEC_LBAR 0x00 /* Index addressing 4 bytes */
+#define DMEC_ECVER0 0x04
+#define DMEC_ECVER1 0x05
+#define DMEC_ECFTR0 0x07
+#define DMEC_ECFTR1 0x08
+#define DMEC_FPGAVER0 0x0c
+#define DMEC_FPGAVER1 0x0d
+#define DMEC_FPGABLD0 0x0e
+#define DMEC_FPGABLD1 0x0f
+#define DMEC_IRQCFG0 0x10
+#define DMEC_IRQCFG1 0x11
+#define DMEC_RTM_START 0x60
+#define DMEC_RTM_END 0x6e
+
+#define DMEC_MAX_GPIO_CHIPS 2
+
+#define DMEC_VERSION_LEN 32
+
+#define DMEC_FEATURE_BIT_I2C BIT(0)
+#define DMEC_FEATURE_BIT_WDT BIT(4)
+#define DMEC_FEATURE_BIT_GPIO (3 << 6)
+
+#define DMEC_REG_MAX 0x7f
+#define DMEC_MAX_DEVS ARRAY_SIZE(dmec_devs)
+#define DMEC_MAX_IO_RES 2
+#define DMEC_STR_SZ 128
+
+static bool i_addr;
+module_param(i_addr, bool, 0644);
+MODULE_PARM_DESC(i_addr, "Enable register index addressing usage");
+
+static const char * const fw_types[] = {"release", "custom",
+ "debug", "reserved"};
+
+enum dmec_cells {
+ DMEC_I2C = 0,
+ DMEC_GPIOA,
+ DMEC_GPIOB,
+ DMEC_WDT,
+ DMEC_RTM
+};
+
+struct dmec_features {
+ unsigned int i2c_buses:2;
+ unsigned int uarts:2;
+ unsigned int wdt:1;
+ unsigned int rsvd1:1;
+ unsigned int gpio_chips:2;
+ unsigned int spi_buses:2;
+ unsigned int can_buses:2;
+ unsigned int rsvd2:1;
+ unsigned int nmi:1;
+ unsigned int sci:1;
+ unsigned int smi:1;
+};
+
+struct dmec_info {
+ unsigned int ec_ver:4;
+ unsigned int ec_rev:4;
+ unsigned int ec_num:2;
+ unsigned int ec_type:2;
+ unsigned int ec_dbg:4;
+ u16 fpga_ver;
+ u16 fpga_bld;
+ char version[DMEC_VERSION_LEN];
+};
+
+struct dmec_device_data {
+ void __iomem *io_base;
+ void __iomem *io_index;
+ void __iomem *io_data;
+ union {
+ u16 feature_mask;
+ struct dmec_features ftr;
+ } u;
+ struct device *dev;
+ struct dmec_info info;
+ struct regmap *regmap;
+ /* use index addressing for register access if set*/
+ bool i_addr;
+};
+
+struct dmec_platform_data {
+ int (*get_info)(struct dmec_device_data *);
+ int (*register_cells)(struct dmec_device_data *);
+};
+
+static struct dmec_i2c_platform_data dmec_i2c_data = {
+ .reg_shift = 0, /* two bytes between registers */
+ .reg_io_width = 1, /* register io read/write width */
+ .clock_khz = 50000, /* input clock of 50MHz */
+};
+
+static struct dmec_gpio_platform_data dmec_gpio_pdata[DMEC_MAX_GPIO_CHIPS] = {
+ {
+ .gpio_base = -1,
+ .chip_num = 0,
+ },
+ {
+ .gpio_base = -1,
+ .chip_num = 1,
+ },
+};
+
+/* The gpio block can use up to DMEC_GPIO_MAX_IRQS APIC irqs */
+static struct resource dmec_gpio_irq_resources[DMEC_MAX_GPIO_CHIPS];
+static struct resource dmec_wdt_irq_resource;
+static struct resource dmec_i2c_irq_resource;
+
+static struct mfd_cell dmec_devs[] = {
+ [DMEC_I2C] = {
+ .name = "dmec-i2c",
+ .platform_data = &dmec_i2c_data,
+ .pdata_size = sizeof(dmec_i2c_data),
+ .resources = &dmec_i2c_irq_resource,
+ .num_resources = 1,
+ },
+ [DMEC_GPIOA] = {
+ .name = "dmec-gpio",
+ .platform_data = &dmec_gpio_pdata[0],
+ .pdata_size = sizeof(struct dmec_gpio_platform_data),
+ .resources = &dmec_gpio_irq_resources[0],
+ .num_resources = 1,
+ },
+ [DMEC_GPIOB] = {
+ .name = "dmec-gpio",
+ .platform_data = &dmec_gpio_pdata[1],
+ .pdata_size = sizeof(struct dmec_gpio_platform_data),
+ .resources = &dmec_gpio_irq_resources[1],
+ .num_resources = 1,
+ },
+ [DMEC_WDT] = {
+ .name = "dmec-wdt",
+ .resources = &dmec_wdt_irq_resource,
+ .num_resources = 1,
+ },
+ [DMEC_RTM] = {
+ .name = "dmec-rtm",
+ },
+};
+
+static void dmec_get_gpio_irqs(struct dmec_device_data *ec)
+{
+ unsigned int irq, val;
+
+ regmap_read(ec->regmap, DMEC_IRQCFG1, &val);
+ irq = (val >> 4) & 0xf;
+ dmec_gpio_irq_resources[0].start = irq;
+ dmec_gpio_irq_resources[0].end = irq;
+ dmec_gpio_irq_resources[0].flags = IORESOURCE_IRQ;
+ irq = val & 0xf;
+ dmec_gpio_irq_resources[1].start = irq;
+ dmec_gpio_irq_resources[1].end = irq;
+ dmec_gpio_irq_resources[1].flags = IORESOURCE_IRQ;
+}
+
+static void dmec_get_wdt_irq(struct dmec_device_data *ec)
+{
+ unsigned int irq, val;
+
+ regmap_read(ec->regmap, DMEC_IRQCFG0, &val);
+ irq = val & 0xf;
+ dmec_wdt_irq_resource.start = irq;
+ dmec_wdt_irq_resource.end = irq;
+ dmec_wdt_irq_resource.flags = IORESOURCE_IRQ;
+}
+
+static void dmec_get_i2c_irq(struct dmec_device_data *ec)
+{
+ unsigned int irq, val;
+
+ regmap_read(ec->regmap, DMEC_IRQCFG0, &val);
+ irq = (val >> 4) & 0xf;
+ dmec_i2c_irq_resource.start = irq;
+ dmec_i2c_irq_resource.end = irq;
+ dmec_i2c_irq_resource.flags = IORESOURCE_IRQ;
+}
+
+static int dmec_rtm_detect(struct dmec_device_data *ec)
+{
+ unsigned int val, n;
+
+ for (n = DMEC_RTM_START; n <= DMEC_RTM_END; n++) {
+ regmap_read(ec->regmap, n, &val);
+ if (val != 0xff)
+ return 1;
+ }
+
+ return 0;
+}
+
+static int dmec_register_cells(struct dmec_device_data *ec)
+{
+ struct mfd_cell cells[DMEC_MAX_DEVS];
+ u8 n_dev = 0;
+
+ if (ec->u.feature_mask & DMEC_FEATURE_BIT_I2C) {
+ dmec_get_i2c_irq(ec);
+ dmec_devs[DMEC_I2C].id = n_dev;
+ cells[n_dev++] = dmec_devs[DMEC_I2C];
+ }
+
+ if (ec->u.feature_mask & DMEC_FEATURE_BIT_GPIO) {
+ dmec_get_gpio_irqs(ec);
+ dmec_devs[DMEC_GPIOA].id = n_dev;
+ cells[n_dev++] = dmec_devs[DMEC_GPIOA];
+ if (ec->u.ftr.gpio_chips > 1) {
+ dmec_devs[DMEC_GPIOB].id = n_dev;
+ cells[n_dev++] = dmec_devs[DMEC_GPIOB];
+ }
+ }
+
+ if (ec->u.feature_mask & DMEC_FEATURE_BIT_WDT) {
+ dmec_get_wdt_irq(ec);
+ dmec_devs[DMEC_WDT].id = n_dev;
+ cells[n_dev++] = dmec_devs[DMEC_WDT];
+ }
+
+ if (dmec_rtm_detect(ec)) {
+ dmec_devs[DMEC_RTM].id = n_dev;
+ cells[n_dev++] = dmec_devs[DMEC_RTM];
+ }
+
+ return devm_mfd_add_devices(ec->dev, 0,
+ cells, n_dev, NULL, 0, NULL);
+}
+
+static int dmec_read16(struct dmec_device_data *ec, u8 reg)
+{
+ unsigned int lsb, msb;
+ int ret;
+
+ ret = regmap_read(ec->regmap, reg, &lsb);
+ ret = regmap_read(ec->regmap, reg + 0x1, &msb);
+
+ return (msb << 8) | lsb;
+}
+
+static int dmec_get_info(struct dmec_device_data *ec)
+{
+ unsigned int ver0, ver1;
+
+ regmap_read(ec->regmap, DMEC_ECVER0, &ver0);
+ regmap_read(ec->regmap, DMEC_ECVER1, &ver1);
+ if (ver0 == 0xff && ver1 == 0xff)
+ return -ENODEV;
+
+ ec->u.feature_mask = dmec_read16(ec, DMEC_ECFTR0);
+
+ ec->info.ec_ver = (ver0 >> 4) & 0xf;
+ ec->info.ec_rev = ver0 & 0xf;
+ ec->info.ec_num = ver1 & 0x3;
+ ec->info.ec_type = (ver1 >> 2) & 0x3;
+ ec->info.ec_dbg = (ver1 >> 4) & 0xf;
+
+ ec->info.fpga_ver = dmec_read16(ec, DMEC_FPGAVER0);
+ ec->info.fpga_bld = dmec_read16(ec, DMEC_FPGABLD0);
+
+ return 0;
+}
+
+static int dmec_regmap_reg_read(void *context,
+ unsigned int reg, unsigned int *val)
+{
+ struct dmec_device_data *ec = context;
+
+ if (ec->i_addr) {
+ iowrite8(reg, ec->io_index);
+ *val = ioread8(ec->io_data);
+ } else {
+ *val = ioread8(ec->io_base + reg);
+ }
+
+ return 0;
+}
+
+static int dmec_regmap_reg_write(void *context,
+ unsigned int reg, unsigned int val)
+{
+ struct dmec_device_data *ec = context;
+
+ if (ec->i_addr) {
+ iowrite8(reg, ec->io_index);
+ iowrite8(val, ec->io_data);
+ } else {
+ iowrite8(val, ec->io_base + reg);
+ }
+
+ return 0;
+}
+
+struct regmap *dmec_get_regmap(struct device *dev)
+{
+ struct dmec_device_data *ec = dev_get_drvdata(dev);
+
+ return ec->regmap;
+}
+EXPORT_SYMBOL(dmec_get_regmap);
+
+static ssize_t dmec_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dmec_device_data *ec = dev_get_drvdata(dev);
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n", ec->info.version);
+}
+
+static ssize_t dmec_fw_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dmec_device_data *ec = dev_get_drvdata(dev);
+
+ return scnprintf(buf, PAGE_SIZE,
+ "ver: %u.%u\n"
+ "ec: %u\n"
+ "type: %s\n"
+ "debug: %u\n"
+ "fpga ver: %x\n"
+ "fpga build: %x\n",
+ ec->info.ec_ver,
+ ec->info.ec_rev,
+ ec->info.ec_num,
+ fw_types[ec->info.ec_type % (ARRAY_SIZE(fw_types) - 1)],
+ ec->info.ec_dbg,
+ ec->info.fpga_ver,
+ ec->info.fpga_bld);
+}
+
+static ssize_t dmec_features_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct dmec_device_data *ec = dev_get_drvdata(dev);
+ struct dmec_features *ftr = &ec->u.ftr;
+
+ return scnprintf(buf, PAGE_SIZE,
+ "i2c buses: %2u\n"
+ "uarts: %2u\n"
+ "watchdog: %2u\n"
+ "gpio chips: %2u\n"
+ "spi buses: %2u\n"
+ "can buses: %2u\n"
+ "nmi: %2u\n"
+ "sci: %2u\n"
+ "smi: %2u\n",
+ ftr->i2c_buses, ftr->uarts, ftr->wdt,
+ ftr->gpio_chips, ftr->spi_buses, ftr->can_buses,
+ ftr->nmi, ftr->sci, ftr->smi);
+}
+
+static DEVICE_ATTR(version, 0444, dmec_version_show, NULL);
+static DEVICE_ATTR(fw_type, 0444, dmec_fw_type_show, NULL);
+static DEVICE_ATTR(features, 0444, dmec_features_show, NULL);
+
+static struct attribute *dmec_attributes[] = {
+ &dev_attr_version.attr,
+ &dev_attr_fw_type.attr,
+ &dev_attr_features.attr,
+ NULL
+};
+
+static const struct attribute_group ec_attr_group = {
+ .attrs = dmec_attributes,
+};
+
+static int dmec_detect_device(struct dmec_device_data *ec)
+{
+ int ret;
+
+ ret = dmec_get_info(ec);
+ if (ret)
+ return ret;
+
+ ret = scnprintf(ec->info.version, sizeof(ec->info.version),
+ "%u.%u",
+ ec->info.ec_ver, ec->info.ec_rev);
+ if (ret < 0)
+ return ret;
+
+ dev_info(ec->dev, "v%s (%s) features: %#x\n",
+ ec->info.version,
+ fw_types[ec->info.ec_type % (ARRAY_SIZE(fw_types) - 1)],
+ ec->u.feature_mask);
+
+ ret = dmec_register_cells(ec);
+ if (ret)
+ return ret;
+
+ return sysfs_create_group(&ec->dev->kobj, &ec_attr_group);
+}
+
+static const struct regmap_config dmec_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .reg_stride = 1,
+ .max_register = DMEC_REG_MAX,
+ .reg_write = dmec_regmap_reg_write,
+ .reg_read = dmec_regmap_reg_read,
+ .cache_type = REGCACHE_NONE,
+ .fast_io = true,
+};
+
+static int dmec_mfd_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dmec_device_data *ec;
+ struct resource *io_idx, *io;
+ int ret;
+
+ ret = platform_device_add_data(pdev, NULL, 0);
+ if (ret)
+ return ret;
+
+ ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
+ if (!ec)
+ return -ENOMEM;
+
+ io_idx = platform_get_resource(pdev, IORESOURCE_IO, 0);
+ if (!io_idx)
+ return -EINVAL;
+
+ io = platform_get_resource(pdev, IORESOURCE_IO, 1);
+ if (!io) {
+ dev_info(dev, "falling back to index addressing\n");
+ ec->io_base = devm_ioport_map(dev, io_idx->start,
+ io_idx->end - io_idx->start);
+ i_addr = true;
+ } else
+ ec->io_base = devm_ioport_map(dev, io->start,
+ io->end - io->start);
+
+ if (IS_ERR(ec->io_base))
+ return PTR_ERR(ec->io_base);
+
+ /* In index mode registers @ 0x0 and 0x2 are used by the BIOS */
+ ec->i_addr = i_addr;
+ ec->io_index = ec->io_base + 1;
+ ec->io_data = ec->io_base + 3;
+ ec->dev = dev;
+
+ ec->regmap = devm_regmap_init(dev, NULL, ec, &dmec_regmap_config);
+ if (IS_ERR(ec->regmap))
+ return PTR_ERR(ec->regmap);
+ regcache_cache_bypass(ec->regmap, true);
+
+ platform_set_drvdata(pdev, ec);
+
+ return dmec_detect_device(ec);
+}
+
+static int dmec_mfd_remove(struct platform_device *pdev)
+{
+ struct dmec_device_data *ec = platform_get_drvdata(pdev);
+
+ sysfs_remove_group(&ec->dev->kobj, &ec_attr_group);
+
+ return 0;
+}
+
+static const struct acpi_device_id dmec_acpi_ids[] = {
+ {"DMEC0001", 0},
+ {"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, dmec_acpi_ids);
+
+static struct platform_driver dmec_driver = {
+ .probe = dmec_mfd_probe,
+ .remove = dmec_mfd_remove,
+ .driver = {
+ .name = "dmec",
+ .acpi_match_table = ACPI_PTR(dmec_acpi_ids)
+ },
+};
+
+module_platform_driver(dmec_driver);
+
+MODULE_DESCRIPTION("DMO embedded controller core driver");
+MODULE_AUTHOR("Zahari Doychev <zahari.doychev@linux.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dmec-core");
diff --git a/drivers/staging/dmec/dmec.h b/drivers/staging/dmec/dmec.h
new file mode 100644
index 0000000..4d8712d
--- /dev/null
+++ b/drivers/staging/dmec/dmec.h
@@ -0,0 +1,6 @@
+#ifndef _LINUX_MFD_DMEC_H
+#define _LINUX_MFD_DMEC_H
+
+struct regmap *dmec_get_regmap(struct device *dev);
+
+#endif
--
git-series 0.8.10
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| From | Greg KH <gregkh@linuxfoundation.org> |
|---|---|
| Date | 2016-10-27 17:20 +0200 |
| Message-ID | <swUDg-3BS-3@gated-at.bofh.it> |
| In reply to | #1510192 |
On Thu, Oct 27, 2016 at 12:47:11PM +0200, Zahari Doychev wrote: > This patch series adds support for the Data Modul Embedded Controller(dmec) > which is implemented within an on board FPGA found on Data Modul embedded > CPU modules. > > The dmec is connected to the host through the LPC bus and its registers are > mapped into the host I/O space. The controller supports two addressing modes: > linear and indexed. > > The driver adds support for the following functionality: > > - i2c > - gpio > - watchdog > - running time meter (rtm) Why do you want these in staging? I need a TODO file listing what needs to be done to the code to get it out of staging, and for someone to agree to work toward that goal. Please resend the series with that information. thanks, greg k-h
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| From | Zahari Doychev <zahari.doychev@linux.com> |
|---|---|
| Date | 2016-10-27 18:00 +0200 |
| Message-ID | <swVfY-3Pm-47@gated-at.bofh.it> |
| In reply to | #1510379 |
On Thu, Oct 27, 2016 at 05:01:51PM +0200, Greg KH wrote: > On Thu, Oct 27, 2016 at 12:47:11PM +0200, Zahari Doychev wrote: > > This patch series adds support for the Data Modul Embedded Controller(dmec) > > which is implemented within an on board FPGA found on Data Modul embedded > > CPU modules. > > > > The dmec is connected to the host through the LPC bus and its registers are > > mapped into the host I/O space. The controller supports two addressing modes: > > linear and indexed. > > > > The driver adds support for the following functionality: > > > > - i2c > > - gpio > > - watchdog > > - running time meter (rtm) > > Why do you want these in staging? I need a TODO file listing what needs > to be done to the code to get it out of staging, and for someone to > agree to work toward that goal. Actually there is no reason to have them in staging. I was not sure what was the right way to go. I just wanted to get some feedback. The drivers have been through a lot of testing so next time I will resend the patches putting each driver in its subsystem. Regards Zahari > > Please resend the series with that information. > > thanks, > > greg k-h
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