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[PATCH v2 0/3] powernv:stop: Use psscr_val,mask provided by firmware

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  [PATCH v2 0/3] powernv:stop: Use psscr_val,mask provided by firmware "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> - 2016-10-27 16:10 +0200
    [PATCH v2 1/3] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> - 2016-10-27 16:20 +0200
    Re: [PATCH v2 0/3] powernv:stop: Use psscr_val,mask provided by firmware "Rafael J. Wysocki" <rjw@rjwysocki.net> - 2016-11-01 05:20 +0100

#1510205 — [PATCH v2 0/3] powernv:stop: Use psscr_val,mask provided by firmware

From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>

Hi,

This is the second iteration of the patchset to use the psscr_val and
psscr_mask provided by the firmware for each of the stop states.

The previous version can be found here: 
https://lkml.org/lkml/2016/9/29/45

The main changes in this version are:

1) Add a helper function in powernv-cpuidle.c to help initialize the
   powernv_states cpuidle table.

2) Handle the older firmware which populates only the Requested Level
   (RL) fields of the psscr and psscr_mask in the device tree. This
   patchset ensures that in the presence of the older firmware, the
   other fields of PSSCR are initalized to sane default values.


Synopsis
==========
In the current implementation, the code for ISA v3.0 stop
implementation has a couple of shortcomings.

a) The code hand-codes the values for ESL,EC,TR,MTL bits of PSSCR and
   uses only the RL field from the firmware. While this is not
   incorrect, since the hand-coded values are legitimate, it is not a
   very flexible design since the firmware has the capability to
   communicate these values via the "ibm,cpu-idle-state-psscr" and
   "ibm,cpu-idle-state-psscr-mask" properties. In case where the
   firmware provides values for these fields that is different from
   the hand-coded values, the current code will not work as intended.

b) Due to issue a), the current code assumes that ESL=EC=1 for all the
   stop states and hence the wakeup from the stop instruction will
   happen at 0x100, the system-reset vector. However, the ISA v3.0
   allows the ESL=EC=0 behaviour where the corresponding stop-state
   loses no state and wakes up from the subsequent instruction. The
   current code doesn't handle this case.
   
This patch series addresses these issues.

The first patch in the series renames the existing
IDLE_STATE_ENTER_SEQ macro to IDLE_STATE_ENTER_SEQ_NORET. It reuses
the name IDLE_STATE_ENTER_SEQ for entering into stop-states which wake
up at the subsequent instruction.

The second patch adds a helper function in cpuidle-powernv.c for
initializing entries of the powernv_states[] table that is passed to
the cpu-idle core. This eliminates some of the code duplication in the
function that discovers and initializes the stop states.

The third patch in the series fixes issues a) and b) by ensuring that
the psscr-value and the psscr-mask provided by the firmware are what
will be used to set a particular stop state. It also adds support for
handling wake-up from stop states which were entered with ESL=EC=0.

The third patch also handles the older firmware which sets only the
Requested Level (RL) field in the psscr and psscr-mask exposed in the
device tree. In the presence of such older firmware, this patch will
set the default sane values for for remaining PSSCR fields (i.e PSLL,
MTL, ESL, EC, and TR).

The skiboot patch populates all the relevant fields in the PSSCR
values and the mask for all the stop states can be found here:
https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html

The patches are based on top of
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes

Gautham R. Shenoy (3):
  powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
  cpuidle:powernv: Add helper function to populate powernv idle states.
  powernv: Pass PSSCR value and mask to power9_idle_stop

 arch/powerpc/include/asm/cpuidle.h       |  42 +++++++++++-
 arch/powerpc/include/asm/processor.h     |   3 +-
 arch/powerpc/kernel/exceptions-64s.S     |   6 +-
 arch/powerpc/kernel/idle_book3s.S        |  41 +++++++-----
 arch/powerpc/platforms/powernv/idle.c    |  81 +++++++++++++++++++----
 arch/powerpc/platforms/powernv/powernv.h |   3 +-
 arch/powerpc/platforms/powernv/smp.c     |  14 ++--
 drivers/cpuidle/cpuidle-powernv.c        | 110 ++++++++++++++++++++-----------
 include/linux/cpuidle.h                  |   1 +
 9 files changed, 220 insertions(+), 81 deletions(-)

-- 
1.9.4

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#1510241 — [PATCH v2 1/3] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>

Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.

On ISA_300, when the ESL and EC bits in the PSSCR are zero, the
CPU is expected to wake up at the next instruction of the idle
instruction.

This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
for a variant that allows resuming operation at the instruction next
to the idle-instruction.

Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/cpuidle.h   |  5 ++++-
 arch/powerpc/kernel/exceptions-64s.S |  6 +++---
 arch/powerpc/kernel/idle_book3s.S    | 10 +++++-----
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h
index 3919332..0a3255b 100644
--- a/arch/powerpc/include/asm/cpuidle.h
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -21,7 +21,7 @@
 
 /* Idle state entry routines */
 #ifdef	CONFIG_PPC_P7_NAP
-#define	IDLE_STATE_ENTER_SEQ(IDLE_INST)				\
+#define IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
 	/* Magic NAP/SLEEP/WINKLE mode enter sequence */	\
 	std	r0,0(r1);					\
 	ptesync;						\
@@ -29,6 +29,9 @@
 1:	cmpd	cr0,r0,r0;					\
 	bne	1b;						\
 	IDLE_INST;						\
+
+#define	IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST)			\
+	IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
 	b	.
 #endif /* CONFIG_PPC_P7_NAP */
 
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index f129408..7a71cdf 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -366,12 +366,12 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
 	lbz	r3,PACA_THREAD_IDLE_STATE(r13)
 	cmpwi	r3,PNV_THREAD_NAP
 	bgt	10f
-	IDLE_STATE_ENTER_SEQ(PPC_NAP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
 	/* No return */
 10:
 	cmpwi	r3,PNV_THREAD_SLEEP
 	bgt	2f
-	IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
 	/* No return */
 
 2:
@@ -385,7 +385,7 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
 	 */
 	ori	r13,r13,1
 	SET_PACA(r13)
-	IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
 	/* No return */
 4:
 #endif
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 72dac0b..be90e2f 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -205,7 +205,7 @@ pnv_enter_arch207_idle_mode:
 	stb	r3,PACA_THREAD_IDLE_STATE(r13)
 	cmpwi	cr3,r3,PNV_THREAD_SLEEP
 	bge	cr3,2f
-	IDLE_STATE_ENTER_SEQ(PPC_NAP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
 	/* No return */
 2:
 	/* Sleep or winkle */
@@ -239,7 +239,7 @@ pnv_fastsleep_workaround_at_entry:
 
 common_enter: /* common code for all the threads entering sleep or winkle */
 	bgt	cr3,enter_winkle
-	IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
 
 fastsleep_workaround_at_entry:
 	ori	r15,r15,PNV_CORE_IDLE_LOCK_BIT
@@ -261,7 +261,7 @@ fastsleep_workaround_at_entry:
 enter_winkle:
 	bl	save_sprs_to_stack
 
-	IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
 
 /*
  * r3 - requested stop state
@@ -280,7 +280,7 @@ power_enter_stop:
 	ld	r4,ADDROFF(pnv_first_deep_stop_state)(r5)
 	cmpd	r3,r4
 	bge	2f
-	IDLE_STATE_ENTER_SEQ(PPC_STOP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
 2:
 /*
  * Entering deep idle state.
@@ -302,7 +302,7 @@ lwarx_loop_stop:
 
 	bl	save_sprs_to_stack
 
-	IDLE_STATE_ENTER_SEQ(PPC_STOP)
+	IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
 
 _GLOBAL(power7_idle)
 	/* Now check if user or arch enabled NAP mode */
-- 
1.9.4

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#1513075

On Thursday, October 27, 2016 02:05:04 PM Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
> 
> Hi,
> 
> This is the second iteration of the patchset to use the psscr_val and
> psscr_mask provided by the firmware for each of the stop states.
> 
> The previous version can be found here: 
> https://lkml.org/lkml/2016/9/29/45
> 
> The main changes in this version are:
> 
> 1) Add a helper function in powernv-cpuidle.c to help initialize the
>    powernv_states cpuidle table.
> 
> 2) Handle the older firmware which populates only the Requested Level
>    (RL) fields of the psscr and psscr_mask in the device tree. This
>    patchset ensures that in the presence of the older firmware, the
>    other fields of PSSCR are initalized to sane default values.
> 
> 
> Synopsis
> ==========
> In the current implementation, the code for ISA v3.0 stop
> implementation has a couple of shortcomings.
> 
> a) The code hand-codes the values for ESL,EC,TR,MTL bits of PSSCR and
>    uses only the RL field from the firmware. While this is not
>    incorrect, since the hand-coded values are legitimate, it is not a
>    very flexible design since the firmware has the capability to
>    communicate these values via the "ibm,cpu-idle-state-psscr" and
>    "ibm,cpu-idle-state-psscr-mask" properties. In case where the
>    firmware provides values for these fields that is different from
>    the hand-coded values, the current code will not work as intended.
> 
> b) Due to issue a), the current code assumes that ESL=EC=1 for all the
>    stop states and hence the wakeup from the stop instruction will
>    happen at 0x100, the system-reset vector. However, the ISA v3.0
>    allows the ESL=EC=0 behaviour where the corresponding stop-state
>    loses no state and wakes up from the subsequent instruction. The
>    current code doesn't handle this case.
>    
> This patch series addresses these issues.
> 
> The first patch in the series renames the existing
> IDLE_STATE_ENTER_SEQ macro to IDLE_STATE_ENTER_SEQ_NORET. It reuses
> the name IDLE_STATE_ENTER_SEQ for entering into stop-states which wake
> up at the subsequent instruction.
> 
> The second patch adds a helper function in cpuidle-powernv.c for
> initializing entries of the powernv_states[] table that is passed to
> the cpu-idle core. This eliminates some of the code duplication in the
> function that discovers and initializes the stop states.
> 
> The third patch in the series fixes issues a) and b) by ensuring that
> the psscr-value and the psscr-mask provided by the firmware are what
> will be used to set a particular stop state. It also adds support for
> handling wake-up from stop states which were entered with ESL=EC=0.
> 
> The third patch also handles the older firmware which sets only the
> Requested Level (RL) field in the psscr and psscr-mask exposed in the
> device tree. In the presence of such older firmware, this patch will
> set the default sane values for for remaining PSSCR fields (i.e PSLL,
> MTL, ESL, EC, and TR).
> 
> The skiboot patch populates all the relevant fields in the PSSCR
> values and the mask for all the stop states can be found here:
> https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html
> 
> The patches are based on top of
> git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes
> 
> Gautham R. Shenoy (3):
>   powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
>   cpuidle:powernv: Add helper function to populate powernv idle states.
>   powernv: Pass PSSCR value and mask to power9_idle_stop

OK

I need someone to review this for me.

Thanks,
Rafael

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