Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1507067 > unrolled thread

[PATCH 0/3] clk: qcom: Add support for hw controlled gdscs/clocks

Started bySricharan R <sricharan@codeaurora.org>
First post2016-10-24 12:20 +0200
Last post2016-10-24 12:20 +0200
Articles 2 — 1 participant

Back to article view | Back to linux.kernel


Contents

  [PATCH 0/3] clk: qcom: Add support for hw controlled gdscs/clocks Sricharan R <sricharan@codeaurora.org> - 2016-10-24 12:20 +0200
    [PATCH 2/3] clk: qcom: Put venus core0/1 gdscs to hw control mode Sricharan R <sricharan@codeaurora.org> - 2016-10-24 12:20 +0200

#1507067 — [PATCH 0/3] clk: qcom: Add support for hw controlled gdscs/clocks

FromSricharan R <sricharan@codeaurora.org>
Date2016-10-24 12:20 +0200
Subject[PATCH 0/3] clk: qcom: Add support for hw controlled gdscs/clocks
Message-ID<svKwh-6el-13@gated-at.bofh.it>
This series adds support for gdscs(powerdomains) that can be configured
in hw controlled mode. So they are turned 'ON' based on needs dynamically,
helping to save power. Also updated the venus video ip's gdsc/clock
data to put them in hw control.

Rajendra Nayak (1):
  clk: qcom: gdsc: Add support for gdscs with HW control

Sricharan R (2):
  clk: qcom: Put venus core0/1 gdscs to hw control mode
  clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks

 drivers/clk/qcom/gdsc.c         | 15 +++++++++++++++
 drivers/clk/qcom/gdsc.h         |  1 +
 drivers/clk/qcom/mmcc-msm8996.c |  4 ++++
 3 files changed, 20 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

[toc] | [next] | [standalone]


#1507070 — [PATCH 2/3] clk: qcom: Put venus core0/1 gdscs to hw control mode

FromSricharan R <sricharan@codeaurora.org>
Date2016-10-24 12:20 +0200
Subject[PATCH 2/3] clk: qcom: Put venus core0/1 gdscs to hw control mode
Message-ID<svKwi-6el-29@gated-at.bofh.it>
In reply to#1507067
The venus video ip's internal core blocks are under the
control of the firmware and their powerdomains needs to be
'ON' only when used by the firmware. So putting it into
hw controlled mode lets this to happen, otherwise the firmware
hangs checking for this.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/mmcc-msm8996.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index ca97e11..41aabe3 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -2945,6 +2945,7 @@ enum {
 		.name = "venus_core0",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.flags = HW_CTRL,
 };
 
 static struct gdsc venus_core1_gdsc = {
@@ -2955,6 +2956,7 @@ enum {
 		.name = "venus_core1",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.flags = HW_CTRL,
 };
 
 static struct gdsc camss_gdsc = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

[toc] | [prev] | [standalone]


Back to top | Article view | linux.kernel


csiph-web