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| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2016-10-17 14:00 +0200 |
| Last post | 2016-10-21 04:40 +0200 |
| Articles | 2 — 2 participants |
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[PATCH 4/6] ARM: sun5i: Add SPI2 pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-17 14:00 +0200
Re: [PATCH 4/6] ARM: sun5i: Add SPI2 pins Chen-Yu Tsai <wens@csie.org> - 2016-10-21 04:40 +0200
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-10-17 14:00 +0200 |
| Subject | [PATCH 4/6] ARM: sun5i: Add SPI2 pins |
| Message-ID | <steKd-2XK-15@gated-at.bofh.it> |
All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the
DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index e374f4fc8073..245cee14cf1d 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -591,6 +591,20 @@
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PE1", "PE2", "PE3";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi2_cs0_pins_a: spi2-cs0@0 {
+ allwinner,pins = "PE0";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
uart3_pins_a: uart3@0 {
allwinner,pins = "PG9", "PG10";
allwinner,function = "uart3";
--
git-series 0.8.10
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-10-21 04:40 +0200 |
| Message-ID | <suxUt-7SK-5@gated-at.bofh.it> |
| In reply to | #1501908 |
On Mon, Oct 17, 2016 at 7:49 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the > DT. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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