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[PATCH 3.12 78/84] KVM: PPC: Book3S PR: Emulate TIR register

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  [PATCH 3.12 78/84] KVM: PPC: Book3S PR: Emulate TIR register Jiri Slaby <jslaby@suse.cz> - 2016-10-17 10:00 +0200

#1501678 — [PATCH 3.12 78/84] KVM: PPC: Book3S PR: Emulate TIR register

From: Alexander Graf <agraf@suse.de>

3.12-stable review patch.  If anyone has any objections, please let me know.

===============

commit a5948fa092a04dfd6b9ee31c99eb6896c158eb08 upstream.

In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
---
 arch/powerpc/kvm/book3s_emulate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 57913b199919..cda2cba56915 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -570,6 +570,7 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
 	case SPRN_MMCR0:
 	case SPRN_MMCR1:
 	case SPRN_MMCR2:
+	case SPRN_TIR:
 #endif
 		*spr_val = 0;
 		break;
-- 
2.10.1

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