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| Started by | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| First post | 2016-10-08 01:50 +0200 |
| Last post | 2016-10-11 18:50 +0200 |
| Articles | 4 — 3 participants |
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[PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Nilay Vaish <nilayvaish@gmail.com> - 2016-10-08 19:20 +0200
Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id "Luck, Tony" <tony.luck@intel.com> - 2016-10-10 18:50 +0200
Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Nilay Vaish <nilayvaish@gmail.com> - 2016-10-11 18:50 +0200
| From | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| Date | 2016-10-08 01:50 +0200 |
| Subject | [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id |
| Message-ID | <spN3Q-7BE-13@gated-at.bofh.it> |
From: Fenghua Yu <fenghua.yu@intel.com> Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> --- Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 4987417..b1c3d69 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes the modified cache line is written to main memory only when it is replaced + +What: /sys/devices/system/cpu/cpu*/cache/index*/id +Date: September 2016 +Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> +Description: Cache id + + The id provides a unique name for a specific instance of + a cache of a particular type. E.g. there may be a level + 3 unified cache on each socket in a server and we may + assign them ids 0, 1, 2, ... + + Note that id value may not be contiguous. E.g. level 1 + caches typically exist per core, but there may not be a + power of two cores on a socket, so these caches may be + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ... + What: /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub_turbo_stat -- 2.5.0
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| From | Nilay Vaish <nilayvaish@gmail.com> |
|---|---|
| Date | 2016-10-08 19:20 +0200 |
| Subject | Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id |
| Message-ID | <sq3rY-1p5-11@gated-at.bofh.it> |
| In reply to | #1497593 |
On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote: > From: Fenghua Yu <fenghua.yu@intel.com> > > Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id. > > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> > Signed-off-by: Tony Luck <tony.luck@intel.com> > --- > Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu > index 4987417..b1c3d69 100644 > --- a/Documentation/ABI/testing/sysfs-devices-system-cpu > +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu > @@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes > the modified cache line is written to main > memory only when it is replaced > > + > +What: /sys/devices/system/cpu/cpu*/cache/index*/id > +Date: September 2016 > +Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> > +Description: Cache id > + > + The id provides a unique name for a specific instance of > + a cache of a particular type. E.g. there may be a level > + 3 unified cache on each socket in a server and we may > + assign them ids 0, 1, 2, ... > + > + Note that id value may not be contiguous. E.g. level 1 > + caches typically exist per core, but there may not be a > + power of two cores on a socket, so these caches may be > + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ... > + While it is ok that the caches are not numbered contiguously, it is unclear how this is related to number of cores on a socket being a power of 2 or not. -- Nilay
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| From | "Luck, Tony" <tony.luck@intel.com> |
|---|---|
| Date | 2016-10-10 18:50 +0200 |
| Subject | Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id |
| Message-ID | <sqLW2-3yz-27@gated-at.bofh.it> |
| In reply to | #1497792 |
On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote: > On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote: > > From: Fenghua Yu <fenghua.yu@intel.com> > > + caches typically exist per core, but there may not be a > > + power of two cores on a socket, so these caches may be > > + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ... > > + > > While it is ok that the caches are not numbered contiguously, it is > unclear how this is related to number of cores on a socket being a > power of 2 or not. That's a side effect of the x86 algorithm to generate the unique ID which uses a shift to put the socket number in some upper bits while leaving the "id within a socket" in the low bits. I don't think it worth documenting here, but I noticed that we don't keep the IDs within a core contguous either. On my 24 core Broadwell they are not 0 ... 23 then a gap from 24 to 31. I actually have on socket 0: 0, 1, 2, 3, 4, 5 8, 9, 10, 11, 12, 13 16, 17, 18, 19, 20, 21 24, 25, 26, 27, 28, 29 -Tony
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| From | Nilay Vaish <nilayvaish@gmail.com> |
|---|---|
| Date | 2016-10-11 18:50 +0200 |
| Subject | Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id |
| Message-ID | <sr8pA-DS-13@gated-at.bofh.it> |
| In reply to | #1498423 |
On 10 October 2016 at 11:45, Luck, Tony <tony.luck@intel.com> wrote: > On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote: >> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote: >> > From: Fenghua Yu <fenghua.yu@intel.com> > >> > + caches typically exist per core, but there may not be a >> > + power of two cores on a socket, so these caches may be >> > + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ... >> > + >> >> While it is ok that the caches are not numbered contiguously, it is >> unclear how this is related to number of cores on a socket being a >> power of 2 or not. > > That's a side effect of the x86 algorithm to generate the unique ID > which uses a shift to put the socket number in some upper bits while > leaving the "id within a socket" in the low bits. > > I don't think it worth documenting here, but I noticed that we don't > keep the IDs within a core contguous either. On my 24 core Broadwell > they are not 0 ... 23 then a gap from 24 to 31. I actually have on > socket 0: > > 0, 1, 2, 3, 4, 5 > 8, 9, 10, 11, 12, 13 > 16, 17, 18, 19, 20, 21 > 24, 25, 26, 27, 28, 29 > Thanks for the info. -- Nilay
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