Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1497607 > unrolled thread
| Started by | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| First post | 2016-10-08 01:50 +0200 |
| Last post | 2016-10-08 02:00 +0200 |
| Articles | 2 on this page of 22 — 6 participants |
Back to article view | Back to linux.kernel
[PATCH v3 00/18] Intel Cache Allocation Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 04/18] x86/intel_rdt: Feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-08 19:20 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-08 20:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-08 22:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Dave Hansen <dave.hansen@intel.com> - 2016-10-10 18:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-10 18:20 +0200
[PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 00:00 +0200
[PATCH v3 16/18] x86/intel_rdt: Add schemata file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 13:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-09 16:10 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 18:30 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-10 21:00 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 13:20 +0200
RE: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-11 17:00 +0200
[PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 20:00 +0200
[RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation "Luck, Tony" <tony.luck@intel.com> - 2016-10-08 02:00 +0200
Page 2 of 2 — ← Prev page 1 [2]
| From | Nilay Vaish <nilayvaish@gmail.com> |
|---|---|
| Date | 2016-10-10 20:00 +0200 |
| Subject | Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system |
| Message-ID | <sqN1L-4aJ-23@gated-at.bofh.it> |
| In reply to | #1497613 |
On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
> diff --git a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> index 28df92e..efcbfe7 100644
> --- a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> +++ b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> @@ -36,6 +36,52 @@ struct kernfs_root *rdt_root;
> struct rdtgroup rdtgroup_default;
> LIST_HEAD(rdt_all_groups);
>
> +/*
> + * Trivial allocator for CLOSIDs. Since h/w only supports
> + * a small number, we can keep a bitmap of free CLOSIDs in
> + * a single integer.
> + */
> +static int closid_free_map;
> +
> +static void closid_init(void)
> +{
> + closid_free_map = BIT_MASK(rdt_max_closid) - 1;
> +
> + /* CLOSID 0 is always reserved for the default group */
> + closid_free_map &= ~1;
> +}
> +
> +int closid_alloc(void)
> +{
> + int closid = ffs(closid_free_map);
> +
> + if (closid == 0)
> + return -ENOSPC;
> + closid--;
> + closid_free_map &= ~(1 << closid);
> +
> + return closid;
> +}
> +
> +static void closid_free(int closid)
> +{
> + closid_free_map |= 1 << closid;
> +}
> +
> +static struct rdtgroup *rdtgroup_alloc(void)
> +{
> + struct rdtgroup *rdtgrp;
> +
> + rdtgrp = kzalloc(sizeof(*rdtgrp), GFP_KERNEL);
> +
> + return rdtgrp;
> +}
> +
> +static void rdtgroup_free(struct rdtgroup *rdtgroup)
> +{
> + kfree(rdtgroup);
> +}
Any reason why you defined the above two functions? Why not call
kzalloc() and kfree() directly?
--
Nilay
[toc] | [prev] | [next] | [standalone]
| From | "Luck, Tony" <tony.luck@intel.com> |
|---|---|
| Date | 2016-10-08 02:00 +0200 |
| Subject | [RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation |
| Message-ID | <spNdv-7Ff-5@gated-at.bofh.it> |
| In reply to | #1497607 |
Just in case you think that part 0010 is a bit complex setting
up all that infrastructure for just the L3 cache and using
for_each_rdt_resource() all over the place to loop over just one
thing. Here's the payoff.
Untested because I don't have a machine handy that supports L2 ... but this
should be all that needs to change for L2 cache allocation (both as an
alternate to L3, or in combination with L3).
Next feature after L2 is not a cache - so rdt_resource will have to grow
some new flags, or perhaps some "->resource_ops()" functions to handle
the pieces that work a bit differently, but the fundamentals should still
apply.
Not-signed-off-yet: Tony Luck
---
arch/x86/include/asm/intel_rdt.h | 2 ++
arch/x86/kernel/cpu/intel_rdt.c | 23 +++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index aefa3a655408..641d32db9d74 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -97,6 +97,7 @@ struct rdt_resource {
#define IA32_L3_QOS_CFG 0xc81
#define IA32_L3_CBM_BASE 0xc90
+#define IA32_L2_CBM_BASE 0xd10
/**
* struct rdt_domain - group of cpus sharing an RDT resource
@@ -134,6 +135,7 @@ extern struct rdt_resource rdt_resources_all[];
enum {
RDT_RESOURCE_L3,
+ RDT_RESOURCE_L2,
};
/* Maximum CLOSID allowed across all enabled resoources */
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 1afca46e080d..c457641c49b6 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -50,6 +50,13 @@ struct rdt_resource rdt_resources_all[] = {
.cache_level = 3
},
{
+ .name = "L2",
+ .domains = domain_init(RDT_RESOURCE_L2),
+ .msr_base = IA32_L2_CBM_BASE,
+ .min_cbm_bits = 1,
+ .cache_level = 2
+ },
+ {
/* NULL terminated */
}
};
@@ -122,6 +129,22 @@ static inline bool get_rdt_resources(struct cpuinfo_x86 *c)
ret = true;
}
+ if (cpu_has(c, X86_FEATURE_CAT_L2)) {
+ union cpuid_0x10_1_eax eax;
+ union cpuid_0x10_1_edx edx;
+ u32 ebx, ecx;
+
+ /* CPUID 0x10.2 fields are same format at 0x10.1 */
+ r = &rdt_resources_all[RDT_RESOURCE_L2];
+ cpuid_count(0x00000010, 2, &eax.full, &ebx, &ecx, &edx.full);
+ r->max_closid = edx.split.cos_max + 1;
+ r->num_closid = r->max_closid;
+ r->cbm_len = eax.split.cbm_len + 1;
+ r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
+ r->enabled = true;
+
+ ret = true;
+ }
return ret;
}
--
2.5.0
[toc] | [prev] | [standalone]
Page 2 of 2 — ← Prev page 1 [2]
Back to top | Article view | linux.kernel
csiph-web