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[PATCH 0/3] Juniper PCI methods

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  [PATCH 0/3] Juniper PCI methods Pantelis Antoniou <pantelis.antoniou@konsulko.com> - 2016-10-07 17:30 +0200
    Re: [PATCH 0/3] Juniper PCI methods Greg Kroah-Hartman <gregkh@linuxfoundation.org> - 2016-10-07 17:30 +0200
    [PATCH 1/3] staging: jnx: PCI quirks for all Juniper platforms Pantelis Antoniou <pantelis.antoniou@konsulko.com> - 2016-10-07 17:30 +0200
    [PATCH 2/3] staging: jnx: Common Juniper PCI methods Pantelis Antoniou <pantelis.antoniou@konsulko.com> - 2016-10-07 17:30 +0200

#1497230 — [PATCH 0/3] Juniper PCI methods

Introduce PCI methods and infrastructure dealing with the
peculiarities of Juniper PTX series of routers.

The Juniper series of routers comprise of both x86 and powerpc
platforms that contain similar hardware components necessitating
common support methods.

Note that this is the first submission and we expect things to be
moved around as required.

This patchset is against mainline as of today: v4.8-9431-g3477d16
and is dependent on the "Juniper prerequisites" and
"Juniper infrastructure" patchsets sent earlier.

Rajat Jain (3):
  staging: jnx: PCI quirks for all Juniper platforms
  staging: jnx: Common Juniper PCI methods
  staging: jnx: pex8xxx I2C interface driver

 drivers/staging/jnx/Kconfig               |  19 ++
 drivers/staging/jnx/Makefile              |   3 +
 drivers/staging/jnx/jnx-chip-pci-quirks.c | 105 ++++++
 drivers/staging/jnx/jnx_common_pci.c      | 244 ++++++++++++++
 drivers/staging/jnx/pex8xxx_i2c.c         | 509 ++++++++++++++++++++++++++++++
 include/linux/jnx/jnx_common_pci.h        |  49 +++
 6 files changed, 929 insertions(+)
 create mode 100644 drivers/staging/jnx/jnx-chip-pci-quirks.c
 create mode 100644 drivers/staging/jnx/jnx_common_pci.c
 create mode 100644 drivers/staging/jnx/pex8xxx_i2c.c
 create mode 100644 include/linux/jnx/jnx_common_pci.h

-- 
1.9.1

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#1497234

On Fri, Oct 07, 2016 at 06:15:53PM +0300, Pantelis Antoniou wrote:
> Introduce PCI methods and infrastructure dealing with the
> peculiarities of Juniper PTX series of routers.

<snip>

Same comments as my previous ones, why is this in staging, and make it
all one patch series please.

thanks,

greg k-h

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#1497248 — [PATCH 1/3] staging: jnx: PCI quirks for all Juniper platforms

From: Rajat Jain <rajatjain@juniper.net>

PCI quirks for all juniper platforms. This is located here
since the same PCI devices are present on both PPC and x86
platforms, so per-arch quirks are not appropriate.

Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
Signed-off-by: Georgi Vlaev <gvlaev@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Shyamshankar Dharmarajan <shyamd@juniper.net>
[Ported from Juniper kernel]
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
---
 drivers/staging/jnx/Kconfig               |   6 ++
 drivers/staging/jnx/Makefile              |   1 +
 drivers/staging/jnx/jnx-chip-pci-quirks.c | 105 ++++++++++++++++++++++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 drivers/staging/jnx/jnx-chip-pci-quirks.c

diff --git a/drivers/staging/jnx/Kconfig b/drivers/staging/jnx/Kconfig
index 5d2b207..f01ef54 100644
--- a/drivers/staging/jnx/Kconfig
+++ b/drivers/staging/jnx/Kconfig
@@ -21,4 +21,10 @@ config JNX_SYSTEM
 
 endmenu
 
+config JNX_CHIP_PCI_QUIRKS
+	bool
+	select PCI_MMCONFIG
+	---help---
+	  PCI quirks for the Juniper chips (ASICs, CPLDs, FPGAs)
+
 endif # JNX_DEVICES
diff --git a/drivers/staging/jnx/Makefile b/drivers/staging/jnx/Makefile
index 52b8286..b29699c 100644
--- a/drivers/staging/jnx/Makefile
+++ b/drivers/staging/jnx/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_JNX_SYSTEM)	+= jnx-subsys.o jnx-board-core.o
+obj-$(CONFIG_JNX_CHIP_PCI_QUIRKS)+= jnx-chip-pci-quirks.o
diff --git a/drivers/staging/jnx/jnx-chip-pci-quirks.c b/drivers/staging/jnx/jnx-chip-pci-quirks.c
new file mode 100644
index 0000000..f90b4c7
--- /dev/null
+++ b/drivers/staging/jnx/jnx-chip-pci-quirks.c
@@ -0,0 +1,105 @@
+/*
+ * Common Juniper ASICs - PCI fixup code
+ *
+ * Guenter Roeck <groeck@juniper.net>
+ * Copyright 2012-2014 Juniper Networks
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License version 2 as published
+ * by the Free Software Foundation
+ */
+
+#include <linux/bitops.h>
+#include <linux/dmi.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/jnx/pci_ids.h>
+
+#define INTEL_DEBUG_REG                 0x8F8
+#define INTEL_DEBUG_REG_IGNORE_GEN      BIT(3)
+
+static void jnx_init_fpga(struct pci_dev *dev)
+{
+	/*
+	 * PCI class reported by Juniper FPGAs (SAM/PAM) is
+	 * "Unassigned class [ff00]". Change it to something more appropriate.
+	 */
+	dev->class = PCI_CLASS_SYSTEM_OTHER << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_SAM,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_SAM_OMEGA,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_SAM_X,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_PAM,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_CBC,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_CBC_P2,
+			jnx_init_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_OMG_CBC,
+			jnx_init_fpga);
+
+static struct dmi_system_id jnx_asic_pci_bug_affected_platforms[] = {
+	{
+		.ident = "Juniper Networks PTX MLC Card",
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "Juniper Networks Inc."),
+			DMI_MATCH(DMI_BOARD_NAME, "0C0A")
+		},
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(dmi, jnx_asic_pci_bug_affected_platforms);
+
+/*
+ * Juniper Broadway ASICs have an issue where they report incorrect gen type
+ * (Gen-1 / Gen-2) for the PCIe link to the root port.
+ * This workaround needs to be applied to each Intel root port which connects
+ * to a juniper ASIC. It causes the root port to ignore the incorrect fields.
+ */
+static void fixup_intel_root_port(struct pci_dev *dev)
+{
+	struct pci_dev *rootport = dev;
+	u32 tmp32;
+	int ret = 0;
+
+	while (!pci_is_root_bus(rootport->bus))
+		rootport = pci_upstream_bridge(rootport);
+
+	if (rootport->vendor != PCI_VENDOR_ID_INTEL)
+		return;
+
+	ret = pci_read_config_dword(rootport, INTEL_DEBUG_REG, &tmp32);
+	tmp32 |= INTEL_DEBUG_REG_IGNORE_GEN;
+	ret |= pci_write_config_dword(rootport, INTEL_DEBUG_REG, tmp32);
+	if (ret)
+		dev_err(&rootport->dev,
+			"Error applying Intel root port quirk! CONFIG_PCI_MMCONFIG not selected?\n");
+}
+
+/*
+ * The TL/TQ ASICs report their device class as PCI_CLASS_NOT_DEFINED.
+ * Linux does not configure memory access for this class,
+ * so we have to ajust it to something acceptable.
+ */
+static void jnx_init_asic(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_NETWORK_OTHER << 8;
+
+	if (dmi_check_system(jnx_asic_pci_bug_affected_platforms))
+		fixup_intel_root_port(dev);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_TF,
+			jnx_init_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_TL,
+			jnx_init_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_TQ,
+			jnx_init_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_OTN_FRAMER,
+			jnx_init_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_PE,
+			jnx_init_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, PCI_DEVICE_ID_JNX_PF,
+			jnx_init_asic);
-- 
1.9.1

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#1497256 — [PATCH 2/3] staging: jnx: Common Juniper PCI methods

From: Rajat Jain <rajatjain@juniper.net>

All Juniper PTX platforms, whether powerpc or x86 based, use
similar PCI bridges (PLX & IDT). We don't want to duplicate
code in different arch directories, so put them here.

Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
[Ported from Juniper kernel]
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
---
 drivers/staging/jnx/Kconfig          |   6 +
 drivers/staging/jnx/Makefile         |   1 +
 drivers/staging/jnx/jnx_common_pci.c | 244 +++++++++++++++++++++++++++++++++++
 include/linux/jnx/jnx_common_pci.h   |  49 +++++++
 4 files changed, 300 insertions(+)
 create mode 100644 drivers/staging/jnx/jnx_common_pci.c
 create mode 100644 include/linux/jnx/jnx_common_pci.h

diff --git a/drivers/staging/jnx/Kconfig b/drivers/staging/jnx/Kconfig
index f01ef54..507f10d 100644
--- a/drivers/staging/jnx/Kconfig
+++ b/drivers/staging/jnx/Kconfig
@@ -21,6 +21,12 @@ config JNX_SYSTEM
 
 endmenu
 
+config JNX_COMMON_PCI
+	bool
+	---help---
+	  JNX common PCI code used by the quircks for configuring the PCIe
+	  switches in the system.
+
 config JNX_CHIP_PCI_QUIRKS
 	bool
 	select PCI_MMCONFIG
diff --git a/drivers/staging/jnx/Makefile b/drivers/staging/jnx/Makefile
index b29699c..0171476 100644
--- a/drivers/staging/jnx/Makefile
+++ b/drivers/staging/jnx/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_JNX_SYSTEM)	+= jnx-subsys.o jnx-board-core.o
 obj-$(CONFIG_JNX_CHIP_PCI_QUIRKS)+= jnx-chip-pci-quirks.o
+obj-$(CONFIG_JNX_COMMON_PCI)	+= jnx_common_pci.o
diff --git a/drivers/staging/jnx/jnx_common_pci.c b/drivers/staging/jnx/jnx_common_pci.c
new file mode 100644
index 0000000..d234465
--- /dev/null
+++ b/drivers/staging/jnx/jnx_common_pci.c
@@ -0,0 +1,244 @@
+/*
+ * Common PTXPMB Board Setup - PCI fixup code
+ *
+ * Guenter Roeck <groeck@juniper.net>
+ * Copyright 2012-2014 Juniper Networks
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/jnx/pci_ids.h>
+#include <linux/of_platform.h>
+#include <linux/memblock.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include <linux/jnx/jnx_common_pci.h>
+
+#define IDT_GASAADDR		0x00000FF8	/* IDT Global Access Addr Reg */
+#define IDT_GASADATA		0x00000FFC	/* IDT Global Access Data Reg */
+#define IDT_SWCTL		0x0003E000	/* IDT Switch Ctl Register */
+#define IDT_SWCTL_REGUNLOCK	BIT(3)		/* "Unlock" bit in Switch Ctl */
+
+#define PLX_MAGIC_REG		0x660
+#define PLX_MAGIC_BIT		BIT(30)
+
+/*
+ * Use undocumented PLX technique to unlock all registers
+ * (Including the "Read only" ones)
+ */
+void plx_unlock_registers(struct pci_dev *dev)
+{
+	u32 reg32;
+
+	pci_read_config_dword(dev, PLX_MAGIC_REG, &reg32);
+	pci_write_config_dword(dev, PLX_MAGIC_REG, reg32 | PLX_MAGIC_BIT);
+	pci_read_config_dword(dev, PLX_MAGIC_REG, &reg32);
+}
+
+/*
+ * Lock back the Read only registers
+ */
+void plx_lock_registers(struct pci_dev *dev)
+{
+	u32 reg32;
+
+	pci_read_config_dword(dev, PLX_MAGIC_REG, &reg32);
+	/*
+	 * This is a hack. For some reason, if I lock it back, the
+	 * INTERRUPT_PIN register is not getting cleared. Will need to talk to
+	 * PLX about this. For now, leave it unlocked.
+	 * pci_write_config_dword(dev, PLX_MAGIC_REG, reg32 & ~PLX_MAGIC_BIT);
+	 */
+	pci_write_config_dword(dev, PLX_MAGIC_REG, reg32 | PLX_MAGIC_BIT);
+	pci_read_config_dword(dev, PLX_MAGIC_REG, &reg32);
+}
+
+/*
+ * Unlock all IDT registers (include read only registers)
+ */
+void idt_48H12G2_unlock_registers(struct pci_dev *dev)
+{
+	u32 reg32;
+
+	pci_write_config_dword(dev, IDT_GASAADDR, IDT_SWCTL);
+	pci_read_config_dword(dev, IDT_GASADATA, &reg32);
+	pci_write_config_dword(dev, IDT_GASAADDR, IDT_SWCTL);
+	pci_write_config_dword(dev, IDT_GASADATA, reg32 | IDT_SWCTL_REGUNLOCK);
+}
+
+/*
+ * Lock back the read only registers.
+ */
+void idt_48H12G2_lock_registers(struct pci_dev *dev)
+{
+	u32 reg32;
+
+	pci_write_config_dword(dev, IDT_GASAADDR, IDT_SWCTL);
+	pci_read_config_dword(dev, IDT_GASADATA, &reg32);
+	pci_write_config_dword(dev, IDT_GASAADDR, IDT_SWCTL);
+	pci_write_config_dword(dev, IDT_GASADATA, reg32 & ~IDT_SWCTL_REGUNLOCK);
+}
+
+/*
+ * Turn a downstream port into hot-pluggable slot (to be managed by hot-plug
+ * driver) by setting the required bits in the capability registers. The
+ * function ensures that only ports with link change notification capability
+ * are turned into hotpluggable slots.
+ */
+static void make_hotpluggable_slot(struct pci_dev *dev)
+{
+	u32 reg32, psn;
+	u16 reg16;
+
+	/*
+	 * Only configure downstream ports as hot-pluggable
+	 */
+	if (!pci_find_capability(dev, PCI_CAP_ID_EXP) ||
+	    pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
+		return;
+
+	/*
+	 * There is no point in making it hot-plug if the port
+	 * does not support link change notifications.
+	 */
+	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &reg32);
+	if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
+		dev_warn(&dev->dev,
+			 "port does not support link state reporting\n");
+		return;
+	}
+
+	/*
+	 * Set the PCIe Capability register and the cached copy
+	 * Set "Slot Implemented" bit
+	 */
+	pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
+	reg16 |= PCI_EXP_FLAGS_SLOT;
+	pcie_capability_write_word(dev, PCI_EXP_FLAGS, reg16);
+	dev->pcie_flags_reg = reg16;
+
+	/*
+	 * Use port number as "Slot number"
+	 */
+	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &reg32);
+	psn = (reg32 & PCI_EXP_LNKCAP_PN) >> 24;
+	psn = (psn << 19) & PCI_EXP_SLTCAP_PSN;
+
+	/*
+	 * Set the Slot capability register
+	 * Set "HP capable" and "Physical Slot number"
+	 */
+	pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, &reg32);
+	reg32 &= ~PCI_EXP_SLTCAP_PSN;
+	reg32 |= PCI_EXP_SLTCAP_HPC | psn;
+	pcie_capability_write_dword(dev, PCI_EXP_SLTCAP, reg32);
+}
+
+static int ptx_get_pci_mem_region(struct pci_bus *bus,
+				  struct pci_bus_region *region)
+{
+	int i;
+	struct resource *res;
+
+	pci_bus_for_each_resource(bus, res, i) {
+		if (i > PCI_STD_RESOURCE_END && i < PCI_BRIDGE_RESOURCES)
+			continue;
+		if (res && (res->flags & IORESOURCE_MEM)) {
+			pcibios_resource_to_bus(bus, region, res);
+			return 0;
+		}
+	}
+	return -ENOMEM;
+}
+
+void jnx_fixup_pcie_bridge(struct pci_dev *dev, struct bus_assigns *ap,
+			   u16 base)
+{
+	for (; ap->bus; ap++) {
+		if (ap->bus == dev->bus->number &&
+		    (ap->slot == ANY || ap->slot == PCI_SLOT(dev->devfn))) {
+			pci_write_config_dword(dev, PCI_PRIMARY_BUS, ap->range);
+			if (ap->flags & PCI_MEM_WINDOW_DISABLED) {
+				pci_write_config_word(dev, PCI_MEMORY_BASE,
+						      0xFFFF);
+				pci_write_config_word(dev, PCI_MEMORY_LIMIT,
+						      0x0000);
+			} else {
+				pci_write_config_word(dev, PCI_MEMORY_BASE,
+						      base + ap->offset);
+				pci_write_config_word(dev, PCI_MEMORY_LIMIT,
+						      base + ap->offset +
+						      ap->limit);
+			}
+			pci_write_config_word(dev, PCI_IO_BASE, 0x0);
+			pci_write_config_word(dev, PCI_COMMAND, ap->command);
+			if (ap->flags & PCI_PORT_IS_HOTPLUGGABLE)
+				make_hotpluggable_slot(dev);
+			if (ap->flags & PCI_PORT_POWERON_DELAY)
+				dev->poweron_delay = 1;
+
+			return;
+		}
+	}
+	dev_err(&dev->dev,
+		"No configuration [bus 0x%x slot 0x%x devfn 0x%x]\n",
+		dev->bus->number, PCI_SLOT(dev->devfn), dev->devfn);
+}
+EXPORT_SYMBOL(jnx_fixup_pcie_bridge);
+
+void ptx_init_pci_bridge(struct pci_dev *dev, struct bus_assigns *ap)
+{
+	struct pci_bus_region region;
+	u32 base;
+
+	/* Get memory base address from parent bus */
+	if (!ptx_get_pci_mem_region(dev->bus->parent, &region)) {
+		base = (region.start >> 16) & 0xfff0;
+	} else {
+		dev_err(&dev->dev, "Can not allocate bridge memory\n");
+		base = 0;
+	}
+	jnx_fixup_pcie_bridge(dev, ap, base);
+}
+EXPORT_SYMBOL(ptx_init_pci_bridge);
+
+static void ptx_init_pci_root_bridge(struct pci_dev *dev)
+{
+	struct pci_bus_region region;
+	u32 base, limit;
+
+	if (!ptx_get_pci_mem_region(dev->bus, &region)) {
+		base = (region.start >> 16) & 0xfff0;
+		limit = (region.end >> 16) & 0xfff0;
+	} else {
+		dev_err(&dev->dev, "Can not allocate root bridge memory\n");
+		base = 0;
+		limit = 0;
+	}
+
+	pci_write_config_dword(dev, PCI_PRIMARY_BUS, 0xff0100);
+	pci_write_config_word(dev, PCI_MEMORY_BASE, base);
+	pci_write_config_word(dev, PCI_MEMORY_LIMIT, limit);
+	pci_write_config_word(dev, PCI_COMMAND, PCI_CMD_MEM_MSTR);
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_P2020E,
+			ptx_init_pci_root_bridge);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_P2020,
+			ptx_init_pci_root_bridge);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, 0x0450, /* P5040 */
+			ptx_init_pci_root_bridge);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_P5020E,
+			ptx_init_pci_root_bridge);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_P5020,
+			ptx_init_pci_root_bridge);
+
diff --git a/include/linux/jnx/jnx_common_pci.h b/include/linux/jnx/jnx_common_pci.h
new file mode 100644
index 0000000..c89e2de
--- /dev/null
+++ b/include/linux/jnx/jnx_common_pci.h
@@ -0,0 +1,49 @@
+/*
+ * Common Juniper PCI routine declarations
+ *
+ * Rajat Jain <rajatjain@juniper.net>
+ * Copyright 2014 Juniper Networks
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __JNX_COMMON_PCI_H__
+#define __JNX_COMMON_PCI_H__
+
+/*
+ * Normally bus number ranges, memory maps for PCI bridges and hotplug
+ * capabilities should be initialized by the ROMMON or BIOS or u-boot.
+ * Unfortunately, that is not done correctly today. If that happens and
+ * if the PCIe switch is correctly configured in ROMMON/BIOS/uboot,
+ * we may not need this.
+ */
+struct bus_assigns {
+	u8 bus;		/* bus number */
+	u8 slot;	/* slot number, ANY for all */
+#define ANY		0xff
+	u32 range;	/* bus number range. Three bytes <max, min, curr> */
+	u16 offset;	/* base address offset relative to parent */
+	u16 limit;	/* memory limit (size), added to offset & base */
+	u16 command;	/* command to write into command word */
+#define PCI_CMD_MEM_MSTR    (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
+	u32 flags;
+#define PCI_PORT_IS_HOTPLUGGABLE (1 << 0) /* true if port is hotpluggable */
+#define PCI_MEM_WINDOW_DISABLED	 (1 << 1)
+#define PCI_PORT_POWERON_DELAY	 (1 << 2) /* true if port needs poweron delay */
+};
+
+/* Common helper routines */
+void jnx_fixup_pcie_bridge(struct pci_dev *, struct bus_assigns *, u16);
+extern void ptx_init_pci_bridge(struct pci_dev *, struct bus_assigns *);
+
+/* PLX routines */
+extern void plx_unlock_registers(struct pci_dev *dev);
+extern void plx_lock_registers(struct pci_dev *dev);
+
+/* IDT routines */
+extern void idt_48H12G2_unlock_registers(struct pci_dev *dev);
+extern void idt_48H12G2_lock_registers(struct pci_dev *dev);
+#endif /* __JNX_COMMON_PCI_H__ */
-- 
1.9.1

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