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| Started by | Neil Armstrong <narmstrong@baylibre.com> |
|---|---|
| First post | 2016-10-05 16:00 +0200 |
| Last post | 2016-10-07 16:50 +0200 |
| Articles | 2 — 2 participants |
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[PATCH] ARM64: dts: meson-gx: Add missing L2 cache node Neil Armstrong <narmstrong@baylibre.com> - 2016-10-05 16:00 +0200
Re: [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node Kevin Hilman <khilman@baylibre.com> - 2016-10-07 16:50 +0200
| From | Neil Armstrong <narmstrong@baylibre.com> |
|---|---|
| Date | 2016-10-05 16:00 +0200 |
| Subject | [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node |
| Message-ID | <soUTM-1HA-3@gated-at.bofh.it> |
In order to remove the boot warning :
[ 2.290933] Unable to detect cache hierarchy from DT for CPU 0
And add missing L2 cache hierarchy information, add a simple l2 cache node
and reference it from the A53 cpu nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 0737056..a6cd953 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -64,6 +64,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -71,6 +72,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -78,6 +80,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -85,6 +88,11 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
};
};
--
1.9.1
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| From | Kevin Hilman <khilman@baylibre.com> |
|---|---|
| Date | 2016-10-07 16:50 +0200 |
| Message-ID | <spEDg-1QU-53@gated-at.bofh.it> |
| In reply to | #1495886 |
Neil Armstrong <narmstrong@baylibre.com> writes: > In order to remove the boot warning : > [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 > And add missing L2 cache hierarchy information, add a simple l2 cache node > and reference it from the A53 cpu nodes. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Applied to v4.10/dt64. Kevin
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