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[PATCH 2/2] drm/amd/powerplay: remove unused functions

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  [PATCH 2/2] drm/amd/powerplay: remove unused functions Baoyou Xie <baoyou.xie@linaro.org> - 2016-09-30 12:00 +0200
    [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible Baoyou Xie <baoyou.xie@linaro.org> - 2016-09-30 12:10 +0200
      Re: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible Christian König <deathsimple@vodafone.de> - 2016-09-30 14:20 +0200
        Re: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible Alex Deucher <alexdeucher@gmail.com> - 2016-09-30 19:40 +0200
          RE: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible "Zhu, Rex" <Rex.Zhu@amd.com> - 2016-10-03 19:00 +0200

#1494006 — [PATCH 2/2] drm/amd/powerplay: remove unused functions

We get 10 warnings when building kernel with W=1:
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:65:6: warning: no previous prototype for 'cz_phm_is_safe_for_asic_block' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:71:5: warning: no previous prototype for 'cz_phm_enable_disable_gfx_power_gating' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:76:5: warning: no previous prototype for 'cz_phm_smu_power_up_down_pcie' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:82:5: warning: no previous prototype for 'cz_phm_initialize_display_phy_access' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:88:5: warning: no previous prototype for 'cz_phm_get_display_phy_access_info' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:94:5: warning: no previous prototype for 'cz_phm_gate_unused_display_phys' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:100:5: warning: no previous prototype for 'cz_phm_ungate_all_display_phys' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1278:5: warning: no previous prototype for 'smu7_disable_dpm_tasks' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1336:5: warning: no previous prototype for 'smu7_reset_asic_tasks' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/eventmgr/eventtasks.c:322:5: warning: no previous prototype for 'pem_task_enable_clock_power_gating' [-Wmissing-prototypes]

In fact, these functions are called by no one and not exported,
so this patch removes them.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
 .../gpu/drm/amd/powerplay/eventmgr/eventtasks.c    |   7 -
 .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c  |  42 -----
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 206 ---------------------
 .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c   |  59 ------
 .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h   |   2 -
 5 files changed, 316 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
index b6f45fd..03e5c02 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
@@ -319,13 +319,6 @@ int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *e
 	return 0;
 }
 
-int pem_task_enable_clock_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
-	/* TODO */
-	return 0;
-}
-
-
 int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
 {
 	/* TODO */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 2028980..0966fc8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -61,48 +61,6 @@ int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock bloc
 	return ret;
 }
 
-
-bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block)
-{
-	return true;
-}
-
-
-int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable)
-{
-	return 0;
-}
-
-int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args)
-{
-	/* TODO */
-	return 0;
-}
-
-int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw)
-{
-	/* TODO */
-	return 0;
-}
-
-int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr)
-{
-	/* TODO */
-	return 0;
-}
-
-int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr)
-{
-	/* TODO */
-	return 0;
-}
-
-int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
-{
-	/* TODO */
-	return 0;
-}
-
 static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
 {
 	return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 649fdd3..1c85925 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -409,34 +409,6 @@ static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
-{
-	/* Reset voting clients before disabling DPM */
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
-
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_0, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_1, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_2, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_3, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_4, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_5, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_6, 0);
-	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixCG_FREQ_TRAN_VOTING_7, 0);
-
-	return 0;
-}
-
 /* Copy one arb setting to another and then switch the active set.
  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
  */
@@ -486,11 +458,6 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
-{
-	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
-}
-
 /**
 * Initial switch from ARB F0->F1
 *
@@ -504,21 +471,6 @@ static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 			MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 }
 
-static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
-{
-	uint32_t tmp;
-
-	tmp = (cgs_read_ind_register(hwmgr->device,
-			CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
-			0x0000ff00) >> 8;
-
-	if (tmp == MC_CG_ARB_FREQ_F0)
-		return 0;
-
-	return smu7_copy_and_switch_arb_sets(hwmgr,
-			tmp, MC_CG_ARB_FREQ_F0);
-}
-
 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -873,16 +825,6 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-	if (data->ulv_supported)
-		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
-
-	return 0;
-}
-
 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -903,21 +845,6 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
-{
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_SclkDeepSleep)) {
-		if (smum_send_msg_to_smc(hwmgr->smumgr,
-				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
-			PP_ASSERT_WITH_CODE(false,
-					"Attempt to disable Master Deep Sleep switch failed!",
-					return -EINVAL);
-		}
-	}
-
-	return 0;
-}
-
 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -1025,58 +952,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-	/* disable SCLK dpm */
-	if (!data->sclk_dpm_key_disabled)
-		PP_ASSERT_WITH_CODE(
-				(smum_send_msg_to_smc(hwmgr->smumgr,
-						PPSMC_MSG_DPM_Disable) == 0),
-				"Failed to disable SCLK DPM!",
-				return -EINVAL);
-
-	/* disable MCLK dpm */
-	if (!data->mclk_dpm_key_disabled) {
-		PP_ASSERT_WITH_CODE(
-				(smum_send_msg_to_smc(hwmgr->smumgr,
-						PPSMC_MSG_MCLKDPM_Disable) == 0),
-				"Failed to disable MCLK DPM!",
-				return -EINVAL);
-	}
-
-	return 0;
-}
-
-static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-	/* disable general power management */
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-			GLOBAL_PWRMGT_EN, 0);
-	/* disable sclk deep sleep */
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-			DYNAMIC_PM_EN, 0);
-
-	/* disable PCIE dpm */
-	if (!data->pcie_dpm_key_disabled) {
-		PP_ASSERT_WITH_CODE(
-				(smum_send_msg_to_smc(hwmgr->smumgr,
-						PPSMC_MSG_PCIeDPM_Disable) == 0),
-				"Failed to disable pcie DPM during DPM Stop Function!",
-				return -EINVAL);
-	}
-
-	if (smu7_disable_sclk_mclk_dpm(hwmgr)) {
-		printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
 {
 	bool protection;
@@ -1134,23 +1009,6 @@ static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
 	return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
 }
 
-static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
-		PHM_AutoThrottleSource source)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-	if (data->active_auto_throttle_sources & (1 << source)) {
-		data->active_auto_throttle_sources &= ~(1 << source);
-		smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
-	}
-	return 0;
-}
-
-static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
-{
-	return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
-}
-
 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -1275,70 +1133,6 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-{
-	int tmp_result, result = 0;
-
-	tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1;
-	PP_ASSERT_WITH_CODE(tmp_result == 0,
-			"DPM is not running right now, no need to disable DPM!",
-			return 0);
-
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_ThermalController))
-		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-				GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
-
-	tmp_result = smu7_disable_power_containment(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to disable power containment!", result = tmp_result);
-
-	tmp_result = smu7_disable_smc_cac(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to disable SMC CAC!", result = tmp_result);
-
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-			CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
-	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-			GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
-
-	tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to disable thermal auto throttle!", result = tmp_result);
-
-	tmp_result = smu7_stop_dpm(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to stop DPM!", result = tmp_result);
-
-	tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to disable deep sleep master switch!", result = tmp_result);
-
-	tmp_result = smu7_disable_ulv(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to disable ULV!", result = tmp_result);
-
-	tmp_result = smu7_clear_voting_clients(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to clear voting clients!", result = tmp_result);
-
-	tmp_result = smu7_reset_to_default(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to reset to default!", result = tmp_result);
-
-	tmp_result = smu7_force_switch_to_arbf0(hwmgr);
-	PP_ASSERT_WITH_CODE((tmp_result == 0),
-			"Failed to force to switch arbf0!", result = tmp_result);
-
-	return result;
-}
-
-int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
-{
-
-	return 0;
-}
-
 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 260fce050..77d79b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -575,23 +575,6 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-	int result = 0;
-
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_CAC) && data->cac_enabled) {
-		int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-				(uint16_t)(PPSMC_MSG_DisableCac));
-		PP_ASSERT_WITH_CODE((smc_result == 0),
-				"Failed to disable CAC in SMC.", result = -1);
-
-		data->cac_enabled = false;
-	}
-	return result;
-}
-
 int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -657,48 +640,6 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
-{
-	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-	int result = 0;
-
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_PowerContainment) &&
-			data->power_containment_features) {
-		int smc_result;
-
-		if (data->power_containment_features &
-				POWERCONTAINMENT_FEATURE_TDCLimit) {
-			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-					(uint16_t)(PPSMC_MSG_TDCLimitDisable));
-			PP_ASSERT_WITH_CODE((smc_result == 0),
-					"Failed to disable TDCLimit in SMC.",
-					result = smc_result);
-		}
-
-		if (data->power_containment_features &
-				POWERCONTAINMENT_FEATURE_DTE) {
-			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-					(uint16_t)(PPSMC_MSG_DisableDTE));
-			PP_ASSERT_WITH_CODE((smc_result == 0),
-					"Failed to disable DTE in SMC.",
-					result = smc_result);
-		}
-
-		if (data->power_containment_features &
-				POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
-			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-					(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
-			PP_ASSERT_WITH_CODE((smc_result == 0),
-					"Failed to disable PkgPwrTracking in SMC.",
-					result = smc_result);
-		}
-		data->power_containment_features = 0;
-	}
-
-	return result;
-}
-
 int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
 {
 	struct phm_ppt_v1_information *table_info =
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h
index 22f86b6..e995fd3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h
@@ -51,9 +51,7 @@
 
 
 int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr);
-int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr);
 int smu7_enable_power_containment(struct pp_hwmgr *hwmgr);
-int smu7_disable_power_containment(struct pp_hwmgr *hwmgr);
 int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
 int smu7_power_control_set_level(struct pp_hwmgr *hwmgr);
 int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);
-- 
2.7.4

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#1494008 — [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible

We get a few warnings when building kernel with W=1:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5: warning: no previous prototype for 'fiji_setup_pwr_virus' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning: no previous prototype for 'fiji_program_mem_timing_parameters' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5: warning: no previous prototype for 'polaris10_avfs_event_mgr' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning: no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prototypes]
....

In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  5 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 12 +++---
 .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  6 +--
 .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  4 +-
 .../amd/powerplay/hwmgr/smu7_clockpowergating.c    | 10 ++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 45 ++++++++++++----------
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    |  2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 12 +++---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  5 ++-
 9 files changed, 54 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7174f7a..bb8a345 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -436,7 +436,8 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 	}
 }
 
-int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
+static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
+		void *input, void *output)
 {
 	int ret = 0;
 	struct pp_instance *pp_handle;
@@ -475,7 +476,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
 	return ret;
 }
 
-enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
+static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 {
 	struct pp_hwmgr *hwmgr;
 	struct pp_power_state *state;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 7e4fcbb..b48d00f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzPowerState(
 	return (struct cz_power_state *)hw_ps;
 }
 
-uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
+static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
 					uint32_t clock, uint32_t msg)
 {
 	int i = 0;
@@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
+static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
 				void *output, void *storage, int result)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
+static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_clock_voltage_dependency_table *table =
@@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 	return result;
 }
 
-int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
+static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
 {
 	return sizeof(struct cz_power_state);
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index 7de701d..155cd0d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
 /**
  * Private Function to get the PowerPlay Table Address.
  */
-const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
+static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
 {
 	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 
@@ -1049,7 +1049,7 @@ static int check_powerplay_tables(
 	return 0;
 }
 
-int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
+static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
 {
 	int result = 0;
 	const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
@@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
+static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
 {
 	struct phm_ppt_v1_information *pp_table_information =
 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index ccf7ebe..bd1f190 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-int get_number_of_vce_state_table_entries(
+static int get_number_of_vce_state_table_entries(
 						  struct pp_hwmgr *hwmgr)
 {
 	const ATOM_PPLIB_POWERPLAYTABLE *table =
@@ -1521,7 +1521,7 @@ int get_number_of_vce_state_table_entries(
 	return 0;
 }
 
-int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
+static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
 							unsigned long i,
 							struct pp_vce_state *vce_state,
 							void **clock_info,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 6eb6db1..f5a58d4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
+static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_uvd_power_gating(hwmgr)) {
 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
+static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_vce_power_gating(hwmgr))
 		return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
+static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_vce_power_gating(hwmgr))
 		return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
+static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_SamuPowerGating))
@@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
+static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_SamuPowerGating))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a3832f2..649fdd3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -89,7 +89,7 @@ enum DPM_EVENT_SRC {
 
 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 
-struct smu7_power_state *cast_phw_smu7_power_state(
+static struct smu7_power_state *cast_phw_smu7_power_state(
 				  struct pp_hw_power_state *hw_ps)
 {
 	PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
@@ -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state(
 	return (struct smu7_power_state *)hw_ps;
 }
 
-const struct smu7_power_state *cast_const_phw_smu7_power_state(
+static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 				 const struct pp_hw_power_state *hw_ps)
 {
 	PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
@@ -115,7 +115,7 @@ const struct smu7_power_state *cast_const_phw_smu7_power_state(
  * @param    hwmgr  the address of the powerplay hardware manager.
  * @return   always 0
  */
-int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
+static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 {
 	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 
@@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
+static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 {
 	uint32_t speedCntl = 0;
 
@@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 }
 
-int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
+static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 {
 	uint32_t link_width;
 
@@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 * @param    pHwMgr  the address of the powerplay hardware manager.
 * @return   always PP_Result_OK
 */
-int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
+static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 {
 	if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);
@@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
+static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
@@ -1151,7 +1151,7 @@ static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
 	return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
 }
 
-int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
+static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	data->pcie_performance_request = true;
@@ -1159,7 +1159,7 @@ int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	int tmp_result = 0;
 	int result = 0;
@@ -1854,7 +1854,7 @@ static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
+static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
 {
 	struct phm_ppt_v1_information *table_info =
 		       (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2243,7 +2243,7 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data;
 	int result;
@@ -3662,14 +3662,16 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
 			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
 }
 
-int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
+static int
+smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
 {
 	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
 
 	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
 }
 
-int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
+static int
+smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 {
 	uint32_t num_active_displays = 0;
 	struct cgs_display_info info = {0};
@@ -3691,7 +3693,7 @@ int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 * @param    hwmgr  the address of the powerplay hardware manager.
 * @return   always OK
 */
-int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
+static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	uint32_t num_active_displays = 0;
@@ -3741,7 +3743,7 @@ int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
+static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
 {
 	return smu7_program_display_gap(hwmgr);
 }
@@ -3765,13 +3767,14 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
 			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }
 
-int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
+static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
 					const void *thermal_interrupt_info)
 {
 	return 0;
 }
 
-bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
+static bool
+smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	bool is_update_required = false;
@@ -3800,7 +3803,9 @@ static inline bool smu7_are_power_levels_equal(const struct smu7_performance_lev
 		  (pl1->pcie_lane == pl2->pcie_lane));
 }
 
-int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
+static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
+		const struct pp_hw_power_state *pstate1,
+		const struct pp_hw_power_state *pstate2, bool *equal)
 {
 	const struct smu7_power_state *psa = cast_const_phw_smu7_power_state(pstate1);
 	const struct smu7_power_state *psb = cast_const_phw_smu7_power_state(pstate2);
@@ -3831,7 +3836,7 @@ int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_sta
 	return 0;
 }
 
-int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
+static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
@@ -3960,7 +3965,7 @@ static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
+static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
 {
 	int tmp_result, result = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 76310ac..e7e8944 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -2049,7 +2049,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 02fe1df..b86e48f 100755
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -159,7 +159,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
 	return result;
 }
 
-int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
+static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
 {
 	int i, result = -1;
 	uint32_t reg, data;
@@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
 	return result;
 }
 
-int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
+static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
 {
 	int result = 0;
 	uint32_t table_start;
@@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
 	return result;
 }
 
-int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
+static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 {
 	int32_t vr_config;
 	uint32_t table_start;
@@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 }
 
 /* Work in Progress */
-int fiji_restore_vft_table(struct pp_smumgr *smumgr)
+static int fiji_restore_vft_table(struct pp_smumgr *smumgr)
 {
 	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 
@@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr)
 }
 
 /* Work in Progress */
-int fiji_save_vft_table(struct pp_smumgr *smumgr)
+static int fiji_save_vft_table(struct pp_smumgr *smumgr)
 {
 	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 
@@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr)
 		return -EINVAL;
 }
 
-int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
+static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
 {
 	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 5c3598a..f38a687 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
 }
 
 
-int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
+static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 {
 	uint32_t vr_config;
 	uint32_t dpm_table_start;
@@ -172,7 +172,8 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 	return 0;
 }
 
-int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
+static int
+polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
 {
 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
 
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1494068 — Re: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible

Both patches are Acked-by: Christian König <christian.koenig@amd.com>.

Regards,
Christian.

Am 30.09.2016 um 11:58 schrieb Baoyou Xie:
> We get a few warnings when building kernel with W=1:
> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5: warning: no previous prototype for 'fiji_setup_pwr_virus' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning: no previous prototype for 'fiji_program_mem_timing_parameters' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5: warning: no previous prototype for 'polaris10_avfs_event_mgr' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning: no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prototypes]
> ....
>
> In fact, these functions are only used in the file in which they are
> declared and don't need a declaration, but can be made static.
> So this patch marks these functions with 'static'.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  5 ++-
>   drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 12 +++---
>   .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  6 +--
>   .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  4 +-
>   .../amd/powerplay/hwmgr/smu7_clockpowergating.c    | 10 ++---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 45 ++++++++++++----------
>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    |  2 +-
>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 12 +++---
>   .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  5 ++-
>   9 files changed, 54 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7174f7a..bb8a345 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -436,7 +436,8 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
>   	}
>   }
>   
> -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
> +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
> +		void *input, void *output)
>   {
>   	int ret = 0;
>   	struct pp_instance *pp_handle;
> @@ -475,7 +476,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
>   	return ret;
>   }
>   
> -enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> +static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>   {
>   	struct pp_hwmgr *hwmgr;
>   	struct pp_power_state *state;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 7e4fcbb..b48d00f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzPowerState(
>   	return (struct cz_power_state *)hw_ps;
>   }
>   
> -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
> +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
>   					uint32_t clock, uint32_t msg)
>   {
>   	int i = 0;
> @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
>   	return 0;
>   }
>   
> -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
> +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
>   				void *output, void *storage, int result)
>   {
>   	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
> +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>   {
>   	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>   
> @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>   {
>   	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>   	struct phm_clock_voltage_dependency_table *table =
> @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
> +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
>   {
>   	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>   
> @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
>   	return result;
>   }
>   
> -int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
> +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
>   {
>   	return sizeof(struct cz_power_state);
>   }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> index 7de701d..155cd0d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
>   /**
>    * Private Function to get the PowerPlay Table Address.
>    */
> -const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
> +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
>   {
>   	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
>   
> @@ -1049,7 +1049,7 @@ static int check_powerplay_tables(
>   	return 0;
>   }
>   
> -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
> +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>   {
>   	int result = 0;
>   	const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
> @@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>   	return result;
>   }
>   
> -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
> +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
>   {
>   	struct phm_ppt_v1_information *pp_table_information =
>   		(struct phm_ppt_v1_information *)(hwmgr->pptable);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index ccf7ebe..bd1f190 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
>   	return 0;
>   }
>   
> -int get_number_of_vce_state_table_entries(
> +static int get_number_of_vce_state_table_entries(
>   						  struct pp_hwmgr *hwmgr)
>   {
>   	const ATOM_PPLIB_POWERPLAYTABLE *table =
> @@ -1521,7 +1521,7 @@ int get_number_of_vce_state_table_entries(
>   	return 0;
>   }
>   
> -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
> +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
>   							unsigned long i,
>   							struct pp_vce_state *vce_state,
>   							void **clock_info,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> index 6eb6db1..f5a58d4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> @@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
> +static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>   {
>   	if (phm_cf_want_uvd_power_gating(hwmgr)) {
>   		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> @@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
> +static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>   {
>   	if (phm_cf_want_vce_power_gating(hwmgr))
>   		return smum_send_msg_to_smc(hwmgr->smumgr,
> @@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
> +static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>   {
>   	if (phm_cf_want_vce_power_gating(hwmgr))
>   		return smum_send_msg_to_smc(hwmgr->smumgr,
> @@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
> +static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>   {
>   	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>   			PHM_PlatformCaps_SamuPowerGating))
> @@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
> +static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
>   {
>   	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>   			PHM_PlatformCaps_SamuPowerGating))
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index a3832f2..649fdd3 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -89,7 +89,7 @@ enum DPM_EVENT_SRC {
>   
>   static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
>   
> -struct smu7_power_state *cast_phw_smu7_power_state(
> +static struct smu7_power_state *cast_phw_smu7_power_state(
>   				  struct pp_hw_power_state *hw_ps)
>   {
>   	PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
> @@ -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state(
>   	return (struct smu7_power_state *)hw_ps;
>   }
>   
> -const struct smu7_power_state *cast_const_phw_smu7_power_state(
> +static const struct smu7_power_state *cast_const_phw_smu7_power_state(
>   				 const struct pp_hw_power_state *hw_ps)
>   {
>   	PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
> @@ -115,7 +115,7 @@ const struct smu7_power_state *cast_const_phw_smu7_power_state(
>    * @param    hwmgr  the address of the powerplay hardware manager.
>    * @return   always 0
>    */
> -int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
> +static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
>   {
>   	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
>   
> @@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
> +static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>   {
>   	uint32_t speedCntl = 0;
>   
> @@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>   			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
>   }
>   
> -int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
> +static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>   {
>   	uint32_t link_width;
>   
> @@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>   * @param    pHwMgr  the address of the powerplay hardware manager.
>   * @return   always PP_Result_OK
>   */
> -int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
> +static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
>   {
>   	if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
>   		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);
> @@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
> +static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   
> @@ -1151,7 +1151,7 @@ static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
>   	return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
>   }
>   
> -int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
> +static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   	data->pcie_performance_request = true;
> @@ -1159,7 +1159,7 @@ int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>   {
>   	int tmp_result = 0;
>   	int result = 0;
> @@ -1854,7 +1854,7 @@ static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
> +static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
>   {
>   	struct phm_ppt_v1_information *table_info =
>   		       (struct phm_ppt_v1_information *)(hwmgr->pptable);
> @@ -2243,7 +2243,7 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> +static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data;
>   	int result;
> @@ -3662,14 +3662,16 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
>   			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
>   }
>   
> -int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
> +static int
> +smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
>   {
>   	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
>   
>   	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
>   }
>   
> -int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
> +static int
> +smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
>   {
>   	uint32_t num_active_displays = 0;
>   	struct cgs_display_info info = {0};
> @@ -3691,7 +3693,7 @@ int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
>   * @param    hwmgr  the address of the powerplay hardware manager.
>   * @return   always OK
>   */
> -int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
> +static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   	uint32_t num_active_displays = 0;
> @@ -3741,7 +3743,7 @@ int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> +static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
>   {
>   	return smu7_program_display_gap(hwmgr);
>   }
> @@ -3765,13 +3767,14 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
>   			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
>   }
>   
> -int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
> +static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
>   					const void *thermal_interrupt_info)
>   {
>   	return 0;
>   }
>   
> -bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
> +static bool
> +smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   	bool is_update_required = false;
> @@ -3800,7 +3803,9 @@ static inline bool smu7_are_power_levels_equal(const struct smu7_performance_lev
>   		  (pl1->pcie_lane == pl2->pcie_lane));
>   }
>   
> -int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
> +static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
> +		const struct pp_hw_power_state *pstate1,
> +		const struct pp_hw_power_state *pstate2, bool *equal)
>   {
>   	const struct smu7_power_state *psa = cast_const_phw_smu7_power_state(pstate1);
>   	const struct smu7_power_state *psb = cast_const_phw_smu7_power_state(pstate2);
> @@ -3831,7 +3836,7 @@ int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_sta
>   	return 0;
>   }
>   
> -int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
> +static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   
> @@ -3960,7 +3965,7 @@ static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
> +static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
>   {
>   	int tmp_result, result = 0;
>   
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> index 76310ac..e7e8944 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> @@ -2049,7 +2049,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
>   	return 0;
>   }
>   
> -int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
> +static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
>   {
>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>   
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index 02fe1df..b86e48f 100755
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -159,7 +159,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
>   	return result;
>   }
>   
> -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
> +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>   {
>   	int i, result = -1;
>   	uint32_t reg, data;
> @@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
>   	return result;
>   }
>   
> -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
> +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>   {
>   	int result = 0;
>   	uint32_t table_start;
> @@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>   	return result;
>   }
>   
> -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> +static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>   {
>   	int32_t vr_config;
>   	uint32_t table_start;
> @@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>   }
>   
>   /* Work in Progress */
> -int fiji_restore_vft_table(struct pp_smumgr *smumgr)
> +static int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>   {
>   	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>   
> @@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>   }
>   
>   /* Work in Progress */
> -int fiji_save_vft_table(struct pp_smumgr *smumgr)
> +static int fiji_save_vft_table(struct pp_smumgr *smumgr)
>   {
>   	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>   
> @@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr)
>   		return -EINVAL;
>   }
>   
> -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
> +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
>   {
>   	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>   
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index 5c3598a..f38a687 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
>   }
>   
>   
> -int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
> +static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>   {
>   	uint32_t vr_config;
>   	uint32_t dpm_table_start;
> @@ -172,7 +172,8 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>   	return 0;
>   }
>   
> -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
> +static int
> +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
>   {
>   	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
>   

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#1494216 — Re: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible

On Fri, Sep 30, 2016 at 8:16 AM, Christian König
<deathsimple@vodafone.de> wrote:
> Both patches are Acked-by: Christian König <christian.koenig@amd.com>.

Applied patch 1.  I'd like to get Rex's ack on patch 2 before applying it.

Alex

>
> Regards,
> Christian.
>
>
> Am 30.09.2016 um 11:58 schrieb Baoyou Xie:
>>
>> We get a few warnings when building kernel with W=1:
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5:
>> warning: no previous prototype for 'fiji_setup_pwr_virus'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning:
>> no previous prototype for 'fiji_program_mem_timing_parameters'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5:
>> warning: no previous prototype for 'polaris10_avfs_event_mgr'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning:
>> no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning:
>> no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prototypes]
>> ....
>>
>> In fact, these functions are only used in the file in which they are
>> declared and don't need a declaration, but can be made static.
>> So this patch marks these functions with 'static'.
>>
>> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
>> ---
>>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  5 ++-
>>   drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 12 +++---
>>   .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  6 +--
>>   .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  4 +-
>>   .../amd/powerplay/hwmgr/smu7_clockpowergating.c    | 10 ++---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 45
>> ++++++++++++----------
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    |  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 12 +++---
>>   .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  5 ++-
>>   9 files changed, 54 insertions(+), 47 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> index 7174f7a..bb8a345 100644
>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> @@ -436,7 +436,8 @@ static enum PP_StateUILabel power_state_convert(enum
>> amd_pm_state_type  state)
>>         }
>>   }
>>   -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
>> void *input, void *output)
>> +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event
>> event_id,
>> +               void *input, void *output)
>>   {
>>         int ret = 0;
>>         struct pp_instance *pp_handle;
>> @@ -475,7 +476,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum
>> amd_pp_event event_id, void *input,
>>         return ret;
>>   }
>>   -enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>> +static enum amd_pm_state_type pp_dpm_get_current_power_state(void
>> *handle)
>>   {
>>         struct pp_hwmgr *hwmgr;
>>         struct pp_power_state *state;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index 7e4fcbb..b48d00f 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -66,7 +66,7 @@ static const struct cz_power_state
>> *cast_const_PhwCzPowerState(
>>         return (struct cz_power_state *)hw_ps;
>>   }
>>   -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
>> +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
>>                                         uint32_t clock, uint32_t msg)
>>   {
>>         int i = 0;
>> @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct
>> pp_hwmgr *hwmgr, void *input,
>>         return 0;
>>   }
>>   -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
>> +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void
>> *input,
>>                                 void *output, void *storage, int result)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>> @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>   @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>         struct phm_clock_voltage_dependency_table *table =
>> @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>   @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct
>> pp_hwmgr *hwmgr,
>>         return result;
>>   }
>>   -int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
>> +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
>>   {
>>         return sizeof(struct cz_power_state);
>>   }
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> index 7de701d..155cd0d 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr,
>> uint32_t powerplay_caps)
>>   /**
>>    * Private Function to get the PowerPlay Table Address.
>>    */
>> -const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
>> +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
>>   {
>>         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
>>   @@ -1049,7 +1049,7 @@ static int check_powerplay_tables(
>>         return 0;
>>   }
>>   -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>> +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>>   {
>>         int result = 0;
>>         const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
>> @@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr
>> *hwmgr)
>>         return result;
>>   }
>>   -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
>> +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
>>   {
>>         struct phm_ppt_v1_information *pp_table_information =
>>                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> index ccf7ebe..bd1f190 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hwmgr
>> *hwmgr,
>>         return 0;
>>   }
>>   -int get_number_of_vce_state_table_entries(
>> +static int get_number_of_vce_state_table_entries(
>>                                                   struct pp_hwmgr *hwmgr)
>>   {
>>         const ATOM_PPLIB_POWERPLAYTABLE *table =
>> @@ -1521,7 +1521,7 @@ int get_number_of_vce_state_table_entries(
>>         return 0;
>>   }
>>   -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
>> +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
>>                                                         unsigned long i,
>>                                                         struct
>> pp_vce_state *vce_state,
>>                                                         void **clock_info,
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> index 6eb6db1..f5a58d4 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> @@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_uvd_power_gating(hwmgr)) {
>>                 if
>> (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>> @@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_vce_power_gating(hwmgr))
>>                 return smum_send_msg_to_smc(hwmgr->smumgr,
>> @@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_vce_power_gating(hwmgr))
>>                 return smum_send_msg_to_smc(hwmgr->smumgr,
>> @@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>                         PHM_PlatformCaps_SamuPowerGating))
>> @@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>                         PHM_PlatformCaps_SamuPowerGating))
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index a3832f2..649fdd3 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -89,7 +89,7 @@ enum DPM_EVENT_SRC {
>>     static const unsigned long PhwVIslands_Magic = (unsigned
>> long)(PHM_VIslands_Magic);
>>   -struct smu7_power_state *cast_phw_smu7_power_state(
>> +static struct smu7_power_state *cast_phw_smu7_power_state(
>>                                   struct pp_hw_power_state *hw_ps)
>>   {
>>         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
>> @@ -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state(
>>         return (struct smu7_power_state *)hw_ps;
>>   }
>>   -const struct smu7_power_state *cast_const_phw_smu7_power_state(
>> +static const struct smu7_power_state *cast_const_phw_smu7_power_state(
>>                                  const struct pp_hw_power_state *hw_ps)
>>   {
>>         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
>> @@ -115,7 +115,7 @@ const struct smu7_power_state
>> *cast_const_phw_smu7_power_state(
>>    * @param    hwmgr  the address of the powerplay hardware manager.
>>    * @return   always 0
>>    */
>> -int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
>> +static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
>>   {
>>         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
>>   @@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>> +static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>>   {
>>         uint32_t speedCntl = 0;
>>   @@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr
>> *hwmgr)
>>                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
>>   }
>>   -int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>> +static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>>   {
>>         uint32_t link_width;
>>   @@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct
>> pp_hwmgr *hwmgr)
>>   * @param    pHwMgr  the address of the powerplay hardware manager.
>>   * @return   always PP_Result_OK
>>   */
>> -int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
>> +static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
>>   {
>>         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
>>                 smum_send_msg_to_smc(hwmgr->smumgr,
>> PPSMC_MSG_Voltage_Cntl_Enable);
>> @@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
>> +static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   @@ -1151,7 +1151,7 @@ static int
>> smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
>>         return smu7_disable_auto_throttle_source(hwmgr,
>> PHM_AutoThrottleSource_Thermal);
>>   }
>>   -int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>> +static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         data->pcie_performance_request = true;
>> @@ -1159,7 +1159,7 @@ int smu7_pcie_performance_request(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>> +static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>>   {
>>         int tmp_result = 0;
>>         int result = 0;
>> @@ -1854,7 +1854,7 @@ static int
>> smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
>> +static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
>>   {
>>         struct phm_ppt_v1_information *table_info =
>>                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
>> @@ -2243,7 +2243,7 @@ static int
>> smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>> +static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data;
>>         int result;
>> @@ -3662,14 +3662,16 @@ static int smu7_set_max_fan_pwm_output(struct
>> pp_hwmgr *hwmgr, uint16_t us_max_f
>>                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
>>   }
>>   -int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool
>> has_display)
>> +static int
>> +smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
>>   {
>>         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay :
>> (PPSMC_Msg)PPSMC_NoDisplay;
>>         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
>>   }
>>   -int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
>> *hwmgr)
>> +static int
>> +smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
>> *hwmgr)
>>   {
>>         uint32_t num_active_displays = 0;
>>         struct cgs_display_info info = {0};
>> @@ -3691,7 +3693,7 @@ int
>> smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
>>   * @param    hwmgr  the address of the powerplay hardware manager.
>>   * @return   always OK
>>   */
>> -int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>> +static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         uint32_t num_active_displays = 0;
>> @@ -3741,7 +3743,7 @@ int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
>> +static int smu7_display_configuration_changed_task(struct pp_hwmgr
>> *hwmgr)
>>   {
>>         return smu7_program_display_gap(hwmgr);
>>   }
>> @@ -3765,13 +3767,14 @@ static int smu7_set_max_fan_rpm_output(struct
>> pp_hwmgr *hwmgr, uint16_t us_max_f
>>                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
>>   }
>>   -int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
>> +static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr
>> *hwmgr,
>>                                         const void
>> *thermal_interrupt_info)
>>   {
>>         return 0;
>>   }
>>   -bool smu7_check_smc_update_required_for_display_configuration(struct
>> pp_hwmgr *hwmgr)
>> +static bool
>> +smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr
>> *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         bool is_update_required = false;
>> @@ -3800,7 +3803,9 @@ static inline bool smu7_are_power_levels_equal(const
>> struct smu7_performance_lev
>>                   (pl1->pcie_lane == pl2->pcie_lane));
>>   }
>>   -int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct
>> pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool
>> *equal)
>> +static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
>> +               const struct pp_hw_power_state *pstate1,
>> +               const struct pp_hw_power_state *pstate2, bool *equal)
>>   {
>>         const struct smu7_power_state *psa =
>> cast_const_phw_smu7_power_state(pstate1);
>>         const struct smu7_power_state *psb =
>> cast_const_phw_smu7_power_state(pstate2);
>> @@ -3831,7 +3836,7 @@ int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
>> const struct pp_hw_power_sta
>>         return 0;
>>   }
>>   -int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
>> +static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   @@ -3960,7 +3965,7 @@ static int smu7_init_sclk_threshold(struct
>> pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
>> +static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
>>   {
>>         int tmp_result, result = 0;
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> index 76310ac..e7e8944 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> @@ -2049,7 +2049,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
>> +static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> index 02fe1df..b86e48f 100755
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> @@ -159,7 +159,7 @@ static int
>> fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>> +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>>   {
>>         int i, result = -1;
>>         uint32_t reg, data;
>> @@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr
>> *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>> +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>>   {
>>         int result = 0;
>>         uint32_t table_start;
>> @@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr
>> *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>> +static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>>   {
>>         int32_t vr_config;
>>         uint32_t table_start;
>> @@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct
>> pp_smumgr *smumgr)
>>   }
>>     /* Work in Progress */
>> -int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>> +static int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr
>> *)(smumgr->backend);
>>   @@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>>   }
>>     /* Work in Progress */
>> -int fiji_save_vft_table(struct pp_smumgr *smumgr)
>> +static int fiji_save_vft_table(struct pp_smumgr *smumgr)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr
>> *)(smumgr->backend);
>>   @@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr)
>>                 return -EINVAL;
>>   }
>>   -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
>> +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool
>> smu_started)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr
>> *)(smumgr->backend);
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> index 5c3598a..f38a687 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> @@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr
>> *smumgr)
>>   }
>>     -int polaris10_setup_graphics_level_structure(struct pp_smumgr
>> *smumgr)
>> +static int polaris10_setup_graphics_level_structure(struct pp_smumgr
>> *smumgr)
>>   {
>>         uint32_t vr_config;
>>         uint32_t dpm_table_start;
>> @@ -172,7 +172,8 @@ int polaris10_setup_graphics_level_structure(struct
>> pp_smumgr *smumgr)
>>         return 0;
>>   }
>>   -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool
>> SMU_VFT_INTACT)
>> +static int
>> +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
>>   {
>>         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr
>> *)(smumgr->backend);
>>
>
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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#1494971 — RE: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible

Hi Alex and Baoyou,

I will implement and use most of the functions in Patch2 in the future.
and I will refine the code and fix the build warning.

Thanks very much.

Best Regards
Rex


-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com] 
Sent: Saturday, October 01, 2016 1:32 AM
To: Christian König
Cc: Baoyou Xie; Deucher, Alexander; Dave Airlie; Zhu, Rex; Huang, JinHuiEric; Zhou, Jammy; StDenis, Tom; Nath, Arindam; Nils Wallménius; Yang, Eric; funfunctor@folklore1984.net; Yang, Young; Dan Carpenter; Huang, Ray; Arnd Bergmann; Cui, Flora; Wang, Ken; Liu, Monk; Min, Frank; tang.qiang007@zte.com.cn; xie.baoyou@zte.com.cn; han.fei@zte.com.cn; LKML; Maling list - DRI developers
Subject: Re: [PATCH 1/2] drm/amd/powerplay: mark symbols static where possible

On Fri, Sep 30, 2016 at 8:16 AM, Christian König <deathsimple@vodafone.de> wrote:
> Both patches are Acked-by: Christian König <christian.koenig@amd.com>.

Applied patch 1.  I'd like to get Rex's ack on patch 2 before applying it.

Alex

>
> Regards,
> Christian.
>
>
> Am 30.09.2016 um 11:58 schrieb Baoyou Xie:
>>
>> We get a few warnings when building kernel with W=1:
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5:
>> warning: no previous prototype for 'fiji_setup_pwr_virus'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning:
>> no previous prototype for 'fiji_program_mem_timing_parameters'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5:
>> warning: no previous prototype for 'polaris10_avfs_event_mgr'
>> [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning:
>> no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes]
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning:
>> no previous prototype for 'cast_phw_smu7_power_state' 
>> [-Wmissing-prototypes] ....
>>
>> In fact, these functions are only used in the file in which they are 
>> declared and don't need a declaration, but can be made static.
>> So this patch marks these functions with 'static'.
>>
>> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
>> ---
>>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  5 ++-
>>   drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 12 +++---
>>   .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  6 +--
>>   .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  4 +-
>>   .../amd/powerplay/hwmgr/smu7_clockpowergating.c    | 10 ++---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 45
>> ++++++++++++----------
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    |  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 12 +++---
>>   .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  5 ++-
>>   9 files changed, 54 insertions(+), 47 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> index 7174f7a..bb8a345 100644
>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> @@ -436,7 +436,8 @@ static enum PP_StateUILabel 
>> power_state_convert(enum amd_pm_state_type  state)
>>         }
>>   }
>>   -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event 
>> event_id, void *input, void *output)
>> +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event
>> event_id,
>> +               void *input, void *output)
>>   {
>>         int ret = 0;
>>         struct pp_instance *pp_handle; @@ -475,7 +476,7 @@ int 
>> pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void 
>> *input,
>>         return ret;
>>   }
>>   -enum amd_pm_state_type pp_dpm_get_current_power_state(void 
>> *handle)
>> +static enum amd_pm_state_type pp_dpm_get_current_power_state(void
>> *handle)
>>   {
>>         struct pp_hwmgr *hwmgr;
>>         struct pp_power_state *state; diff --git 
>> a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index 7e4fcbb..b48d00f 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -66,7 +66,7 @@ static const struct cz_power_state 
>> *cast_const_PhwCzPowerState(
>>         return (struct cz_power_state *)hw_ps;
>>   }
>>   -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
>> +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
>>                                         uint32_t clock, uint32_t msg)
>>   {
>>         int i = 0;
>> @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct 
>> pp_hwmgr *hwmgr, void *input,
>>         return 0;
>>   }
>>   -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void 
>> *input,
>> +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void
>> *input,
>>                                 void *output, void *storage, int result)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr 
>> *)(hwmgr->backend); @@ -1225,7 +1225,7 @@ static int 
>> cz_hwmgr_backend_fini(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>   @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>         struct phm_clock_voltage_dependency_table *table = @@ -1277,7 
>> +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
>> +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
>>   {
>>         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>>   @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct 
>> pp_hwmgr *hwmgr,
>>         return result;
>>   }
>>   -int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
>> +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
>>   {
>>         return sizeof(struct cz_power_state);
>>   }
>> diff --git 
>> a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> index 7de701d..155cd0d 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>> @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr 
>> *hwmgr, uint32_t powerplay_caps)
>>   /**
>>    * Private Function to get the PowerPlay Table Address.
>>    */
>> -const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
>> +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
>>   {
>>         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
>>   @@ -1049,7 +1049,7 @@ static int check_powerplay_tables(
>>         return 0;
>>   }
>>   -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>> +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
>>   {
>>         int result = 0;
>>         const ATOM_Tonga_POWERPLAYTABLE *powerplay_table; @@ -1100,7 
>> +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr
>> *hwmgr)
>>         return result;
>>   }
>>   -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
>> +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
>>   {
>>         struct phm_ppt_v1_information *pp_table_information =
>>                 (struct phm_ppt_v1_information *)(hwmgr->pptable); 
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> index ccf7ebe..bd1f190 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct 
>> pp_hwmgr *hwmgr,
>>         return 0;
>>   }
>>   -int get_number_of_vce_state_table_entries(
>> +static int get_number_of_vce_state_table_entries(
>>                                                   struct pp_hwmgr *hwmgr)
>>   {
>>         const ATOM_PPLIB_POWERPLAYTABLE *table = @@ -1521,7 +1521,7 
>> @@ int get_number_of_vce_state_table_entries(
>>         return 0;
>>   }
>>   -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
>> +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
>>                                                         unsigned long i,
>>                                                         struct 
>> pp_vce_state *vce_state,
>>                                                         void 
>> **clock_info, diff --git 
>> a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> index 6eb6db1..f5a58d4 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
>> @@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_uvd_power_gating(hwmgr)) {
>>                 if
>> (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>> @@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_vce_power_gating(hwmgr))
>>                 return smum_send_msg_to_smc(hwmgr->smumgr,
>> @@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cf_want_vce_power_gating(hwmgr))
>>                 return smum_send_msg_to_smc(hwmgr->smumgr,
>> @@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>                         PHM_PlatformCaps_SamuPowerGating))
>> @@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
>> +static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
>>   {
>>         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>                         PHM_PlatformCaps_SamuPowerGating))
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index a3832f2..649fdd3 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -89,7 +89,7 @@ enum DPM_EVENT_SRC {
>>     static const unsigned long PhwVIslands_Magic = (unsigned 
>> long)(PHM_VIslands_Magic);
>>   -struct smu7_power_state *cast_phw_smu7_power_state(
>> +static struct smu7_power_state *cast_phw_smu7_power_state(
>>                                   struct pp_hw_power_state *hw_ps)
>>   {
>>         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), @@ 
>> -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state(
>>         return (struct smu7_power_state *)hw_ps;
>>   }
>>   -const struct smu7_power_state *cast_const_phw_smu7_power_state(
>> +static const struct smu7_power_state 
>> +*cast_const_phw_smu7_power_state(
>>                                  const struct pp_hw_power_state *hw_ps)
>>   {
>>         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), @@ 
>> -115,7 +115,7 @@ const struct smu7_power_state 
>> *cast_const_phw_smu7_power_state(
>>    * @param    hwmgr  the address of the powerplay hardware manager.
>>    * @return   always 0
>>    */
>> -int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
>> +static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
>>   {
>>         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
>>   @@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct 
>> pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>> +static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
>>   {
>>         uint32_t speedCntl = 0;
>>   @@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct 
>> pp_hwmgr
>> *hwmgr)
>>                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
>>   }
>>   -int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>> +static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
>>   {
>>         uint32_t link_width;
>>   @@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct
>> pp_hwmgr *hwmgr)
>>   * @param    pHwMgr  the address of the powerplay hardware manager.
>>   * @return   always PP_Result_OK
>>   */
>> -int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
>> +static int smu7_enable_smc_voltage_controller(struct pp_hwmgr 
>> +*hwmgr)
>>   {
>>         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
>>                 smum_send_msg_to_smc(hwmgr->smumgr,
>> PPSMC_MSG_Voltage_Cntl_Enable);
>> @@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct 
>> pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
>> +static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   @@ -1151,7 +1151,7 @@ static int
>> smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
>>         return smu7_disable_auto_throttle_source(hwmgr,
>> PHM_AutoThrottleSource_Thermal);
>>   }
>>   -int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>> +static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         data->pcie_performance_request = true; @@ -1159,7 +1159,7 @@ 
>> int smu7_pcie_performance_request(struct pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>> +static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>>   {
>>         int tmp_result = 0;
>>         int result = 0;
>> @@ -1854,7 +1854,7 @@ static int
>> smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
>> +static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
>>   {
>>         struct phm_ppt_v1_information *table_info =
>>                        (struct phm_ppt_v1_information 
>> *)(hwmgr->pptable); @@ -2243,7 +2243,7 @@ static int 
>> smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>> +static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data;
>>         int result;
>> @@ -3662,14 +3662,16 @@ static int smu7_set_max_fan_pwm_output(struct
>> pp_hwmgr *hwmgr, uint16_t us_max_f
>>                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
>>   }
>>   -int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool
>> has_display)
>> +static int
>> +smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool 
>> +has_display)
>>   {
>>         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay :
>> (PPSMC_Msg)PPSMC_NoDisplay;
>>         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
>>   }
>>   -int smu7_notify_smc_display_config_after_ps_adjustment(struct 
>> pp_hwmgr
>> *hwmgr)
>> +static int
>> +smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
>> *hwmgr)
>>   {
>>         uint32_t num_active_displays = 0;
>>         struct cgs_display_info info = {0}; @@ -3691,7 +3693,7 @@ int 
>> smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
>>   * @param    hwmgr  the address of the powerplay hardware manager.
>>   * @return   always OK
>>   */
>> -int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>> +static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         uint32_t num_active_displays = 0; @@ -3741,7 +3743,7 @@ int 
>> smu7_program_display_gap(struct pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_display_configuration_changed_task(struct pp_hwmgr 
>> *hwmgr)
>> +static int smu7_display_configuration_changed_task(struct pp_hwmgr
>> *hwmgr)
>>   {
>>         return smu7_program_display_gap(hwmgr);
>>   }
>> @@ -3765,13 +3767,14 @@ static int smu7_set_max_fan_rpm_output(struct
>> pp_hwmgr *hwmgr, uint16_t us_max_f
>>                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
>>   }
>>   -int smu7_register_internal_thermal_interrupt(struct pp_hwmgr 
>> *hwmgr,
>> +static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr
>> *hwmgr,
>>                                         const void
>> *thermal_interrupt_info)
>>   {
>>         return 0;
>>   }
>>   -bool 
>> smu7_check_smc_update_required_for_display_configuration(struct
>> pp_hwmgr *hwmgr)
>> +static bool
>> +smu7_check_smc_update_required_for_display_configuration(struct 
>> +pp_hwmgr
>> *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>         bool is_update_required = false; @@ -3800,7 +3803,9 @@ static 
>> inline bool smu7_are_power_levels_equal(const struct 
>> smu7_performance_lev
>>                   (pl1->pcie_lane == pl2->pcie_lane));
>>   }
>>   -int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct 
>> pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, 
>> bool
>> *equal)
>> +static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
>> +               const struct pp_hw_power_state *pstate1,
>> +               const struct pp_hw_power_state *pstate2, bool *equal)
>>   {
>>         const struct smu7_power_state *psa = 
>> cast_const_phw_smu7_power_state(pstate1);
>>         const struct smu7_power_state *psb = 
>> cast_const_phw_smu7_power_state(pstate2);
>> @@ -3831,7 +3836,7 @@ int smu7_check_states_equal(struct pp_hwmgr 
>> *hwmgr, const struct pp_hw_power_sta
>>         return 0;
>>   }
>>   -int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
>> +static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   @@ -3960,7 +3965,7 @@ static int smu7_init_sclk_threshold(struct 
>> pp_hwmgr *hwmgr)
>>         return 0;
>>   }
>>   -int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
>> +static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
>>   {
>>         int tmp_result, result = 0;
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> index 76310ac..e7e8944 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> @@ -2049,7 +2049,7 @@ int fiji_thermal_setup_fan_table(struct 
>> pp_hwmgr
>> *hwmgr)
>>         return 0;
>>   }
>>   -int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
>> +static int fiji_program_mem_timing_parameters(struct pp_hwmgr 
>> +*hwmgr)
>>   {
>>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> index 02fe1df..b86e48f 100755
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> @@ -159,7 +159,7 @@ static int
>> fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>> +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>>   {
>>         int i, result = -1;
>>         uint32_t reg, data;
>> @@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr
>> *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>> +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
>>   {
>>         int result = 0;
>>         uint32_t table_start;
>> @@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr
>> *smumgr)
>>         return result;
>>   }
>>   -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
>> +static int fiji_setup_graphics_level_structure(struct pp_smumgr 
>> +*smumgr)
>>   {
>>         int32_t vr_config;
>>         uint32_t table_start;
>> @@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct
>> pp_smumgr *smumgr)
>>   }
>>     /* Work in Progress */
>> -int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>> +static int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr 
>> *)(smumgr->backend);
>>   @@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr)
>>   }
>>     /* Work in Progress */
>> -int fiji_save_vft_table(struct pp_smumgr *smumgr)
>> +static int fiji_save_vft_table(struct pp_smumgr *smumgr)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr 
>> *)(smumgr->backend);
>>   @@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr)
>>                 return -EINVAL;
>>   }
>>   -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool 
>> smu_started)
>> +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool
>> smu_started)
>>   {
>>         struct fiji_smumgr *priv = (struct fiji_smumgr 
>> *)(smumgr->backend);
>>   diff --git 
>> a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> index 5c3598a..f38a687 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
>> @@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr
>> *smumgr)
>>   }
>>     -int polaris10_setup_graphics_level_structure(struct pp_smumgr
>> *smumgr)
>> +static int polaris10_setup_graphics_level_structure(struct pp_smumgr
>> *smumgr)
>>   {
>>         uint32_t vr_config;
>>         uint32_t dpm_table_start;
>> @@ -172,7 +172,8 @@ int 
>> polaris10_setup_graphics_level_structure(struct
>> pp_smumgr *smumgr)
>>         return 0;
>>   }
>>   -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool
>> SMU_VFT_INTACT)
>> +static int
>> +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool 
>> +SMU_VFT_INTACT)
>>   {
>>         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr 
>> *)(smumgr->backend);
>>
>
>
>
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