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[PATCH v3 0/5] AT91: sckc improvements

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  [PATCH v3 0/5] AT91: sckc improvements Alexandre Belloni <alexandre.belloni@free-electrons.com> - 2016-09-20 23:00 +0200
    [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support Alexandre Belloni <alexandre.belloni@free-electrons.com> - 2016-09-20 23:00 +0200
      Re: [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support Stephen Boyd <sboyd@codeaurora.org> - 2016-09-21 02:10 +0200
    [PATCH v3 3/5] clk: at91: sckc: optimize boot time Alexandre Belloni <alexandre.belloni@free-electrons.com> - 2016-09-20 23:10 +0200
      Re: [PATCH v3 3/5] clk: at91: sckc: optimize boot time Stephen Boyd <sboyd@codeaurora.org> - 2016-09-21 02:10 +0200
    [PATCH v3 4/5] ARM: dts: at91: sama5d4: use proper sckc compatible Alexandre Belloni <alexandre.belloni@free-electrons.com> - 2016-09-20 23:10 +0200

#1487637 — [PATCH v3 0/5] AT91: sckc improvements

Hi,

This patch set improves the slow clock controller driver.

The first patch simply moves some code around to avoid having extern
functions declared.

The second patch adds support for the SCKC found on sama5d4 and later.
It is notably missing the OSC32EN bit.

The third patch is an optimization. Trying to find wether the slow
oscillator is already stable to avoid waiting 1.2s twice in the boot
process.

Like discussed on IRC, the clk patches can probably go in v4.9 through the clk
tree. I'll take both dtsi patches through the at91 tree for v4.10.

Changes in v3:
 - rebased on clk-next to get the clk_hw rework
 - use a fixed clock for the rc oscillator on sama5d4
 - reordered patches

Changes in v2:
 - Fixed a typo pointed by Boris


Alexandre Belloni (5):
  clk: at91: move slow clock controller clocks to sckc.c
  clk: at91: Add sama5d4 sckc support
  clk: at91: sckc: optimize boot time
  ARM: dts: at91: sama5d4: use proper sckc compatible
  ARM: dts: at91: sama5d2: use correct sckc compatible

 .../devicetree/bindings/clock/at91-clock.txt       |   3 +-
 arch/arm/boot/dts/sama5d2.dtsi                     |  26 +-
 arch/arm/boot/dts/sama5d4.dtsi                     |  27 +-
 drivers/clk/at91/clk-slow.c                        | 365 ----------------
 drivers/clk/at91/sckc.c                            | 464 ++++++++++++++++++++-
 drivers/clk/at91/sckc.h                            |  22 -
 6 files changed, 473 insertions(+), 434 deletions(-)
 delete mode 100644 drivers/clk/at91/sckc.h

-- 
2.9.3

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#1487638 — [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support

Starting with sama5d4, the crystal oscillator is always enabled at startup
and the SCKC doesn't have an OSC32EN bit anymore.

Add support for that new controller.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 .../devicetree/bindings/clock/at91-clock.txt       |   3 +-
 drivers/clk/at91/sckc.c                            | 100 +++++++++++++++++++++
 2 files changed, 102 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index 181bc8ac4e3a..5f3ad65daf69 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -6,7 +6,8 @@ This binding uses the common clock binding[1].
 
 Required properties:
 - compatible : shall be one of the following:
-	"atmel,at91sam9x5-sckc":
+	"atmel,at91sam9x5-sckc" or
+	"atmel,sama5d4-sckc":
 		at91 SCKC (Slow Clock Controller)
 		This node contains the slow clock definitions.
 
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index f6ed711af738..60d8225715a2 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -36,6 +36,15 @@ struct clk_slow_osc {
 
 #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
 
+struct clk_sama5d4_slow_osc {
+	struct clk_hw hw;
+	void __iomem *sckcr;
+	unsigned long startup_usec;
+	bool prepared;
+};
+
+#define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw)
+
 struct clk_slow_rc_osc {
 	struct clk_hw hw;
 	void __iomem *sckcr;
@@ -417,3 +426,94 @@ static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
 }
 CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
 	       of_at91sam9x5_sckc_setup);
+
+static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
+{
+	struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
+
+	if (osc->prepared)
+		return 0;
+
+	/*
+	 * Assume that if it has already been selected (for example by the
+	 * bootloader), enough time has aready passed.
+	 */
+	if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {
+		osc->prepared = true;
+		return 0;
+	}
+
+	usleep_range(osc->startup_usec, osc->startup_usec + 1);
+	osc->prepared = true;
+
+	return 0;
+}
+
+static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw)
+{
+	struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
+
+	return osc->prepared;
+}
+
+static const struct clk_ops sama5d4_slow_osc_ops = {
+	.prepare = clk_sama5d4_slow_osc_prepare,
+	.is_prepared = clk_sama5d4_slow_osc_is_prepared,
+};
+
+static void __init of_sama5d4_sckc_setup(struct device_node *np)
+{
+	void __iomem *regbase = of_iomap(np, 0);
+	struct clk_hw *hw;
+	struct clk_sama5d4_slow_osc *osc;
+	struct clk_init_data init;
+	const char *xtal_name;
+	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
+	bool bypass;
+	int ret;
+
+	if (!regbase)
+		return;
+
+	hw = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
+						      NULL, 0, 32768,
+						      250000000);
+	if (IS_ERR(hw))
+		return;
+
+	xtal_name = of_clk_get_parent_name(np, 0);
+
+	bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
+	if (!osc)
+		return;
+
+	init.name = parent_names[1];
+	init.ops = &sama5d4_slow_osc_ops;
+	init.parent_names = &xtal_name;
+	init.num_parents = 1;
+	init.flags = CLK_IGNORE_UNUSED;
+
+	osc->hw.init = &init;
+	osc->sckcr = regbase;
+	osc->startup_usec = 1200000;
+
+	if (bypass)
+		writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase);
+
+	hw = &osc->hw;
+	ret = clk_hw_register(NULL, &osc->hw);
+	if (ret) {
+		kfree(osc);
+		return;
+	}
+
+	hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
+	if (IS_ERR(hw))
+		return;
+
+	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
+	       of_sama5d4_sckc_setup);
-- 
2.9.3

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#1487730 — Re: [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support

On 09/20, Alexandre Belloni wrote:
> Starting with sama5d4, the crystal oscillator is always enabled at startup
> and the SCKC doesn't have an OSC32EN bit anymore.
> 
> Add support for that new controller.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1487639 — [PATCH v3 3/5] clk: at91: sckc: optimize boot time

Assume that if the oscillator is enabled (OSC32EN bit is present), the
delay has already elapsed as the bootloader probably waited for the
oscillator to settle. This could waste up to 1.2s.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 drivers/clk/at91/sckc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 60d8225715a2..b1265f2cdae7 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -69,7 +69,7 @@ static int clk_slow_osc_prepare(struct clk_hw *hw)
 	void __iomem *sckcr = osc->sckcr;
 	u32 tmp = readl(sckcr);
 
-	if (tmp & AT91_SCKC_OSC32BYP)
+	if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))
 		return 0;
 
 	writel(tmp | AT91_SCKC_OSC32EN, sckcr);
-- 
2.9.3

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#1487726 — Re: [PATCH v3 3/5] clk: at91: sckc: optimize boot time

On 09/20, Alexandre Belloni wrote:
> Assume that if the oscillator is enabled (OSC32EN bit is present), the
> delay has already elapsed as the bootloader probably waited for the
> oscillator to settle. This could waste up to 1.2s.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1487640 — [PATCH v3 4/5] ARM: dts: at91: sama5d4: use proper sckc compatible

Now that there is support for the sama5d4 slow clock controller, use its
driver.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/sama5d4.dtsi | 27 ++++-----------------------
 1 file changed, 4 insertions(+), 23 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 65e725fb5679..fe094263595c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1314,30 +1314,11 @@
 				status = "disabled";
 			};
 
-			sckc@fc068650 {
-				compatible = "atmel,at91sam9x5-sckc";
+			clk32k: sckc@fc068650 {
+				compatible = "atmel,sama5d4-sckc";
 				reg = <0xfc068650 0x4>;
-
-				slow_rc_osc: slow_rc_osc {
-					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
-					#clock-cells = <0>;
-					clock-frequency = <32768>;
-					clock-accuracy = <250000000>;
-					atmel,startup-time-usec = <75>;
-				};
-
-				slow_osc: slow_osc {
-					compatible = "atmel,at91sam9x5-clk-slow-osc";
-					#clock-cells = <0>;
-					clocks = <&slow_xtal>;
-					atmel,startup-time-usec = <1200000>;
-				};
-
-				clk32k: slowck {
-					compatible = "atmel,at91sam9x5-clk-slow";
-					#clock-cells = <0>;
-					clocks = <&slow_rc_osc &slow_osc>;
-				};
+				#clock-cells = <0>;
+				clocks = <&slow_xtal>;
 			};
 
 			rtc@fc0686b0 {
-- 
2.9.3

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