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Re: [PATCH 1/2] dt-bindings: msm8996-pcie-phy: add support for msm8996 pcie phy

Started byRob Herring <robh@kernel.org>
First post2016-09-16 16:00 +0200
Last post2016-09-16 18:50 +0200
Articles 2 — 2 participants

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  Re: [PATCH 1/2] dt-bindings: msm8996-pcie-phy: add support for  msm8996 pcie phy Rob Herring <robh@kernel.org> - 2016-09-16 16:00 +0200
    Re: [PATCH 1/2] dt-bindings: msm8996-pcie-phy: add support for  msm8996 pcie phy Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2016-09-16 18:50 +0200

#1485005 — Re: [PATCH 1/2] dt-bindings: msm8996-pcie-phy: add support for msm8996 pcie phy

FromRob Herring <robh@kernel.org>
Date2016-09-16 16:00 +0200
SubjectRe: [PATCH 1/2] dt-bindings: msm8996-pcie-phy: add support for msm8996 pcie phy
Message-ID<si1Qm-5pB-25@gated-at.bofh.it>
On Wed, Sep 07, 2016 at 11:55:32AM +0100, Srinivas Kandagatla wrote:
> This patch adds bindings for pcie phy on MSM8996.
> 
> This PHY has 3 Ports, including a common block. Each port is connected
> to one root complex. Each port has dedicated reset control lines apart
> from common reset and clocks for common block.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>  .../bindings/phy/qcom-msm8996-pcie-phy.txt         | 62 ++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
> new file mode 100644
> index 0000000..51930ed
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
> @@ -0,0 +1,62 @@
> +Qualcomm msm8996 pcie PHY
> +------------------------
> +
> +Required properties:
> +- compatible: compatible list, contains "qcom,msm8996-pcie-phy".

8994 has PCIe, this phy is completely different? And Archit mentioned 
another SoC, too.

Rob

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#1485174

FromSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date2016-09-16 18:50 +0200
Message-ID<si4uR-7hN-7@gated-at.bofh.it>
In reply to#1485005

On 16/09/16 14:52, Rob Herring wrote:
> On Wed, Sep 07, 2016 at 11:55:32AM +0100, Srinivas Kandagatla wrote:
>> This patch adds bindings for pcie phy on MSM8996.
>>
>> This PHY has 3 Ports, including a common block. Each port is connected
>> to one root complex. Each port has dedicated reset control lines apart
>> from common reset and clocks for common block.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>>  .../bindings/phy/qcom-msm8996-pcie-phy.txt         | 62 ++++++++++++++++++++++
>>  1 file changed, 62 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
>> new file mode 100644
>> index 0000000..51930ed
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
>> @@ -0,0 +1,62 @@
>> +Qualcomm msm8996 pcie PHY
>> +------------------------
>> +
>> +Required properties:
>> +- compatible: compatible list, contains "qcom,msm8996-pcie-phy".
>
> 8994 has PCIe, this phy is completely different? And Archit mentioned
> another SoC, too.

Recently I too learned that this phy IP is used across USB, UFS and 
other SOCs, so Am planning to dump this patchset and write one common 
driver.

Thanks,
srini
>
> Rob
>

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