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[RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

Started byRandy Li <ayaka@soulik.info>
First post2016-09-09 21:10 +0200
Last post2016-09-13 16:40 +0200
Articles 7 — 3 participants

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  [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform Randy Li <ayaka@soulik.info> - 2016-09-09 21:10 +0200
    [RESEND PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset Randy Li <ayaka@soulik.info> - 2016-09-09 21:10 +0200
    [RESEND PATCH v7 1/4] phy: Add reset callback Randy Li <ayaka@soulik.info> - 2016-09-09 21:10 +0200
      Re: [RESEND PATCH v7 1/4] phy: Add reset callback Heiko Stuebner <heiko@sntech.de> - 2016-09-10 11:00 +0200
    Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform Heiko Stuebner <heiko@sntech.de> - 2016-09-13 13:10 +0200
      Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288  platform ayaka <ayaka@soulik.info> - 2016-09-13 13:30 +0200
        Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform Heiko Stuebner <heiko@sntech.de> - 2016-09-13 16:40 +0200

#1480264 — [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

FromRandy Li <ayaka@soulik.info>
Date2016-09-09 21:10 +0200
Subject[RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform
Message-ID<sfzlw-6S1-5@gated-at.bofh.it>
  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Changelog:
 - v7:
    adding a wrapper for the reset operation for phy
    using that wrapper
 - v6:
    move pwms pinctrl to pwms node
    fix the order of the dtb file in Makefile
 - v5:
   - correct the mail format
 - v4:
   - re-order some nodes in alphabetical order
   - fix some minor bugs
   - add a entry in vendor list
 - v3:
   - fixing the rtc clock, using clock source from PMIC
   - enable the tmu
   - enable the fimc for elite board
   - suuport the audio codec at elite board
   - fixing minor bugs in the last commit
 - v2:
   - removing rtc node
     the clock source driver is not done yet.
   - adding exynos-bus
   - fixing the MFC

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
    wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
 drivers/phy/phy-core.c                               | 14 ++++++++++++++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 drivers/usb/dwc2/core_intr.c                         | 11 +++++++++++
 include/linux/phy/phy.h                              |  3 +++
 6 files changed, 55 insertions(+)

-- 
2.7.4

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#1480266 — [RESEND PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

FromRandy Li <ayaka@soulik.info>
Date2016-09-09 21:10 +0200
Subject[RESEND PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
Message-ID<sfzlw-6S1-17@gated-at.bofh.it>
In reply to#1480264
The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBOTG_PHY>;
+				reset-names = "phy-reset";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBHOST1_PHY>;
+				reset-names = "phy-reset";
 			};
 		};
 	};
-- 
2.7.4

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#1480267 — [RESEND PATCH v7 1/4] phy: Add reset callback

FromRandy Li <ayaka@soulik.info>
Date2016-09-09 21:10 +0200
Subject[RESEND PATCH v7 1/4] phy: Add reset callback
Message-ID<sfzlw-6S1-27@gated-at.bofh.it>
In reply to#1480264
The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 drivers/phy/phy-core.c  | 14 ++++++++++++++
 include/linux/phy/phy.h |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 8eca906..32e838d 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -357,6 +357,20 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
 }
 EXPORT_SYMBOL_GPL(phy_set_mode);
 
+int phy_reset(struct phy *phy)
+{
+	int ret;
+	if (!phy || !phy->ops->reset)
+		return 0;
+
+	mutex_lock(&phy->mutex);
+	ret = phy->ops->reset(phy);
+	mutex_unlock(&phy->mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phy_reset);
+
 /**
  * _of_phy_get() - lookup and obtain a reference to a phy by phandle
  * @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..7978df6 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
 	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
+	int	(*reset)(struct phy *phy);
 	struct module *owner;
 };
 
@@ -136,6 +138,7 @@ int phy_exit(struct phy *phy);
 int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
 int phy_set_mode(struct phy *phy, enum phy_mode mode);
+int phy_reset(struct phy *phy);
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return phy->attrs.bus_width;
-- 
2.7.4

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#1480536 — Re: [RESEND PATCH v7 1/4] phy: Add reset callback

FromHeiko Stuebner <heiko@sntech.de>
Date2016-09-10 11:00 +0200
SubjectRe: [RESEND PATCH v7 1/4] phy: Add reset callback
Message-ID<sfMiJ-6sU-3@gated-at.bofh.it>
In reply to#1480267
Hi Randy,

Am Samstag, 10. September 2016, 02:59:37 CEST schrieb Randy Li:
> The only use for this is for solving a hardware design problem in
> usb of Rockchip RK3288.
> 
> Signed-off-by: Randy Li <ayaka@soulik.info>

When sending new versions, please carry over received Reviewed- / Tested- / 
Acked-by tags received on old versions.

So again, to me this looks good.

Although Kishon suggested earlier to have the init callback do the reset and 
simply call it again in the reset-case, the whole refcounting done in phy_init 
and phy_exit (phy->init_count) really shows that init and exit should be 
called pairwise, so that extra reset callback seems justified, so from my phy-
noob-pov

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  drivers/phy/phy-core.c  | 14 ++++++++++++++
>  include/linux/phy/phy.h |  3 +++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index 8eca906..32e838d 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -357,6 +357,20 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
>  }
>  EXPORT_SYMBOL_GPL(phy_set_mode);
> 
> +int phy_reset(struct phy *phy)
> +{
> +	int ret;
> +	if (!phy || !phy->ops->reset)
> +		return 0;
> +
> +	mutex_lock(&phy->mutex);
> +	ret = phy->ops->reset(phy);
> +	mutex_unlock(&phy->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(phy_reset);
> +
>  /**
>   * _of_phy_get() - lookup and obtain a reference to a phy by phandle
>   * @np: device_node for which to get the phy
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index f08b672..7978df6 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -36,6 +36,7 @@ enum phy_mode {
>   * @power_on: powering on the phy
>   * @power_off: powering off the phy
>   * @set_mode: set the mode of the phy
> + * @reset: reseting the phy
>   * @owner: the module owner containing the ops
>   */
>  struct phy_ops {
> @@ -44,6 +45,7 @@ struct phy_ops {
>  	int	(*power_on)(struct phy *phy);
>  	int	(*power_off)(struct phy *phy);
>  	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
> +	int	(*reset)(struct phy *phy);
>  	struct module *owner;
>  };
> 
> @@ -136,6 +138,7 @@ int phy_exit(struct phy *phy);
>  int phy_power_on(struct phy *phy);
>  int phy_power_off(struct phy *phy);
>  int phy_set_mode(struct phy *phy, enum phy_mode mode);
> +int phy_reset(struct phy *phy);
>  static inline int phy_get_bus_width(struct phy *phy)
>  {
>  	return phy->attrs.bus_width;

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#1482372

FromHeiko Stuebner <heiko@sntech.de>
Date2016-09-13 13:10 +0200
Message-ID<sgTLc-11k-11@gated-at.bofh.it>
In reply to#1480264
Hi Randy,

could you check if the other host-only dwc2 are also affected by this (rk3188, 
rk3036) please? Because they also seem to act up in some strange way 
sometimes.

Thanks
Heiko

Am Samstag, 10. September 2016, 02:59:36 CEST schrieb Randy Li:
>   At this stage it is the only "full features" and well verified
> USB EHCI controller in this platform. More review is always necessary.
>
> Changelog:
>  - v7:
>     adding a wrapper for the reset operation for phy
>     using that wrapper
>  - v6:
>     move pwms pinctrl to pwms node
>     fix the order of the dtb file in Makefile
>  - v5:
>    - correct the mail format
>  - v4:
>    - re-order some nodes in alphabetical order
>    - fix some minor bugs
>    - add a entry in vendor list
>  - v3:
>    - fixing the rtc clock, using clock source from PMIC
>    - enable the tmu
>    - enable the fimc for elite board
>    - suuport the audio codec at elite board
>    - fixing minor bugs in the last commit
>  - v2:
>    - removing rtc node
>      the clock source driver is not done yet.
>    - adding exynos-bus
>    - fixing the MFC
> 
> Randy Li (4):
>   phy: Add reset callback
>   phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
>     wakeup
>   usb: dwc2: assert phy reset when waking up in rk3288 platform
>   ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
> 
>  .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
>  arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
>  drivers/phy/phy-core.c                               | 14 ++++++++++++++
>  drivers/phy/phy-rockchip-usb.c                       | 20
> ++++++++++++++++++++ drivers/usb/dwc2/core_intr.c                         |
> 11 +++++++++++ include/linux/phy/phy.h                              |  3
> +++
>  6 files changed, 55 insertions(+)

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#1482381 — Re: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

Fromayaka <ayaka@soulik.info>
Date2016-09-13 13:30 +0200
SubjectRe: [RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform
Message-ID<sgU4x-18N-11@gated-at.bofh.it>
In reply to#1482372

On 09/13/2016 07:06 PM, Heiko Stuebner wrote:
> Hi Randy,
>
> could you check if the other host-only dwc2 are also affected by this (rk3188,
> rk3036) please? Because they also seem to act up in some strange way
But I don't have those board currently. I would arrange them anyway.
Btw, I would send a new version to correct the fault reported by the 
auto build machine.
> sometimes.
>
> Thanks
> Heiko
>
> Am Samstag, 10. September 2016, 02:59:36 CEST schrieb Randy Li:
>>    At this stage it is the only "full features" and well verified
>> USB EHCI controller in this platform. More review is always necessary.
>>
>> Changelog:
>>   - v7:
>>      adding a wrapper for the reset operation for phy
>>      using that wrapper
>>   - v6:
>>      move pwms pinctrl to pwms node
>>      fix the order of the dtb file in Makefile
>>   - v5:
>>     - correct the mail format
>>   - v4:
>>     - re-order some nodes in alphabetical order
>>     - fix some minor bugs
>>     - add a entry in vendor list
>>   - v3:
>>     - fixing the rtc clock, using clock source from PMIC
>>     - enable the tmu
>>     - enable the fimc for elite board
>>     - suuport the audio codec at elite board
>>     - fixing minor bugs in the last commit
>>   - v2:
>>     - removing rtc node
>>       the clock source driver is not done yet.
>>     - adding exynos-bus
>>     - fixing the MFC
>>
>> Randy Li (4):
>>    phy: Add reset callback
>>    phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
>>      wakeup
>>    usb: dwc2: assert phy reset when waking up in rk3288 platform
>>    ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
>>
>>   .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
>>   arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
>>   drivers/phy/phy-core.c                               | 14 ++++++++++++++
>>   drivers/phy/phy-rockchip-usb.c                       | 20
>> ++++++++++++++++++++ drivers/usb/dwc2/core_intr.c                         |
>> 11 +++++++++++ include/linux/phy/phy.h                              |  3
>> +++
>>   6 files changed, 55 insertions(+)

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#1482546

FromHeiko Stuebner <heiko@sntech.de>
Date2016-09-13 16:40 +0200
Message-ID<sgX2q-39g-25@gated-at.bofh.it>
In reply to#1482381
Am Dienstag, 13. September 2016, 19:26:03 CEST schrieb ayaka:
> On 09/13/2016 07:06 PM, Heiko Stuebner wrote:
> > Hi Randy,
> > 
> > could you check if the other host-only dwc2 are also affected by this
> > (rk3188, rk3036) please? Because they also seem to act up in some strange
> > way
> But I don't have those board currently. I would arrange them anyway.
> Btw, I would send a new version to correct the fault reported by the
> auto build machine.

What I meant was, if you could check with some hardware-people first, if the
other host-only dwc2 are supposedly also affected. Right now I'm trying to
determine if this effect is somehow related with the usb debounce issue
I'm seeing with some recent dwc2 patches [0].


Heiko

[0] http://lists.infradead.org/pipermail/linux-rockchip/2016-September/012141.html
https://git.kernel.org/cgit/linux/kernel/git/balbi/usb.git/commit/?h=testing/next&id=2938fc63e0c26bf694436ac81bc776c8b7eced0c

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