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[PATCH 0/6] arm64: dts: rockchip: added some pd nodes for rk3399 Soc

Started byElaine Zhang <zhangqing@rock-chips.com>
First post2016-09-09 09:50 +0200
Last post2016-09-09 09:50 +0200
Articles 6 — 1 participant

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  [PATCH 0/6] arm64: dts: rockchip: added some pd nodes for rk3399 Soc Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200
    [PATCH 1/6] arm64: dts: rockchip: add pd_edp node for rk3399 Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200
    [PATCH 3/6] arm64: dts: rockchip: add pd_perihp power node for rk3399 Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200
    [PATCH 4/6] arm64: dts: rockchip: add pd_sd power node for rk3399 Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200
    [PATCH 5/6] arm64: dts: rockchip: add pd_sdioaudio power node for rk3399 Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200
    [PATCH 6/6] arm64: dts: rockchip: add pd_usb3 power node for rk3399 Elaine Zhang <zhangqing@rock-chips.com> - 2016-09-09 09:50 +0200

#1479707 — [PATCH 0/6] arm64: dts: rockchip: added some pd nodes for rk3399 Soc

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 0/6] arm64: dts: rockchip: added some pd nodes for rk3399 Soc
Message-ID<sfoJs-8tz-9@gated-at.bofh.it>
1.added the edp,emmc,perihp(pcie,usb2),sd,
sdioaudio(i2s,spdif,sdio,spi5),usb3 pd nodes
2.added the pd consumers node

Elaine Zhang (6):
  arm64: dts: rockchip: add pd_edp node for rk3399
  arm64: dts: rockchip: add pd_emmc power node for rk3399
  arm64: dts: rockchip: add pd_perihp power node for rk3399
  arm64: dts: rockchip: add pd_sd power node for rk3399
  arm64: dts: rockchip: add pd_sdioaudio power node for rk3399
  arm64: dts: rockchip: add pd_usb3 power node for rk3399

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 95 ++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

-- 
1.9.1

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#1479708 — [PATCH 1/6] arm64: dts: rockchip: add pd_edp node for rk3399

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 1/6] arm64: dts: rockchip: add pd_edp node for rk3399
Message-ID<sfoJs-8tz-11@gated-at.bofh.it>
In reply to#1479707
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193dc64e..52b4bfb52288 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -823,6 +823,10 @@
 			};
 
 			/* These power domains are grouped by VD_LOGIC */
+			pd_edp@RK3399_PD_EDP {
+				reg = <RK3399_PD_EDP>;
+				clocks = <&cru PCLK_EDP_CTRL>;
+			};
 			pd_gmac@RK3399_PD_GMAC {
 				reg = <RK3399_PD_GMAC>;
 				clocks = <&cru ACLK_GMAC>;
-- 
1.9.1

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#1479711 — [PATCH 3/6] arm64: dts: rockchip: add pd_perihp power node for rk3399

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 3/6] arm64: dts: rockchip: add pd_perihp power node for rk3399
Message-ID<sfoJs-8tz-15@gated-at.bofh.it>
In reply to#1479707
1.add pd node for RK3399 Soc
2.create power domain tree
3.add qos node for domain,include usb2,pcie
4.add the pd_perihp consumers node

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 34 ++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 869b52d60b73..52eeb007fddf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -303,6 +303,7 @@
 		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 			 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
 		reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+		power-domains = <&power RK3399_PD_PERIHP>;
 		status = "disabled";
 
 		pcie0_intc: interrupt-controller {
@@ -320,6 +321,7 @@
 		clock-names = "hclk_host0", "hclk_host0_arb";
 		phys = <&u2phy0_host>;
 		phy-names = "usb";
+		power-domains = <&power RK3399_PD_PERIHP>;
 		status = "disabled";
 	};
 
@@ -329,6 +331,7 @@
 		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 		clock-names = "hclk_host0", "hclk_host0_arb";
+		power-domains = <&power RK3399_PD_PERIHP>;
 		status = "disabled";
 	};
 
@@ -340,6 +343,7 @@
 		clock-names = "hclk_host1", "hclk_host1_arb";
 		phys = <&u2phy1_host>;
 		phy-names = "usb";
+		power-domains = <&power RK3399_PD_PERIHP>;
 		status = "disabled";
 	};
 
@@ -349,6 +353,7 @@
 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 		clock-names = "hclk_host1", "hclk_host1_arb";
+		power-domains = <&power RK3399_PD_PERIHP>;
 		status = "disabled";
 	};
 
@@ -699,6 +704,20 @@
 		compatible = "syscon";
 		reg = <0x0 0xffa5c000 0x0 0x20>;
 	};
+	qos_pcie: qos@ffa60080 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60080 0x0 0x20>;
+	};
+
+	qos_usb_host0: qos@ffa60100 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60100 0x0 0x20>;
+	};
+
+	qos_usb_host1: qos@ffa60180 {
+		compatible = "syscon";
+		reg = <0x0 0xffa60180 0x0 0x20>;
+	};
 
 	qos_hdcp: qos@ffa90000 {
 		compatible = "syscon";
@@ -770,6 +789,11 @@
 		reg = <0x0 0xffad0000 0x0 0x20>;
 	};
 
+	qos_perihp: qos@ffad8080 {
+		compatible = "syscon";
+		reg = <0x0 0xffad8080 0x0 0x20>;
+	};
+
 	qos_gpu: qos@ffae0000 {
 		compatible = "syscon";
 		reg = <0x0 0xffae0000 0x0 0x20>;
@@ -842,6 +866,16 @@
 				clocks = <&cru ACLK_GMAC>;
 				pm_qos = <&qos_gmac>;
 			};
+			pd_perihp@RK3399_PD_PERIHP {
+				reg = <RK3399_PD_PERIHP>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&cru ACLK_PERIHP>;
+				pm_qos = <&qos_perihp>,
+					 <&qos_pcie>,
+					 <&qos_usb_host0>,
+					 <&qos_usb_host1>;
+			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
-- 
1.9.1

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#1479712 — [PATCH 4/6] arm64: dts: rockchip: add pd_sd power node for rk3399

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 4/6] arm64: dts: rockchip: add pd_sd power node for rk3399
Message-ID<sfoJs-8tz-21@gated-at.bofh.it>
In reply to#1479707
1.add pd node for RK3399 Soc
2.create power domain tree
3.add qos node for domain
4.add the pd_sd consumers node

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 52eeb007fddf..e2ecad651cac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -253,6 +253,7 @@
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		power-domains = <&power RK3399_PD_SD>;
 		status = "disabled";
 	};
 
@@ -718,6 +719,10 @@
 		compatible = "syscon";
 		reg = <0x0 0xffa60180 0x0 0x20>;
 	};
+	qos_sd: qos@ffa74000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa74000 0x0 0x20>;
+	};
 
 	qos_hdcp: qos@ffa90000 {
 		compatible = "syscon";
@@ -875,6 +880,13 @@
 					 <&qos_pcie>,
 					 <&qos_usb_host0>,
 					 <&qos_usb_host1>;
+
+				pd_sd@RK3399_PD_SD {
+					reg = <RK3399_PD_SD>;
+					clocks = <&cru HCLK_SDMMC>,
+						 <&cru SCLK_SDMMC>;
+					pm_qos = <&qos_sd>;
+				};
 			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
-- 
1.9.1

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#1479716 — [PATCH 5/6] arm64: dts: rockchip: add pd_sdioaudio power node for rk3399

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 5/6] arm64: dts: rockchip: add pd_sdioaudio power node for rk3399
Message-ID<sfoJs-8tz-31@gated-at.bofh.it>
In reply to#1479707
1.add pd node for RK3399 Soc
2.create power domain tree
3.add qos node for domain
4.add the pd_sdioaudio consumers node

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e2ecad651cac..4b67a249b3bc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -240,6 +240,7 @@
 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
@@ -605,6 +606,7 @@
 		pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
@@ -724,6 +726,11 @@
 		reg = <0x0 0xffa74000 0x0 0x20>;
 	};
 
+	qos_sdioaudio: qos@ffa76000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa76000 0x0 0x20>;
+	};
+
 	qos_hdcp: qos@ffa90000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa90000 0x0 0x20>;
@@ -888,6 +895,11 @@
 					pm_qos = <&qos_sd>;
 				};
 			};
+			pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+				reg = <RK3399_PD_SDIOAUDIO>;
+				clocks = <&cru HCLK_SDIO>;
+				pm_qos = <&qos_sdioaudio>;
+			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
@@ -1281,6 +1293,7 @@
 		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spdif_bus>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
@@ -1295,6 +1308,7 @@
 		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s0_8ch_bus>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
@@ -1308,6 +1322,7 @@
 		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_2ch_bus>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
@@ -1319,6 +1334,7 @@
 		dma-names = "tx", "rx";
 		clock-names = "i2s_clk", "i2s_hclk";
 		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
+		power-domains = <&power RK3399_PD_SDIOAUDIO>;
 		status = "disabled";
 	};
 
-- 
1.9.1

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#1479717 — [PATCH 6/6] arm64: dts: rockchip: add pd_usb3 power node for rk3399

FromElaine Zhang <zhangqing@rock-chips.com>
Date2016-09-09 09:50 +0200
Subject[PATCH 6/6] arm64: dts: rockchip: add pd_usb3 power node for rk3399
Message-ID<sfoJs-8tz-35@gated-at.bofh.it>
In reply to#1479707
1.add pd node for RK3399 Soc
2.create power domain tree
3.add qos node for domain

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4b67a249b3bc..1cae76afc8ca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -703,10 +703,12 @@
 		compatible = "syscon";
 		reg = <0x0 0xffa58000 0x0 0x20>;
 	};
+
 	qos_gmac: qos@ffa5c000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa5c000 0x0 0x20>;
 	};
+
 	qos_pcie: qos@ffa60080 {
 		compatible = "syscon";
 		reg = <0x0 0xffa60080 0x0 0x20>;
@@ -721,6 +723,17 @@
 		compatible = "syscon";
 		reg = <0x0 0xffa60180 0x0 0x20>;
 	};
+
+	qos_usb_otg0: qos@ffa70000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70000 0x0 0x20>;
+	};
+
+	qos_usb_otg1: qos@ffa70080 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70080 0x0 0x20>;
+	};
+
 	qos_sd: qos@ffa74000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa74000 0x0 0x20>;
@@ -900,6 +913,12 @@
 				clocks = <&cru HCLK_SDIO>;
 				pm_qos = <&qos_sdioaudio>;
 			};
+			pd_usb3@RK3399_PD_USB3 {
+				reg = <RK3399_PD_USB3>;
+				clocks = <&cru ACLK_USB3>;
+				pm_qos = <&qos_usb_otg0>,
+					 <&qos_usb_otg1>;
+			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
-- 
1.9.1

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