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Re: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some SoC-specific devices

Started byShawn Guo <shawnguo@kernel.org>
First post2016-09-08 04:40 +0200
Last post2016-09-08 17:40 +0200
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  Re: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some  SoC-specific devices Shawn Guo <shawnguo@kernel.org> - 2016-09-08 04:40 +0200
    RE: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some  SoC-specific devices "S.H. Xie" <shaohui.xie@nxp.com> - 2016-09-08 17:40 +0200

#1478737 — Re: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some SoC-specific devices

FromShawn Guo <shawnguo@kernel.org>
Date2016-09-08 04:40 +0200
SubjectRe: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some SoC-specific devices
Message-ID<seXpT-8mj-1@gated-at.bofh.it>
On Mon, Sep 05, 2016 at 06:01:29PM +0800, shh.xie@gmail.com wrote:
> From: Shaohui Xie <Shaohui.Xie@nxp.com>
> 
> SCFG and DCFG are SoC-specific devices can be found on SoCs like LS1021A,
> LS1043A and LS1046A, this patch updates bindings for SCFG and DCFG to
> reflect more SoCs.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
> ---
> changes in V2:
> new patch.
> 
>  Documentation/devicetree/bindings/arm/fsl.txt | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index dbbc095..6f92d0b 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
>  Required root node compatible properties:
>    - compatible = "fsl,ls1021a";
>  
> -Freescale LS1021A SoC-specific Device Tree Bindings
> +Freescale SoC-specific Device Tree Bindings
>  -------------------------------------------
>  
>  Freescale SCFG
> @@ -105,7 +105,10 @@ Freescale SCFG
>  configuration and status registers for the chip. Such as getting PEX port
>  status.
>    Required properties:
> -  - compatible: should be "fsl,ls1021a-scfg"
> +  - compatible: Should contain a chip-specific compatible string,
> +	Chip-specific strings are of the form "fsl,<chip>-scfg", such as:
> +	"fsl,ls1021a-scfg"

Per Documentation/devicetree/bindings/submitting-patches.txt, the known
values of "<chip>" should be documented.

Shawn

> +
>    - reg: should contain base address and length of SCFG memory-mapped registers
>  
>  Example:
> @@ -119,7 +122,10 @@ Freescale DCFG
>  configuration and status for the device. Such as setting the secondary
>  core start address and release the secondary core from holdoff and startup.
>    Required properties:
> -  - compatible: should be "fsl,ls1021a-dcfg"
> +  - compatible: Should contain a chip-specific compatible string,
> +	Chip-specific strings are of the form "fsl,<chip>-dcfg", such as:
> +	"fsl,ls1021a-dcfg"
> +
>    - reg : should contain base address and length of DCFG memory-mapped registers
>  
>  Example:
> -- 
> 2.1.0.27.g96db324
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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#1479330

From"S.H. Xie" <shaohui.xie@nxp.com>
Date2016-09-08 17:40 +0200
Message-ID<sf9AK-7xA-15@gated-at.bofh.it>
In reply to#1478737
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Thursday, September 08, 2016 10:30 AM
> To: shh.xie@gmail.com
> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-arm-kernel@lists.infradead.org; catalin.marinas@arm.com;
> will.deacon@arm.com; linux-kernel@vger.kernel.org; S.H. Xie
> <shaohui.xie@nxp.com>; arnd@arndb.de
> Subject: Re: [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some SoC-
> specific devices
> 
> On Mon, Sep 05, 2016 at 06:01:29PM +0800, shh.xie@gmail.com wrote:
> > From: Shaohui Xie <Shaohui.Xie@nxp.com>
> >
> > SCFG and DCFG are SoC-specific devices can be found on SoCs like
> > LS1021A, LS1043A and LS1046A, this patch updates bindings for SCFG and
> > DCFG to reflect more SoCs.
> >
> > Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
> > ---
> > changes in V2:
> > new patch.
> >
> >  Documentation/devicetree/bindings/arm/fsl.txt | 12 +++++++++---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> > b/Documentation/devicetree/bindings/arm/fsl.txt
> > index dbbc095..6f92d0b 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > @@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
> > Required root node compatible properties:
> >    - compatible = "fsl,ls1021a";
> >
> > -Freescale LS1021A SoC-specific Device Tree Bindings
> > +Freescale SoC-specific Device Tree Bindings
> >  -------------------------------------------
> >
> >  Freescale SCFG
> > @@ -105,7 +105,10 @@ Freescale SCFG
> >  configuration and status registers for the chip. Such as getting PEX
> > port  status.
> >    Required properties:
> > -  - compatible: should be "fsl,ls1021a-scfg"
> > +  - compatible: Should contain a chip-specific compatible string,
> > +	Chip-specific strings are of the form "fsl,<chip>-scfg", such as:
> > +	"fsl,ls1021a-scfg"
> 
> Per Documentation/devicetree/bindings/submitting-patches.txt, the known values
> of "<chip>" should be documented.
Will add the supported chips in next version.

Thank you!

Shaohui

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