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RE: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits

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  RE: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits "Li, Liang Z" <liang.z.li@intel.com> - 2016-09-01 16:30 +0200
    Re: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits Paolo Bonzini <pbonzini@redhat.com> - 2016-09-01 17:20 +0200

#1474438 — RE: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits

Intel SDM doesn't describe whether the A bit will be set or not when CPU accesses  a no present EPT page table entry? 
even this patch works for the current CPU, it's not good to make such an assumption. 

Should we revert it?

Thanks!
Liang


> -----Original Message-----
> From: kvm-owner@vger.kernel.org [mailto:kvm-owner@vger.kernel.org]
> On Behalf Of Bandan Das
> Sent: Wednesday, July 13, 2016 6:19 AM
> To: kvm@vger.kernel.org
> Cc: pbonzini@redhat.com; guangrong.xiao@linux.intel.com;
> kernellwp@gmail.com; linux-kernel@vger.kernel.org
> Subject: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits
> 
> This is safe because this function is called on host controlled page table and
> non-present/non-MMIO sptes never use bits 1..31. For the EPT case, this
> ensures that cases where only the execute bit is set is marked valid.
> 
> Signed-off-by: Bandan Das <bsd@redhat.com>
> ---
>  arch/x86/kvm/mmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index
> def97b3..87b62dc 100644
> --- a/arch/x86/kvm/mmu.c
> +++ b/arch/x86/kvm/mmu.c
> @@ -304,7 +304,7 @@ static int is_nx(struct kvm_vcpu *vcpu)
> 
>  static int is_shadow_present_pte(u64 pte)  {
> -	return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
> +	return (pte & 0xFFFFFFFFull) && !is_mmio_spte(pte);
>  }
> 
>  static int is_large_pte(u64 pte)
> --
> 2.5.5
> 
> --
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#1474469

On 01/09/2016 16:20, Li, Liang Z wrote:
> Intel SDM doesn't describe whether the A bit will be set or not when
> CPU accesses  a no present EPT page table entry

Bits in a non-present page table entry are entirely for use by the OS.
The processor will never touch it.  This includes both P=0 in non-EPT
page tables and XWR=000 in EPT page tables.

Paolo

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