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[RFC 01/55] arm64: Add missing TCR hw defines

Started byJintack Lim <jintack@cs.columbia.edu>
First post2017-01-09 07:40 +0100
Last post2017-01-09 07:40 +0100
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  [RFC 01/55] arm64: Add missing TCR hw defines Jintack Lim <jintack@cs.columbia.edu> - 2017-01-09 07:40 +0100

#1554072 — [RFC 01/55] arm64: Add missing TCR hw defines

FromJintack Lim <jintack@cs.columbia.edu>
Date2017-01-09 07:40 +0100
Subject[RFC 01/55] arm64: Add missing TCR hw defines
Message-ID<sXBMB-zF-5@gated-at.bofh.it>
From: Christoffer Dall <christoffer.dall@linaro.org>

Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
---
 arch/arm64/include/asm/pgtable-hwdef.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index eb0c2bd..d26cab7 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -272,9 +272,15 @@
 #define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
 #define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
 
+#define TCR_IPS_SHIFT		32
+#define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
+
 #define TCR_ASID16		(UL(1) << 36)
 #define TCR_TBI0		(UL(1) << 37)
 #define TCR_HA			(UL(1) << 39)
 #define TCR_HD			(UL(1) << 40)
 
+#define TCR_EPD1		(UL(1) << 23)
+#define TCR_EPD0		(UL(1) << 7)
+
 #endif
-- 
1.9.1

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