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[PATCH V2 0/5] PCI: exynos: use the PHY generic framework

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  [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-04 13:40 +0100
    [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-04 13:40 +0100
      Re: [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node  for pcie Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-04 19:10 +0100
        Re: [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie "Jingoo Han" <jingoohan1@gmail.com> - 2017-01-04 19:10 +0100
        Re: [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for  pcie Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-05 03:30 +0100
      Re: [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for  pcie "pankaj.dubey" <pankaj.dubey@samsung.com> - 2017-01-05 10:10 +0100
    [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-04 13:40 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-04 19:00 +0100
        Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-05 03:30 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy "Jingoo Han" <jingoohan1@gmail.com> - 2017-01-04 21:30 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy "pankaj.dubey" <pankaj.dubey@samsung.com> - 2017-01-05 07:20 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Alim Akhtar <alim.akhtar@samsung.com> - 2017-01-09 14:40 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2017-01-10 07:10 +0100
        Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-10 07:20 +0100
      Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-16 09:40 +0100
        Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe  phy Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-16 12:10 +0100
    [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy  binding Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-04 13:40 +0100
      Re: [PATCH V2 1/5] Documetation: samsung-phy: add the  exynos-pcie-phy binding Rob Herring <robh@kernel.org> - 2017-01-04 16:20 +0100
      Re: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy  binding Alim Akhtar <alim.akhtar@samsung.com> - 2017-01-05 05:30 +0100
        Re: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy  binding "pankaj.dubey" <pankaj.dubey@samsung.com> - 2017-01-05 07:10 +0100
    [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-04 13:40 +0100
      Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic  framework Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-04 19:00 +0100
        Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Jaehoon Chung <jh80.chung@samsung.com> - 2017-01-05 03:40 +0100
      Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework "Jingoo Han" <jingoohan1@gmail.com> - 2017-01-04 21:00 +0100
      Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework "pankaj.dubey" <pankaj.dubey@samsung.com> - 2017-01-05 10:10 +0100
      Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Alim Akhtar <alim.akhtar@samsung.com> - 2017-01-09 14:50 +0100
    Re: [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Bjorn Helgaas <helgaas@kernel.org> - 2017-01-12 22:10 +0100

Page 2 of 2 — ← Prev page 1 [2]

#1550736 — [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

This patch is for using PHY generic framework.
To maintain backward compatibility, check whether phy is supported or
not with 'using_phy'.

And if someone use the old dt-file, display the "deprecated" message.
But it's still working fine with it.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
Changelog on V2:
- This patch is split from previous PATCH[1/4]
- Maintain the backward compatibility
- Adds 'using_phy' for cheching whether phy framework is used or not
- Adds 'DEPRECATED' message for old dt-binding way

 drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
 1 file changed, 50 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index feed0fd..34f2eed 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -21,6 +21,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/phy/phy.h>
 #include <linux/resource.h>
 #include <linux/signal.h>
 #include <linux/types.h>
@@ -110,6 +111,10 @@ struct exynos_pcie {
 	struct exynos_pcie_clk_res	*clk_res;
 	const struct exynos_pcie_ops	*ops;
 	int				reset_gpio;
+
+	/* For Generic PHY Framework */
+	bool				using_phy;
+	struct phy			*phy;
 };
 
 struct exynos_pcie_ops {
@@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
 	if (IS_ERR(ep->mem_res->elbi_base))
 		return PTR_ERR(ep->mem_res->elbi_base);
 
+	/* If using the PHY framework, doesn't need to get other resource */
+	if (ep->using_phy)
+		return 0;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(ep->mem_res->phy_base))
@@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
 	}
 
 	exynos_pcie_assert_core_reset(exynos_pcie);
-	exynos_pcie_assert_phy_reset(exynos_pcie);
-	exynos_pcie_deassert_phy_reset(exynos_pcie);
-	exynos_pcie_power_on_phy(exynos_pcie);
-	exynos_pcie_init_phy(exynos_pcie);
-
-	/* pulse for common reset */
-	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
-				PCIE_PHY_COMMON_RESET);
-	udelay(500);
-	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
-				PCIE_PHY_COMMON_RESET);
+
+	if (exynos_pcie->using_phy) {
+		phy_reset(exynos_pcie->phy);
+
+		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
+				PCIE_PWR_RESET);
+
+		phy_power_on(exynos_pcie->phy);
+		phy_init(exynos_pcie->phy);
+	} else {
+		exynos_pcie_assert_phy_reset(exynos_pcie);
+		exynos_pcie_deassert_phy_reset(exynos_pcie);
+		exynos_pcie_power_on_phy(exynos_pcie);
+		exynos_pcie_init_phy(exynos_pcie);
+
+		/* pulse for common reset */
+		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
+					PCIE_PHY_COMMON_RESET);
+		udelay(500);
+		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
+					PCIE_PHY_COMMON_RESET);
+	}
 
 	exynos_pcie_deassert_core_reset(exynos_pcie);
 	dw_pcie_setup_rc(pp);
@@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
 	if (!dw_pcie_wait_for_link(pp))
 		return 0;
 
+	if (exynos_pcie->using_phy) {
+		phy_power_off(exynos_pcie->phy);
+		return -ETIMEDOUT;
+	}
+
 	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
 				PCIE_PHY_PLL_LOCKED) == 0) {
 		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
@@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 
 	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 
+	/* Assume that controller doesn't use the PHY framework */
+	exynos_pcie->using_phy = false;
+
+	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
+	if (IS_ERR(exynos_pcie->phy)) {
+		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
+			return PTR_ERR(exynos_pcie->phy);
+		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
+	} else
+		exynos_pcie->using_phy = true;
+
 	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
 		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
 		if (ret)
@@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	return 0;
 
 fail_probe:
+	if (exynos_pcie->using_phy)
+		phy_exit(exynos_pcie->phy);
+
 	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
 		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
 	return ret;
-- 
2.10.2

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#1551046 — Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

On Wed, Jan 04, 2017 at 09:34:34PM +0900, Jaehoon Chung wrote:
> This patch is for using PHY generic framework.
> To maintain backward compatibility, check whether phy is supported or
> not with 'using_phy'.
> 
> And if someone use the old dt-file, display the "deprecated" message.
> But it's still working fine with it.

This needs improvements. How about:
"Switch the pci-exynos driver to generic PHY framework. At the same time
backward compatibility is preserved: warning will be printed for old
DTB.

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
> 
>  drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
>  1 file changed, 50 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index feed0fd..34f2eed 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
>  #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
>  	struct exynos_pcie_clk_res	*clk_res;
>  	const struct exynos_pcie_ops	*ops;
>  	int				reset_gpio;
> +
> +	/* For Generic PHY Framework */
> +	bool				using_phy;
> +	struct phy			*phy;
>  };
>  
>  struct exynos_pcie_ops {
> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>  	if (IS_ERR(ep->mem_res->elbi_base))
>  		return PTR_ERR(ep->mem_res->elbi_base);
>  
> +	/* If using the PHY framework, doesn't need to get other resource */
> +	if (ep->using_phy)
> +		return 0;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>  	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(ep->mem_res->phy_base))
> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>  	}
>  
>  	exynos_pcie_assert_core_reset(exynos_pcie);
> -	exynos_pcie_assert_phy_reset(exynos_pcie);
> -	exynos_pcie_deassert_phy_reset(exynos_pcie);
> -	exynos_pcie_power_on_phy(exynos_pcie);
> -	exynos_pcie_init_phy(exynos_pcie);
> -
> -	/* pulse for common reset */
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> -				PCIE_PHY_COMMON_RESET);
> -	udelay(500);
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> -				PCIE_PHY_COMMON_RESET);
> +
> +	if (exynos_pcie->using_phy) {
> +		phy_reset(exynos_pcie->phy);
> +
> +		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
> +				PCIE_PWR_RESET);
> +
> +		phy_power_on(exynos_pcie->phy);
> +		phy_init(exynos_pcie->phy);
> +	} else {
> +		exynos_pcie_assert_phy_reset(exynos_pcie);
> +		exynos_pcie_deassert_phy_reset(exynos_pcie);
> +		exynos_pcie_power_on_phy(exynos_pcie);
> +		exynos_pcie_init_phy(exynos_pcie);
> +
> +		/* pulse for common reset */
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> +					PCIE_PHY_COMMON_RESET);
> +		udelay(500);
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> +					PCIE_PHY_COMMON_RESET);
> +	}
>  
>  	exynos_pcie_deassert_core_reset(exynos_pcie);
>  	dw_pcie_setup_rc(pp);
> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>  	if (!dw_pcie_wait_for_link(pp))
>  		return 0;
>  
> +	if (exynos_pcie->using_phy) {
> +		phy_power_off(exynos_pcie->phy);
> +		return -ETIMEDOUT;
> +	}
> +
>  	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>  				PCIE_PHY_PLL_LOCKED) == 0) {
>  		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  
>  	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>  
> +	/* Assume that controller doesn't use the PHY framework */
> +	exynos_pcie->using_phy = false;
> +
> +	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
> +	if (IS_ERR(exynos_pcie->phy)) {
> +		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
> +			return PTR_ERR(exynos_pcie->phy);
> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
> +	} else
> +		exynos_pcie->using_phy = true;
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>  		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>  		if (ret)
> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  	return 0;
>  
>  fail_probe:
> +	if (exynos_pcie->using_phy)
> +		phy_exit(exynos_pcie->phy);
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>  		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>  	return ret;
> -- 
> 2.10.2
> 

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#1551583 — Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

On 01/05/2017 02:50 AM, Krzysztof Kozlowski wrote:
> On Wed, Jan 04, 2017 at 09:34:34PM +0900, Jaehoon Chung wrote:
>> This patch is for using PHY generic framework.
>> To maintain backward compatibility, check whether phy is supported or
>> not with 'using_phy'.
>>
>> And if someone use the old dt-file, display the "deprecated" message.
>> But it's still working fine with it.
> 
> This needs improvements. How about:
> "Switch the pci-exynos driver to generic PHY framework. At the same time
> backward compatibility is preserved: warning will be printed for old
> DTB.

Thanks for comments. Will describe the commit-msg in more detail.

Best Regards,
Jaehoon Chung

> 
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> Best regards,
> Krzysztof
> 
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> Changelog on V2:
>> - This patch is split from previous PATCH[1/4]
>> - Maintain the backward compatibility
>> - Adds 'using_phy' for cheching whether phy framework is used or not
>> - Adds 'DEPRECATED' message for old dt-binding way
>>
>>  drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
>>  1 file changed, 50 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>> index feed0fd..34f2eed 100644
>> --- a/drivers/pci/host/pci-exynos.c
>> +++ b/drivers/pci/host/pci-exynos.c
>> @@ -21,6 +21,7 @@
>>  #include <linux/of_gpio.h>
>>  #include <linux/pci.h>
>>  #include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>>  #include <linux/resource.h>
>>  #include <linux/signal.h>
>>  #include <linux/types.h>
>> @@ -110,6 +111,10 @@ struct exynos_pcie {
>>  	struct exynos_pcie_clk_res	*clk_res;
>>  	const struct exynos_pcie_ops	*ops;
>>  	int				reset_gpio;
>> +
>> +	/* For Generic PHY Framework */
>> +	bool				using_phy;
>> +	struct phy			*phy;
>>  };
>>  
>>  struct exynos_pcie_ops {
>> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>>  	if (IS_ERR(ep->mem_res->elbi_base))
>>  		return PTR_ERR(ep->mem_res->elbi_base);
>>  
>> +	/* If using the PHY framework, doesn't need to get other resource */
>> +	if (ep->using_phy)
>> +		return 0;
>> +
>>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>  	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>>  	if (IS_ERR(ep->mem_res->phy_base))
>> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>>  	}
>>  
>>  	exynos_pcie_assert_core_reset(exynos_pcie);
>> -	exynos_pcie_assert_phy_reset(exynos_pcie);
>> -	exynos_pcie_deassert_phy_reset(exynos_pcie);
>> -	exynos_pcie_power_on_phy(exynos_pcie);
>> -	exynos_pcie_init_phy(exynos_pcie);
>> -
>> -	/* pulse for common reset */
>> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>> -				PCIE_PHY_COMMON_RESET);
>> -	udelay(500);
>> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>> -				PCIE_PHY_COMMON_RESET);
>> +
>> +	if (exynos_pcie->using_phy) {
>> +		phy_reset(exynos_pcie->phy);
>> +
>> +		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
>> +				PCIE_PWR_RESET);
>> +
>> +		phy_power_on(exynos_pcie->phy);
>> +		phy_init(exynos_pcie->phy);
>> +	} else {
>> +		exynos_pcie_assert_phy_reset(exynos_pcie);
>> +		exynos_pcie_deassert_phy_reset(exynos_pcie);
>> +		exynos_pcie_power_on_phy(exynos_pcie);
>> +		exynos_pcie_init_phy(exynos_pcie);
>> +
>> +		/* pulse for common reset */
>> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
>> +					PCIE_PHY_COMMON_RESET);
>> +		udelay(500);
>> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
>> +					PCIE_PHY_COMMON_RESET);
>> +	}
>>  
>>  	exynos_pcie_deassert_core_reset(exynos_pcie);
>>  	dw_pcie_setup_rc(pp);
>> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>>  	if (!dw_pcie_wait_for_link(pp))
>>  		return 0;
>>  
>> +	if (exynos_pcie->using_phy) {
>> +		phy_power_off(exynos_pcie->phy);
>> +		return -ETIMEDOUT;
>> +	}
>> +
>>  	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>>  				PCIE_PHY_PLL_LOCKED) == 0) {
>>  		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
>> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>  
>>  	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>>  
>> +	/* Assume that controller doesn't use the PHY framework */
>> +	exynos_pcie->using_phy = false;
>> +
>> +	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
>> +	if (IS_ERR(exynos_pcie->phy)) {
>> +		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
>> +			return PTR_ERR(exynos_pcie->phy);
>> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
>> +	} else
>> +		exynos_pcie->using_phy = true;
>> +
>>  	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>>  		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>>  		if (ret)
>> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>  	return 0;
>>  
>>  fail_probe:
>> +	if (exynos_pcie->using_phy)
>> +		phy_exit(exynos_pcie->phy);
>> +
>>  	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>>  		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>>  	return ret;
>> -- 
>> 2.10.2
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

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#1551144 — Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

On Wednesday, January 4, 2017 7:35 AM, Jaehoon Chung wrote:
> 
> This patch is for using PHY generic framework.
> To maintain backward compatibility, check whether phy is supported or
> not with 'using_phy'.
> 
> And if someone use the old dt-file, display the "deprecated" message.
> But it's still working fine with it.
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

It looks good!

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han


> ---
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
> 
>  drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++---
> -----
>  1 file changed, 50 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index feed0fd..34f2eed 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
>  #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
>  	struct exynos_pcie_clk_res	*clk_res;
>  	const struct exynos_pcie_ops	*ops;
>  	int				reset_gpio;
> +
> +	/* For Generic PHY Framework */
> +	bool				using_phy;
> +	struct phy			*phy;
>  };
> 
>  struct exynos_pcie_ops {
> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct
> platform_device *pdev,
>  	if (IS_ERR(ep->mem_res->elbi_base))
>  		return PTR_ERR(ep->mem_res->elbi_base);
> 
> +	/* If using the PHY framework, doesn't need to get other resource
> */
> +	if (ep->using_phy)
> +		return 0;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>  	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(ep->mem_res->phy_base))
> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct
> exynos_pcie *exynos_pcie)
>  	}
> 
>  	exynos_pcie_assert_core_reset(exynos_pcie);
> -	exynos_pcie_assert_phy_reset(exynos_pcie);
> -	exynos_pcie_deassert_phy_reset(exynos_pcie);
> -	exynos_pcie_power_on_phy(exynos_pcie);
> -	exynos_pcie_init_phy(exynos_pcie);
> -
> -	/* pulse for common reset */
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> -				PCIE_PHY_COMMON_RESET);
> -	udelay(500);
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> -				PCIE_PHY_COMMON_RESET);
> +
> +	if (exynos_pcie->using_phy) {
> +		phy_reset(exynos_pcie->phy);
> +
> +		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
> +				PCIE_PWR_RESET);
> +
> +		phy_power_on(exynos_pcie->phy);
> +		phy_init(exynos_pcie->phy);
> +	} else {
> +		exynos_pcie_assert_phy_reset(exynos_pcie);
> +		exynos_pcie_deassert_phy_reset(exynos_pcie);
> +		exynos_pcie_power_on_phy(exynos_pcie);
> +		exynos_pcie_init_phy(exynos_pcie);
> +
> +		/* pulse for common reset */
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> +					PCIE_PHY_COMMON_RESET);
> +		udelay(500);
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> +					PCIE_PHY_COMMON_RESET);
> +	}
> 
>  	exynos_pcie_deassert_core_reset(exynos_pcie);
>  	dw_pcie_setup_rc(pp);
> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct
> exynos_pcie *exynos_pcie)
>  	if (!dw_pcie_wait_for_link(pp))
>  		return 0;
> 
> +	if (exynos_pcie->using_phy) {
> +		phy_power_off(exynos_pcie->phy);
> +		return -ETIMEDOUT;
> +	}
> +
>  	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>  				PCIE_PHY_PLL_LOCKED) == 0) {
>  		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct
> platform_device *pdev)
> 
>  	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> 
> +	/* Assume that controller doesn't use the PHY framework */
> +	exynos_pcie->using_phy = false;
> +
> +	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
> +	if (IS_ERR(exynos_pcie->phy)) {
> +		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
> +			return PTR_ERR(exynos_pcie->phy);
> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-
> exynos was deprecated!!\n");
> +	} else
> +		exynos_pcie->using_phy = true;
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>  		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>  		if (ret)
> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct
> platform_device *pdev)
>  	return 0;
> 
>  fail_probe:
> +	if (exynos_pcie->using_phy)
> +		phy_exit(exynos_pcie->phy);
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>  		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>  	return ret;
> --
> 2.10.2

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#1551787 — Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

Hi Jaehoon,

On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch is for using PHY generic framework.
> To maintain backward compatibility, check whether phy is supported or
> not with 'using_phy'.
> 
> And if someone use the old dt-file, display the "deprecated" message.
> But it's still working fine with it.
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
> 

Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>

Thanks,
Pankaj Dubey

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#1554325 — Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework

Hi Jaehoon,

On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
> This patch is for using PHY generic framework.
> To maintain backward compatibility, check whether phy is supported or
> not with 'using_phy'.
>
> And if someone use the old dt-file, display the "deprecated" message.
> But it's still working fine with it.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>


> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
>
>  drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
>  1 file changed, 50 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index feed0fd..34f2eed 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
>  #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
>  	struct exynos_pcie_clk_res	*clk_res;
>  	const struct exynos_pcie_ops	*ops;
>  	int				reset_gpio;
> +
> +	/* For Generic PHY Framework */
> +	bool				using_phy;
> +	struct phy			*phy;
>  };
>
>  struct exynos_pcie_ops {
> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>  	if (IS_ERR(ep->mem_res->elbi_base))
>  		return PTR_ERR(ep->mem_res->elbi_base);
>
> +	/* If using the PHY framework, doesn't need to get other resource */
> +	if (ep->using_phy)
> +		return 0;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>  	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(ep->mem_res->phy_base))
> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>  	}
>
>  	exynos_pcie_assert_core_reset(exynos_pcie);
> -	exynos_pcie_assert_phy_reset(exynos_pcie);
> -	exynos_pcie_deassert_phy_reset(exynos_pcie);
> -	exynos_pcie_power_on_phy(exynos_pcie);
> -	exynos_pcie_init_phy(exynos_pcie);
> -
> -	/* pulse for common reset */
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> -				PCIE_PHY_COMMON_RESET);
> -	udelay(500);
> -	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> -				PCIE_PHY_COMMON_RESET);
> +
> +	if (exynos_pcie->using_phy) {
> +		phy_reset(exynos_pcie->phy);
> +
> +		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
> +				PCIE_PWR_RESET);
> +
> +		phy_power_on(exynos_pcie->phy);
> +		phy_init(exynos_pcie->phy);
> +	} else {
> +		exynos_pcie_assert_phy_reset(exynos_pcie);
> +		exynos_pcie_deassert_phy_reset(exynos_pcie);
> +		exynos_pcie_power_on_phy(exynos_pcie);
> +		exynos_pcie_init_phy(exynos_pcie);
> +
> +		/* pulse for common reset */
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> +					PCIE_PHY_COMMON_RESET);
> +		udelay(500);
> +		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> +					PCIE_PHY_COMMON_RESET);
> +	}
>
>  	exynos_pcie_deassert_core_reset(exynos_pcie);
>  	dw_pcie_setup_rc(pp);
> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
>  	if (!dw_pcie_wait_for_link(pp))
>  		return 0;
>
> +	if (exynos_pcie->using_phy) {
> +		phy_power_off(exynos_pcie->phy);
> +		return -ETIMEDOUT;
> +	}
> +
>  	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
>  				PCIE_PHY_PLL_LOCKED) == 0) {
>  		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>
>  	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>
> +	/* Assume that controller doesn't use the PHY framework */
> +	exynos_pcie->using_phy = false;
> +
> +	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
> +	if (IS_ERR(exynos_pcie->phy)) {
> +		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
> +			return PTR_ERR(exynos_pcie->phy);
> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
> +	} else
> +		exynos_pcie->using_phy = true;
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
>  		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
>  		if (ret)
> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  	return 0;
>
>  fail_probe:
> +	if (exynos_pcie->using_phy)
> +		phy_exit(exynos_pcie->phy);
> +
>  	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
>  		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
>  	return ret;
>

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#1557811

On Wed, Jan 04, 2017 at 09:34:30PM +0900, Jaehoon Chung wrote:
> This patchset is for using PHY generic framework.
> Current pci-exyons doesn't use the phy framework since there haven't been on
> PHY subsystem when Exynos5440 had been upstremed.
> The not using PHY framework make the difficult to upstream the other
> Exynos SoCs.
> 
> Before upstreaming the other Exynos SoCs, it's goal what make to use the PHY framework.
> 
> This patchset has the below modifications:
> 1) Introduces the phy-pcie-pcie
> 2) Handles Phy controller from PHY framework for pci-exynos
> 3) Modifies the dt-binding of pci-exynos
> - The using the getting configuration space address from ranges is old.
> - Deprecated the old way.
> 4) Maintains the backward compatibility
> 
> NOTE: These patches based on below patches:
> 	http://patchwork.ozlabs.org/patch/706998/
> 	http://patchwork.ozlabs.org/patch/706997/
> 	http://patchwork.ozlabs.org/patch/706995/
> 	http://patchwork.ozlabs.org/patch/706994/
> 	http://patchwork.ozlabs.org/patch/703530/
> 	- This patch should be conflicted. so fixes the manually.
> 	http://patchwork.ozlabs.org/patch/708414/
> 
> Changelog on V2:
> - Keep current codes for backward compatibility
> - Fixes some typos
> - Split the patches for removing the dependency
> - Removes the unnecessary codes
> - Change the patch's sequence
> - Based on latest PCI git repository.(next branch)
> 
> Jaehoon Chung (5):
>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>   Documetation: binding: modify the exynos5440 pcie binding
>   PCI: exynos: support the using PHY generic framework
>   ARM: dts: exynos5440: support the phy-pcie node for pcie

Since you're going to update this, please fix the typos in the above,
e.g., s/Documetation/Documentation/.

In addition, please run "git log --oneline" on the files you're
changing and make your subject lines consistent in style and
capitalization with previous ones, e.g., use "PCIe" consistently.
"Modify the ..." contains no useful information.  Of course a patch
modifies something -- please tell us what the modification is useful
for.

>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>  arch/arm/boot/dts/exynos5440.dtsi                  |  34 ++-
>  drivers/pci/host/pci-exynos.c                      |  61 ++++-
>  drivers/phy/Kconfig                                |   9 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-exynos-pcie.c                      | 280 +++++++++++++++++++++
>  7 files changed, 408 insertions(+), 23 deletions(-)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 
> -- 
> 2.10.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

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