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| Started by | Neil Armstrong <narmstrong@baylibre.com> |
|---|---|
| First post | 2017-01-04 11:00 +0100 |
| Last post | 2017-01-04 11:00 +0100 |
| Articles | 2 — 1 participant |
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[PATCH 0/2] drm/meson: Fix CVBS initialization Neil Armstrong <narmstrong@baylibre.com> - 2017-01-04 11:00 +0100
[PATCH 1/2] drm/meson: Fix CVBS initialization when HDMI is configured by bootloader Neil Armstrong <narmstrong@baylibre.com> - 2017-01-04 11:00 +0100
| From | Neil Armstrong <narmstrong@baylibre.com> |
|---|---|
| Date | 2017-01-04 11:00 +0100 |
| Subject | [PATCH 0/2] drm/meson: Fix CVBS initialization |
| Message-ID | <sVQwp-2U6-11@gated-at.bofh.it> |
This serie fixes the CVBS initialization when HDMI is already configured
by the bootloader and fixes the CVBS vdac disable register values.
Neil Armstrong (2):
drm/meson: Fix CVBS initialization when HDMI is configured by
bootloader
drm/meson: Fix CVBS VDAC disable
drivers/gpu/drm/meson/meson_venc.c | 19 +++++++++++++++++++
drivers/gpu/drm/meson/meson_venc_cvbs.c | 2 +-
2 files changed, 20 insertions(+), 1 deletion(-)
--
1.9.1
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| From | Neil Armstrong <narmstrong@baylibre.com> |
|---|---|
| Date | 2017-01-04 11:00 +0100 |
| Subject | [PATCH 1/2] drm/meson: Fix CVBS initialization when HDMI is configured by bootloader |
| Message-ID | <sVQwp-2U6-13@gated-at.bofh.it> |
| In reply to | #1550595 |
When the HDMI output is configured by the bootloader, there is mismatch is the
pipeline configuration and the Vsync interrupt fails to trigger.
This commit disables the HDMI blocks in the probe phase.
Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_venc.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index d836b22..f7c87017 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -38,6 +38,11 @@
* - TV Panel encoding via ENCT
*/
+/* HHI Registers */
+#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
+#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
+#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
+
struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
.mode_tag = MESON_VENC_MODE_CVBS_PAL,
.hso_begin = 3,
@@ -242,6 +247,20 @@ void meson_venc_disable_vsync(struct meson_drm *priv)
void meson_venc_init(struct meson_drm *priv)
{
+ /* Disable CVBS VDAC */
+ regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
+ regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
+
+ /* Power Down Dacs */
+ writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
+
+ /* Disable HDMI PHY */
+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
+
+ /* Disable HDMI */
+ writel_bits_relaxed(0x3, 0,
+ priv->io_base + _REG(VPU_HDMI_SETTING));
+
/* Disable all encoders */
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
--
1.9.1
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