Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1544362 > unrolled thread
| Started by | Jaehoon Chung <jh80.chung@samsung.com> |
|---|---|
| First post | 2016-12-19 09:20 +0100 |
| Last post | 2016-12-24 12:00 +0100 |
| Articles | 3 — 3 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
[PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting Jaehoon Chung <jh80.chung@samsung.com> - 2016-12-19 09:20 +0100
Re: [3/4] PCI: exynos: Use the bitops API to operate the bit shifting "pankaj.dubey" <pankaj.dubey@samsung.com> - 2016-12-21 07:30 +0100
Re: [PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting Krzysztof Kozlowski <krzk@kernel.org> - 2016-12-24 12:00 +0100
| From | Jaehoon Chung <jh80.chung@samsung.com> |
|---|---|
| Date | 2016-12-19 09:20 +0100 |
| Subject | [PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting |
| Message-ID | <sQ1kS-5f4-19@gated-at.bofh.it> |
Just use the bitops api to operate the bit.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index d64e8f1..d705bfe 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -40,19 +40,19 @@ struct exynos_pcie {
/* PCIe ELBI registers */
#define PCIE_IRQ_PULSE 0x000
-#define IRQ_INTA_ASSERT (0x1 << 0)
-#define IRQ_INTB_ASSERT (0x1 << 2)
-#define IRQ_INTC_ASSERT (0x1 << 4)
-#define IRQ_INTD_ASSERT (0x1 << 6)
+#define IRQ_INTA_ASSERT BIT(0)
+#define IRQ_INTB_ASSERT BIT(2)
+#define IRQ_INTC_ASSERT BIT(4)
+#define IRQ_INTD_ASSERT BIT(6)
#define PCIE_IRQ_LEVEL 0x004
#define PCIE_IRQ_SPECIAL 0x008
#define PCIE_IRQ_EN_PULSE 0x00c
#define PCIE_IRQ_EN_LEVEL 0x010
-#define IRQ_MSI_ENABLE (0x1 << 2)
+#define IRQ_MSI_ENABLE BIT(2)
#define PCIE_IRQ_EN_SPECIAL 0x014
#define PCIE_PWR_RESET 0x018
#define PCIE_CORE_RESET 0x01c
-#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
+#define PCIE_CORE_RESET_ENABLE BIT(0)
#define PCIE_STICKY_RESET 0x020
#define PCIE_NONSTICKY_RESET 0x024
#define PCIE_APP_INIT_RESET 0x028
@@ -61,7 +61,7 @@ struct exynos_pcie {
#define PCIE_ELBI_LTSSM_ENABLE 0x1
#define PCIE_ELBI_SLV_AWMISC 0x11c
#define PCIE_ELBI_SLV_ARMISC 0x120
-#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
+#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
/* PCIe Purple registers */
#define PCIE_PHY_GLOBAL_RESET 0x000
@@ -79,27 +79,27 @@ struct exynos_pcie {
#define PCIE_PHY_DCC_FEEDBACK 0x014
#define PCIE_PHY_PLL_DIV_1 0x05c
#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3)
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
#define PCIE_PHY_TRSV0_EMP_LVL 0x084
#define PCIE_PHY_TRSV0_DRV_LVL 0x088
#define PCIE_PHY_TRSV0_RXCDR 0x0ac
#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
#define PCIE_PHY_TRSV0_LVCC 0x0dc
#define PCIE_PHY_TRSV1_EMP_LVL 0x144
#define PCIE_PHY_TRSV1_RXCDR 0x16c
#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
#define PCIE_PHY_TRSV1_LVCC 0x19c
#define PCIE_PHY_TRSV2_EMP_LVL 0x204
#define PCIE_PHY_TRSV2_RXCDR 0x22c
#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
#define PCIE_PHY_TRSV2_LVCC 0x25c
#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
#define PCIE_PHY_TRSV3_RXCDR 0x2ec
#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
--
2.10.2
[toc] | [next] | [standalone]
| From | "pankaj.dubey" <pankaj.dubey@samsung.com> |
|---|---|
| Date | 2016-12-21 07:30 +0100 |
| Subject | Re: [3/4] PCI: exynos: Use the bitops API to operate the bit shifting |
| Message-ID | <sQIzv-8dI-7@gated-at.bofh.it> |
| In reply to | #1544362 |
Hi Jaehoon, On Monday 19 December 2016 01:47 PM, Jaehoon Chung wrote: > Just use the bitops api to operate the bit. > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > --- > drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) > Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-12-24 12:00 +0100 |
| Subject | Re: [PATCH 3/4] PCI: exynos: Use the bitops API to operate the bit shifting |
| Message-ID | <sRSds-5OB-17@gated-at.bofh.it> |
| In reply to | #1544362 |
On Mon, Dec 19, 2016 at 05:17:39PM +0900, Jaehoon Chung wrote: > Just use the bitops api to operate the bit. > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > --- > drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web