Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1540964 > unrolled thread
| Started by | Balbir Singh <bsingharora@gmail.com> |
|---|---|
| First post | 2016-12-13 11:20 +0100 |
| Last post | 2016-12-14 07:40 +0100 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro Balbir Singh <bsingharora@gmail.com> - 2016-12-13 11:20 +0100
Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro Gautham R Shenoy <ego@linux.vnet.ibm.com> - 2016-12-14 07:40 +0100
| From | Balbir Singh <bsingharora@gmail.com> |
|---|---|
| Date | 2016-12-13 11:20 +0100 |
| Subject | Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro |
| Message-ID | <sNSlH-8pl-11@gated-at.bofh.it> |
On 10/12/16 00:32, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > Currently all the low-power idle states are expected to wake up > at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ > that puts the CPU to an idle state and never returns. > > On ISA_300, when the ESL and EC bits in the PSSCR are zero, the > CPU is expected to wake up at the next instruction of the idle > instruction. > > This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the > no-return variant and reuses the name IDLE_STATE_ENTER_SEQ > for a variant that allows resuming operation at the instruction next > to the idle-instruction. > > Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/cpuidle.h | 5 ++++- > arch/powerpc/kernel/exceptions-64s.S | 6 +++--- > arch/powerpc/kernel/idle_book3s.S | 10 +++++----- > 3 files changed, 12 insertions(+), 9 deletions(-) > > diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h > index 3919332..0a3255b 100644 > --- a/arch/powerpc/include/asm/cpuidle.h > +++ b/arch/powerpc/include/asm/cpuidle.h > @@ -21,7 +21,7 @@ > > /* Idle state entry routines */ > #ifdef CONFIG_PPC_P7_NAP > -#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ > +#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ > /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ > std r0,0(r1); \ > ptesync; \ > @@ -29,6 +29,9 @@ > 1: cmpd cr0,r0,r0; \ > bne 1b; \ > IDLE_INST; \ > + Is the power saving magic sequence the same as before for power 9 as well? Balbir Singh
[toc] | [next] | [standalone]
| From | Gautham R Shenoy <ego@linux.vnet.ibm.com> |
|---|---|
| Date | 2016-12-14 07:40 +0100 |
| Message-ID | <sObol-35x-23@gated-at.bofh.it> |
| In reply to | #1540964 |
Hi Balbir, On Tue, Dec 13, 2016 at 09:13:26PM +1100, Balbir Singh wrote: > > > On 10/12/16 00:32, Gautham R. Shenoy wrote: > > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h > > index 3919332..0a3255b 100644 > > --- a/arch/powerpc/include/asm/cpuidle.h > > +++ b/arch/powerpc/include/asm/cpuidle.h > > @@ -21,7 +21,7 @@ > > > > /* Idle state entry routines */ > > #ifdef CONFIG_PPC_P7_NAP > > -#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ > > +#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ > > /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ > > std r0,0(r1); \ > > ptesync; \ > > @@ -29,6 +29,9 @@ > > 1: cmpd cr0,r0,r0; \ > > bne 1b; \ > > IDLE_INST; \ > > + > > Is the power saving magic sequence the same as before for power 9 > as well? Yes, this is the same magic sequence for POWER9. -- Thanks and Regards gautham.
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web