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Re: [PATCH v9] mtd: spi-nor: Add support for S3AN spi-nor devices

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  Re: [PATCH v9] mtd: spi-nor: Add support for S3AN spi-nor devices Marek Vasut <marek.vasut@gmail.com> - 2016-12-13 12:50 +0100
    Re: [PATCH v9] mtd: spi-nor: Add support for S3AN spi-nor devices Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> - 2016-12-13 18:50 +0100

#1541018 — Re: [PATCH v9] mtd: spi-nor: Add support for S3AN spi-nor devices

On 12/02/2016 12:31 PM, Ricardo Ribalda Delgado wrote:
> Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
> their configuration data and (optionally) some user data.
> 
> The protocol of this flash follows most of the spi-nor standard. With
> the following differences:
> 
> - Page size might not be a power of two.
> - The address calculation (default addressing mode).
> - The spi nor commands used.
> 
> Protocol is described on Xilinx User Guide UG333
> 
> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>

[...]

> +static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
> +{
> +	int ret;
> +	u8 val;
> +
> +	ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
> +	if (ret < 0) {
> +		dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
> +		return ret;
> +	}
> +
> +	nor->erase_opcode = SPINOR_OP_XSE;
> +	nor->program_opcode = SPINOR_OP_XPP;
> +	nor->read_opcode = SPINOR_OP_READ;
> +	nor->flags |= SNOR_F_NO_OP_CHIP_ERASE ;

NIT: You have an extra space before ;        ^

> +
> +	/*
> +	 * This flashes have a page size of 264 or 528 bytes (known as
> +	 * Default addressing mode). It can be changed to a more standard
> +	 * Power of two mode where the page size is 256/512. This comes
> +	 * with a price: there is 3% less of space, the data is corrupted
> +	 * and the page size cannot be changed back to default addressing
> +	 * mode.
> +	 *
> +	 * The current addressing mode can be read from the XRDSR register
> +	 * and should not be changed, because is a destructive operation.
> +	 */
> +	if (val & XSR_PAGESIZE) {
> +		/* Flash in Power of 2 mode */
> +		nor->page_size = (nor->page_size == 264) ? 256 : 512;
> +		nor->mtd.writebufsize = nor->page_size;
> +		nor->mtd.size = 8 * nor->page_size * info->n_sectors;
> +		nor->mtd.erasesize = 8 * nor->page_size;
> +	} else {
> +		/* Flash in Default addressing mode */
> +		nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
> +	}
> +
> +	return 0;
> +}

Looks great otherwise:
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>

-- 
Best regards,
Marek Vasut

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#1541353

Le 13/12/2016 à 08:53, Marek Vasut a écrit :
> On 12/02/2016 12:31 PM, Ricardo Ribalda Delgado wrote:
>> Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
>> their configuration data and (optionally) some user data.
>>
>> The protocol of this flash follows most of the spi-nor standard. With
>> the following differences:
>>
>> - Page size might not be a power of two.
>> - The address calculation (default addressing mode).
>> - The spi nor commands used.
>>
>> Protocol is described on Xilinx User Guide UG333
>>
>> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
>> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
>> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
>> Cc: Brian Norris <computersforpeace@gmail.com>
>> Cc: Marek Vasut <marek.vasut@gmail.com>
> 
> [...]
> 
>> +static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
>> +{
>> +	int ret;
>> +	u8 val;
>> +
>> +	ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
>> +	if (ret < 0) {
>> +		dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
>> +		return ret;
>> +	}
>> +
>> +	nor->erase_opcode = SPINOR_OP_XSE;
>> +	nor->program_opcode = SPINOR_OP_XPP;
>> +	nor->read_opcode = SPINOR_OP_READ;
>> +	nor->flags |= SNOR_F_NO_OP_CHIP_ERASE ;
> 
> NIT: You have an extra space before ;        ^
> 
>> +
>> +	/*
>> +	 * This flashes have a page size of 264 or 528 bytes (known as
>> +	 * Default addressing mode). It can be changed to a more standard
>> +	 * Power of two mode where the page size is 256/512. This comes
>> +	 * with a price: there is 3% less of space, the data is corrupted
>> +	 * and the page size cannot be changed back to default addressing
>> +	 * mode.
>> +	 *
>> +	 * The current addressing mode can be read from the XRDSR register
>> +	 * and should not be changed, because is a destructive operation.
>> +	 */
>> +	if (val & XSR_PAGESIZE) {
>> +		/* Flash in Power of 2 mode */
>> +		nor->page_size = (nor->page_size == 264) ? 256 : 512;
>> +		nor->mtd.writebufsize = nor->page_size;
>> +		nor->mtd.size = 8 * nor->page_size * info->n_sectors;
>> +		nor->mtd.erasesize = 8 * nor->page_size;
>> +	} else {
>> +		/* Flash in Default addressing mode */
>> +		nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
>> +	}
>> +
>> +	return 0;
>> +}
> 
> Looks great otherwise:
> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
> 
Applied to git://github.com/spi-nor/linux.git

I've removed the additional SPACE before ';' as reported by Marek.

Thanks!

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