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Re: [GIT pull] x86/cache: Updates for 4.10

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  Re: [GIT pull] x86/cache: Updates for 4.10 Linus Torvalds <torvalds@linux-foundation.org> - 2016-12-13 05:30 +0100
    Re: [GIT pull] x86/cache: Updates for 4.10 Peter Zijlstra <peterz@infradead.org> - 2016-12-13 09:10 +0100
    Re: [GIT pull] x86/cache: Updates for 4.10 Thomas Gleixner <tglx@linutronix.de> - 2016-12-13 10:10 +0100
      Re: [GIT pull] x86/cache: Updates for 4.10 Tony Luck <tony.luck@gmail.com> - 2016-12-17 02:50 +0100

#1540841 — Re: [GIT pull] x86/cache: Updates for 4.10

On Mon, Dec 12, 2016 at 1:53 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
>
> This update provides the support for Intel Cache Allocation Technology, a
> cache partitioning mechanism.

Ugh, this is some funky stuff. And it's entirely x86-specific, with a
rather odd special filesystem interface.

It looks pretty self-contained (good), but it also looks majorly
strange. I will have to think about this. What are the main/expected
users?

                Linus

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#1540889

On Mon, Dec 12, 2016 at 08:26:50PM -0800, Linus Torvalds wrote:
> On Mon, Dec 12, 2016 at 1:53 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> >
> > This update provides the support for Intel Cache Allocation Technology, a
> > cache partitioning mechanism.
> 
> Ugh, this is some funky stuff. And it's entirely x86-specific, with a
> rather odd special filesystem interface.
> 
> It looks pretty self-contained (good), but it also looks majorly
> strange. I will have to think about this. What are the main/expected
> users?

From what I know its aimed at two groups of users:

Firstly the Virtual Machine usecase, where, by assigning cache masks to
individual VMs you avoid one highly active VM trashing the cache of
another.

Secondly the Real-Time usecase, where we can assign cache slices to
individual CPUs such that we can better isolate RT and !RT workloads
running on the same cache domain (socket).

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#1540915

On Mon, 12 Dec 2016, Linus Torvalds wrote:

> On Mon, Dec 12, 2016 at 1:53 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> >
> > This update provides the support for Intel Cache Allocation Technology, a
> > cache partitioning mechanism.

Sorry for being terse in the pull request.

> Ugh, this is some funky stuff. And it's entirely x86-specific, with a
> rather odd special filesystem interface.

Yes. The interface is odd, but the hardware interface of that CAT stuff is
odd as well.

We tried hard to come up with an abstraction, but that only allows rather
simple partitioning, but no way of sharing and dealing with the per package
nature of this mechanism.

In the end we decided to expose the allocation bitmaps directly so all
combinations of the hardware can be utilized.

There are two ways of associating a cache partition:

 - Task

   A task can be added to a resource group. It uses the cache partition
   associated to the group.

 - CPU
 
   All tasks which are not member of a resource group use the group to
   which the CPU they are running on is associated with.

   That allows for simple CPU based partitioning schemes.

> It looks pretty self-contained (good), but it also looks majorly
> strange. I will have to think about this. What are the main/expected
> users?

 - Virtualization so a VM can only trash only the associated part of the
   cash w/o disturbing others

 - Real-Time systems to seperate RT and general workloads. 

 - Latency sensitive enterprise workloads 

 - In theory this also can be used to protect against cache side channel
   attacks.

Thanks,

	tglx

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#1543908

On Tue, Dec 13, 2016 at 1:01 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Mon, 12 Dec 2016, Linus Torvalds wrote:
>
>> On Mon, Dec 12, 2016 at 1:53 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
>> Ugh, this is some funky stuff. And it's entirely x86-specific, with a
>> rather odd special filesystem interface.
>
> Yes. The interface is odd, but the hardware interface of that CAT stuff is
> odd as well.
>
> We tried hard to come up with an abstraction, but that only allows rather
> simple partitioning, but no way of sharing and dealing with the per package
> nature of this mechanism.
>
> In the end we decided to expose the allocation bitmaps directly so all
> combinations of the hardware can be utilized.

Note that there are going to be more resources that can be controlled
using the same mechanism (PQR_ASSOC.CLOSID indexes into an
array of resource specific MSRs that specify how much of the resource
is available to the current process). Next one should be along fairly soon.
Keep an eye on chapter 17 in volume 3 of the SDM.

The code changes for this next resource involve new validation functions
(the resource isn't a cache, and the MSRs for it aren't bitmasks). But I think
it extends nicely.

-Tony

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