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| Started by | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| First post | 2016-12-06 04:00 +0100 |
| Last post | 2016-12-08 13:10 +0100 |
| Articles | 4 — 3 participants |
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[PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Andrew Jeffery <andrew@aj.id.au> - 2016-12-06 04:00 +0100
Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Linus Walleij <linus.walleij@linaro.org> - 2016-12-07 16:20 +0100
Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Joel Stanley <joel@jms.id.au> - 2016-12-08 03:20 +0100
Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) Andrew Jeffery <andrew@aj.id.au> - 2016-12-08 13:10 +0100
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-12-06 04:00 +0100 |
| Subject | [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) |
| Message-ID | <sLe93-4u4-9@gated-at.bofh.it> |
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
on bits in both the System Control Unit and the LPC Host Controller.
The Aspeed LPC Host Controller is described as a child node of the
LPC host-range syscon device for arbitration of access by the host
controller and pinmux drivers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index a97131aba446..9de318ef72da 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -109,3 +109,25 @@ lpc: lpc@1e789000 {
};
};
+Host Node Children
+==================
+
+LPC Host Controller
+-------------------
+
+The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
+between the host and the baseboard management controller. The registers exist
+in the "host" portion of the Aspeed LPC controller, which must be the parent of
+the LPC host controller node.
+
+Required properties:
+- compatible: "aspeed,ast2500-lhc";
+- reg: contains offset/length value of the LHC memory
+ region.
+
+Example:
+
+lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+};
--
2.9.3
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-12-07 16:20 +0100 |
| Subject | Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) |
| Message-ID | <sLMaK-1Ll-27@gated-at.bofh.it> |
| In reply to | #1536619 |
On Tue, Dec 6, 2016 at 3:53 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon device for arbitration of access by the host > controller and pinmux drivers. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
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| From | Joel Stanley <joel@jms.id.au> |
|---|---|
| Date | 2016-12-08 03:20 +0100 |
| Subject | Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) |
| Message-ID | <sLWtr-8ph-13@gated-at.bofh.it> |
| In reply to | #1536619 |
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> on bits in both the System Control Unit and the LPC Host Controller.
>
> The Aspeed LPC Host Controller is described as a child node of the
> LPC host-range syscon device for arbitration of access by the host
> controller and pinmux drivers.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> index a97131aba446..9de318ef72da 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> @@ -109,3 +109,25 @@ lpc: lpc@1e789000 {
> };
> };
>
> +Host Node Children
> +==================
> +
> +LPC Host Controller
> +-------------------
> +
> +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> +between the host and the baseboard management controller. The registers exist
> +in the "host" portion of the Aspeed LPC controller, which must be the parent of
> +the LPC host controller node.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-lhc";
Can you remind me why this binding doesn't cover the ast2400?
Cheers,
Joel
> +- reg: contains offset/length value of the LHC memory
> + region.
> +
> +Example:
> +
> +lhc: lhc@20 {
> + compatible = "aspeed,ast2500-lhc";
> + reg = <0x20 0x24 0x48 0x8>;
> +};
> --
> 2.9.3
>
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-12-08 13:10 +0100 |
| Subject | Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) |
| Message-ID | <sM5Gq-5YO-47@gated-at.bofh.it> |
| In reply to | #1538270 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, 2016-12-08 at 12:42 +1030, Joel Stanley wrote:
> > On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> > on bits in both the System Control Unit and the LPC Host Controller.
> >
> > The Aspeed LPC Host Controller is described as a child node of the
> > LPC host-range syscon device for arbitration of access by the host
> > controller and pinmux drivers.
> >
> > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > index a97131aba446..9de318ef72da 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > > > @@ -109,3 +109,25 @@ lpc: lpc@1e789000 {
> > };
> > };
> >
> > +Host Node Children
> > +==================
> > +
> > +LPC Host Controller
> > +-------------------
> > +
> > +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> > +between the host and the baseboard management controller. The registers exist
> > +in the "host" portion of the Aspeed LPC controller, which must be the parent of
> > +the LPC host controller node.
> > +
> > +Required properties:
> > +- compatible: "aspeed,ast2500-lhc";
>
> Can you remind me why this binding doesn't cover the ast2400?
Partly that we haven't yet needed the LHC for the AST2400.
Mostly that I overlooked it.
If there are other problems with series I'll address this issue, but if
not we can add it when we need it down the track.
Andrew
>
> Cheers,
>
> Joel
>
> > +- reg: contains offset/length value of the LHC memory
> > + region.
> > +
> > +Example:
> > +
> > > > +lhc: lhc@20 {
> > + compatible = "aspeed,ast2500-lhc";
> > + reg = <0x20 0x24 0x48 0x8>;
> > +};
> > --
> > 2.9.3
> >
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