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Groups > linux.kernel > #1534789 > unrolled thread
| Started by | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| First post | 2016-12-02 11:20 +0100 |
| Last post | 2016-12-03 15:50 +0100 |
| Articles | 15 on this page of 35 — 5 participants |
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[PATCH v3 0/7] Add pwm and IIO timer drivers for stm32 Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
[PATCH v3 6/7] IIO: add STM32 timer trigger driver Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 6/7] IIO: add STM32 timer trigger driver Lee Jones <lee.jones@linaro.org> - 2016-12-02 15:00 +0100
[PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Lee Jones <lee.jones@linaro.org> - 2016-12-02 14:20 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Jonathan Cameron <jic23@kernel.org> - 2016-12-03 15:50 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Lee Jones <lee.jones@linaro.org> - 2016-12-05 10:20 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Alexandre Torgue <alexandre.torgue@st.com> - 2016-12-05 17:20 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Lee Jones <lee.jones@linaro.org> - 2016-12-06 10:50 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Alexandre Torgue <alexandre.torgue@st.com> - 2016-12-06 11:00 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Lee Jones <lee.jones@linaro.org> - 2016-12-06 14:00 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Alexandre Torgue <alexandre.torgue@st.com> - 2016-12-02 14:50 +0100
Re: [PATCH v3 7/7] ARM: dts: stm32: add stm32 general purpose timer driver in DT Jonathan Cameron <jic23@kernel.org> - 2016-12-03 15:50 +0100
[PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Lee Jones <lee.jones@linaro.org> - 2016-12-02 15:30 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 08:00 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Lee Jones <lee.jones@linaro.org> - 2016-12-05 09:40 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 12:00 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-05 12:10 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 12:30 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-05 13:20 +0100
Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 13:30 +0100
[PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver Lee Jones <lee.jones@linaro.org> - 2016-12-02 15:00 +0100
Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 15:30 +0100
Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver Jonathan Cameron <jic23@kernel.org> - 2016-12-03 15:50 +0100
[PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 08:30 +0100
Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm Lee Jones <lee.jones@linaro.org> - 2016-12-05 09:30 +0100
Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-05 12:10 +0100
Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm Thierry Reding <thierry.reding@gmail.com> - 2016-12-05 12:40 +0100
[PATCH v3 2/7] MFD: add stm32 general purpose timer driver Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 2/7] MFD: add stm32 general purpose timer driver Lee Jones <lee.jones@linaro.org> - 2016-12-02 15:30 +0100
[PATCH v3 1/7] MFD: add bindings for stm32 general purpose timer driver Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-12-02 11:20 +0100
Re: [PATCH v3 0/7] Add pwm and IIO timer drivers for stm32 Jonathan Cameron <jic23@kernel.org> - 2016-12-03 15:50 +0100
Page 2 of 2 — ← Prev page 1 [2]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-05 13:20 +0100 |
| Subject | Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings |
| Message-ID | <sL0ps-4tV-31@gated-at.bofh.it> |
| In reply to | #1536013 |
2016-12-05 12:23 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>: > On Mon, Dec 05, 2016 at 12:08:32PM +0100, Benjamin Gaignard wrote: >> 2016-12-05 7:53 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>: >> > On Fri, Dec 02, 2016 at 11:17:18AM +0100, Benjamin Gaignard wrote: >> >> Define bindings for pwm-stm32 >> >> >> >> version 2: >> >> - use parameters instead of compatible of handle the hardware configuration >> >> >> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> >> >> --- >> >> .../devicetree/bindings/pwm/pwm-stm32.txt | 38 ++++++++++++++++++++++ >> >> 1 file changed, 38 insertions(+) >> >> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt >> >> >> >> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt >> >> new file mode 100644 >> >> index 0000000..575b9fb >> >> --- /dev/null >> >> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt >> >> @@ -0,0 +1,38 @@ >> >> +STMicroelectronics PWM driver bindings for STM32 >> > >> > Technically this bindings describe devices, so "driver binding" is a >> > somewhat odd wording. Perhaps: >> > >> > STMicroelectronics STM32 General Purpose Timer PWM bindings >> > >> > ? >> done >> >> > >> >> + >> >> +Must be a sub-node of STM32 general purpose timer driver >> >> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt >> > >> > Again, "driver parent node" is odd. Perhaps: >> > >> > Must be a sub-node of an STM32 General Purpose Timer device tree >> > node. See ../mfd/stm32-general-purpose-timer.txt for details about >> > the parent node. >> > >> > ? >> >> done >> >> > >> >> +Required parameters: >> >> +- compatible: Must be "st,stm32-pwm" >> >> +- pinctrl-names: Set to "default". >> >> +- pinctrl-0: List of phandles pointing to pin configuration nodes >> >> + for PWM module. >> >> + For Pinctrl properties, please refer to [1]. >> > >> > Your indentation and capitalization are inconsistent. Also, please refer >> > to the pinctrl bindings by relative path and inline, rather than as a >> > footnote reference. >> >> OK >> >> > >> >> + >> >> +Optional parameters: >> >> +- st,breakinput: Set if the hardware have break input capabilities >> >> +- st,breakinput-polarity: Set break input polarity. Default is 0 >> >> + The value define the active polarity: >> >> + - 0 (active LOW) >> >> + - 1 (active HIGH) >> > >> > Could we fold these into a single property? If st,breakinput-polarity is >> > not present it could simply mean that there is no break input, and if it >> > is present you don't have to rely on a default. >> >> I need to know if I have to activate breakinput feature and on which level >> I will rewrite it like that: >> Optional parameters: >> - st,breakinput-polarity-high: Set if break input polarity is active >> on high level. >> - st,breakinput-polarity-high: Set if break input polarity is active >> on low level. > > How is that different from a single property: > > Optional properties: > - st,breakinput-polarity: If present, a break input is available > for the channel. In that case the property value denotes the > polarity of the break input: > - 0: active low > - 1: active high > > ? For break input feature I need two information: do I have to active it and if activated on which level. I have two solutions: - one parameter with a value (0 or 1) -> st,breakinput-polarity - two parameters without value -> st,breakinput-active-high and st,breakinput-active-low By default break input feature is disabled > >> > The pwm- prefix is rather redundant since the node is already named pwm. >> > Why not simply st,channels? Or simply channels, since it's not really >> > anything specific to this hardware. >> > >> > Come to think of it, might be worth having a discussion with our DT >> > gurus about what their stance is on using the # as prefix for numbers >> > (such as in #address-cells or #size-cells). This could be #channels to >> > mark it more explicitly as representing a count. >> > >> >> +- st,32bits-counter: Set if the hardware have a 32 bits counter >> >> +- st,complementary: Set if the hardware have complementary output channels >> > >> > "hardware has" and also maybe mention explicitly that this is a boolean >> > property. Otherwise people might be left wondering what it should be set >> > to. Or maybe word this differently to imply that it's boolean: >> > >> > - st,32bits-counter: if present, the hardware has a 32 bit counter >> > - st,complementary: if present, the hardware has a complementary >> > output channel >> >> I found a way to detect, at probe time, the number of channels, counter size, >> break input capability and complementary channels so I will remove >> "st,breakinput", "st,32bits-counter", "st,complementary" and "st,pwm-num-chan" >> parameters > > Oh hey, that's very neat. I suppose in that case my comment above about > the break input polarity is somewhat obsoleted. Still I think you won't > need two properties. Instead you can follow what other similar > properties have done: choose a default (often low-active) and have a > single optional property to override the default (often high-active). > > In your case: > > - st,breakinput-active-high: Some channels have a break input, > whose polarity will be active low by default. If this > property is present, the channel will be configured with an > active high polarity for the break input. > > Thierry -- Benjamin Gaignard Graphic Study Group Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
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| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-12-05 13:30 +0100 |
| Subject | Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings |
| Message-ID | <sL0z8-4xj-37@gated-at.bofh.it> |
| In reply to | #1536045 |
[Multipart message — attachments visible in raw view] — view raw
On Mon, Dec 05, 2016 at 01:12:25PM +0100, Benjamin Gaignard wrote: > 2016-12-05 12:23 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>: > > On Mon, Dec 05, 2016 at 12:08:32PM +0100, Benjamin Gaignard wrote: > >> 2016-12-05 7:53 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>: > >> > On Fri, Dec 02, 2016 at 11:17:18AM +0100, Benjamin Gaignard wrote: > >> >> Define bindings for pwm-stm32 > >> >> > >> >> version 2: > >> >> - use parameters instead of compatible of handle the hardware configuration > >> >> > >> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> > >> >> --- > >> >> .../devicetree/bindings/pwm/pwm-stm32.txt | 38 ++++++++++++++++++++++ > >> >> 1 file changed, 38 insertions(+) > >> >> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt > >> >> > >> >> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt > >> >> new file mode 100644 > >> >> index 0000000..575b9fb > >> >> --- /dev/null > >> >> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt > >> >> @@ -0,0 +1,38 @@ > >> >> +STMicroelectronics PWM driver bindings for STM32 > >> > > >> > Technically this bindings describe devices, so "driver binding" is a > >> > somewhat odd wording. Perhaps: > >> > > >> > STMicroelectronics STM32 General Purpose Timer PWM bindings > >> > > >> > ? > >> done > >> > >> > > >> >> + > >> >> +Must be a sub-node of STM32 general purpose timer driver > >> >> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt > >> > > >> > Again, "driver parent node" is odd. Perhaps: > >> > > >> > Must be a sub-node of an STM32 General Purpose Timer device tree > >> > node. See ../mfd/stm32-general-purpose-timer.txt for details about > >> > the parent node. > >> > > >> > ? > >> > >> done > >> > >> > > >> >> +Required parameters: > >> >> +- compatible: Must be "st,stm32-pwm" > >> >> +- pinctrl-names: Set to "default". > >> >> +- pinctrl-0: List of phandles pointing to pin configuration nodes > >> >> + for PWM module. > >> >> + For Pinctrl properties, please refer to [1]. > >> > > >> > Your indentation and capitalization are inconsistent. Also, please refer > >> > to the pinctrl bindings by relative path and inline, rather than as a > >> > footnote reference. > >> > >> OK > >> > >> > > >> >> + > >> >> +Optional parameters: > >> >> +- st,breakinput: Set if the hardware have break input capabilities > >> >> +- st,breakinput-polarity: Set break input polarity. Default is 0 > >> >> + The value define the active polarity: > >> >> + - 0 (active LOW) > >> >> + - 1 (active HIGH) > >> > > >> > Could we fold these into a single property? If st,breakinput-polarity is > >> > not present it could simply mean that there is no break input, and if it > >> > is present you don't have to rely on a default. > >> > >> I need to know if I have to activate breakinput feature and on which level > >> I will rewrite it like that: > >> Optional parameters: > >> - st,breakinput-polarity-high: Set if break input polarity is active > >> on high level. > >> - st,breakinput-polarity-high: Set if break input polarity is active > >> on low level. > > > > How is that different from a single property: > > > > Optional properties: > > - st,breakinput-polarity: If present, a break input is available > > for the channel. In that case the property value denotes the > > polarity of the break input: > > - 0: active low > > - 1: active high > > > > ? > > For break input feature I need two information: do I have to active it > and if activated > on which level. > I have two solutions: > - one parameter with a value (0 or 1) -> st,breakinput-polarity > - two parameters without value -> st,breakinput-active-high and > st,breakinput-active-low > > By default break input feature is disabled Right, what I was suggesting is that you use the first solution because it's the typical way to use for tristate options. It's also much easier to test for in practice because for the second solution you have to parse two properties before you know whether it is active or not. The second is typically the solution for required properties where only one of the properties is used to override the default. Thierry
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-02 11:20 +0100 |
| Subject | [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver |
| Message-ID | <sJT6G-2yH-37@gated-at.bofh.it> |
| In reply to | #1534789 |
Define bindings for stm32 timer trigger
version 3:
- change file name
- add cross reference with mfd bindings
version 2:
- only keep one compatible
- add DT parameters to set lists of the triggers:
one list describe the triggers created by the device
another one give the triggers accepted by the device
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
new file mode 100644
index 0000000..858816d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
@@ -0,0 +1,39 @@
+timer trigger bindings for STM32
+
+Must be a sub-node of STM32 general purpose timer driver
+Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
+
+Required parameters:
+- compatible: must be "st,stm32-iio-timer"
+- interrupts: Interrupt for this device
+ See ../interrupt-controller/st,stm32-exti.txt
+
+Optional parameters:
+- st,input-triggers-names: List of the possible input triggers for
+ the device
+- st,output-triggers-names: List of the possible output triggers for
+ the device
+
+Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-timer-trigger.h
+
+Example:
+ gptimer1: gptimer1@40010000 {
+ compatible = "st,stm32-gptimer";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+
+ timer1@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <27>;
+ st,input-triggers-names = TIM5_TRGO,
+ TIM2_TRGO,
+ TIM4_TRGO,
+ TIM3_TRGO;
+ st,output-triggers-names = TIM1_TRGO,
+ TIM1_CH1,
+ TIM1_CH2,
+ TIM1_CH3,
+ TIM1_CH4;
+ };
+ };
--
1.9.1
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-12-02 15:00 +0100 |
| Subject | Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver |
| Message-ID | <sJWxz-4wP-21@gated-at.bofh.it> |
| In reply to | #1534797 |
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
> Define bindings for stm32 timer trigger
>
> version 3:
> - change file name
> - add cross reference with mfd bindings
>
> version 2:
> - only keep one compatible
> - add DT parameters to set lists of the triggers:
> one list describe the triggers created by the device
> another one give the triggers accepted by the device
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
> new file mode 100644
> index 0000000..858816d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
> @@ -0,0 +1,39 @@
> +timer trigger bindings for STM32
> +
> +Must be a sub-node of STM32 general purpose timer driver
> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
> +
> +Required parameters:
> +- compatible: must be "st,stm32-iio-timer"
> +- interrupts: Interrupt for this device
> + See ../interrupt-controller/st,stm32-exti.txt
> +
> +Optional parameters:
> +- st,input-triggers-names: List of the possible input triggers for
> + the device
> +- st,output-triggers-names: List of the possible output triggers for
> + the device
> +
> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-timer-trigger.h
> +
> +Example:
> + gptimer1: gptimer1@40010000 {
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + timer1@0 {
> + compatible = "st,stm32-timer-trigger";
> + interrupts = <27>;
> + st,input-triggers-names = TIM5_TRGO,
> + TIM2_TRGO,
> + TIM4_TRGO,
> + TIM3_TRGO;
> + st,output-triggers-names = TIM1_TRGO,
> + TIM1_CH1,
> + TIM1_CH2,
> + TIM1_CH3,
> + TIM1_CH4;
I see why you've done it like this now ... because it makes things
easier for you in the driver, since the IIO subsystem matches on names
such as these.
BUT, this is a Linux-implementation-ism. Just use pairs of integers
and create the Linux-ism strings in the driver.
> + };
> + };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-02 15:30 +0100 |
| Subject | Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver |
| Message-ID | <sJX0B-4ZC-19@gated-at.bofh.it> |
| In reply to | #1534933 |
2016-12-02 14:59 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
>
>> Define bindings for stm32 timer trigger
>>
>> version 3:
>> - change file name
>> - add cross reference with mfd bindings
>>
>> version 2:
>> - only keep one compatible
>> - add DT parameters to set lists of the triggers:
>> one list describe the triggers created by the device
>> another one give the triggers accepted by the device
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> new file mode 100644
>> index 0000000..858816d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> @@ -0,0 +1,39 @@
>> +timer trigger bindings for STM32
>> +
>> +Must be a sub-node of STM32 general purpose timer driver
>> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
>> +
>> +Required parameters:
>> +- compatible: must be "st,stm32-iio-timer"
>> +- interrupts: Interrupt for this device
>> + See ../interrupt-controller/st,stm32-exti.txt
>> +
>> +Optional parameters:
>> +- st,input-triggers-names: List of the possible input triggers for
>> + the device
>> +- st,output-triggers-names: List of the possible output triggers for
>> + the device
>> +
>> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-timer-trigger.h
>> +
>> +Example:
>> + gptimer1: gptimer1@40010000 {
>> + compatible = "st,stm32-gptimer";
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "clk_int";
>> +
>> + timer1@0 {
>> + compatible = "st,stm32-timer-trigger";
>> + interrupts = <27>;
>> + st,input-triggers-names = TIM5_TRGO,
>> + TIM2_TRGO,
>> + TIM4_TRGO,
>> + TIM3_TRGO;
>> + st,output-triggers-names = TIM1_TRGO,
>> + TIM1_CH1,
>> + TIM1_CH2,
>> + TIM1_CH3,
>> + TIM1_CH4;
>
> I see why you've done it like this now ... because it makes things
> easier for you in the driver, since the IIO subsystem matches on names
> such as these.
>
> BUT, this is a Linux-implementation-ism. Just use pairs of integers
> and create the Linux-ism strings in the driver.
The goal is not to make things easier in driver but to be able to share
the triggers names with other drivers like DAC or ADC.
If each driver have to create it own triggers names it will more difficult
to keep them coherent than it they share the same definitions
>
>> + };
>> + };
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
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| From | Jonathan Cameron <jic23@kernel.org> |
|---|---|
| Date | 2016-12-03 15:50 +0100 |
| Subject | Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver |
| Message-ID | <sKjNw-2Bb-15@gated-at.bofh.it> |
| In reply to | #1534978 |
On 02/12/16 14:23, Benjamin Gaignard wrote:
> 2016-12-02 14:59 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
>> On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
>>
>>> Define bindings for stm32 timer trigger
>>>
>>> version 3:
>>> - change file name
>>> - add cross reference with mfd bindings
>>>
>>> version 2:
>>> - only keep one compatible
>>> - add DT parameters to set lists of the triggers:
>>> one list describe the triggers created by the device
>>> another one give the triggers accepted by the device
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>> ---
>>> .../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++++++++++++++++++++++
>>> 1 file changed, 39 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>> new file mode 100644
>>> index 0000000..858816d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>> @@ -0,0 +1,39 @@
>>> +timer trigger bindings for STM32
>>> +
>>> +Must be a sub-node of STM32 general purpose timer driver
>>> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
>>> +
>>> +Required parameters:
>>> +- compatible: must be "st,stm32-iio-timer"
>>> +- interrupts: Interrupt for this device
>>> + See ../interrupt-controller/st,stm32-exti.txt
>>> +
>>> +Optional parameters:
>>> +- st,input-triggers-names: List of the possible input triggers for
>>> + the device
>>> +- st,output-triggers-names: List of the possible output triggers for
>>> + the device
>>> +
>>> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-timer-trigger.h
>>> +
>>> +Example:
>>> + gptimer1: gptimer1@40010000 {
>>> + compatible = "st,stm32-gptimer";
>>> + reg = <0x40010000 0x400>;
>>> + clocks = <&rcc 0 160>;
>>> + clock-names = "clk_int";
>>> +
>>> + timer1@0 {
>>> + compatible = "st,stm32-timer-trigger";
>>> + interrupts = <27>;
>>> + st,input-triggers-names = TIM5_TRGO,
>>> + TIM2_TRGO,
>>> + TIM4_TRGO,
>>> + TIM3_TRGO;
>>> + st,output-triggers-names = TIM1_TRGO,
>>> + TIM1_CH1,
>>> + TIM1_CH2,
>>> + TIM1_CH3,
>>> + TIM1_CH4;
>>
>> I see why you've done it like this now ... because it makes things
>> easier for you in the driver, since the IIO subsystem matches on names
>> such as these.
>>
>> BUT, this is a Linux-implementation-ism. Just use pairs of integers
>> and create the Linux-ism strings in the driver.
>
> The goal is not to make things easier in driver but to be able to share
> the triggers names with other drivers like DAC or ADC.
> If each driver have to create it own triggers names it will more difficult
> to keep them coherent than it they share the same definitions
Do it by documentation. This will be effectively ABI going forward
so fixed once it is defined. Should be fairly easy to tell during testing
if someone has messed it up ;)
Jonathan
>
>>
>>> + };
>>> + };
>>
>> --
>> Lee Jones
>> Linaro STMicroelectronics Landing Team Lead
>> Linaro.org │ Open source software for ARM SoCs
>> Follow Linaro: Facebook | Twitter | Blog
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-02 11:20 +0100 |
| Subject | [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm |
| Message-ID | <sJT6F-2yH-23@gated-at.bofh.it> |
| In reply to | #1534789 |
This driver add support for pwm driver on stm32 platform.
The SoC have multiple instances of the hardware IP and each
of them could have small differences: number of channels,
complementary output, counter register size...
Use DT parameters to handle those differentes configuration
version 2:
- only keep one comptatible
- use DT paramaters to discover hardware block configuration
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
drivers/pwm/Kconfig | 8 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 294 insertions(+)
create mode 100644 drivers/pwm/pwm-stm32.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index bf01288..a89fdba 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -388,6 +388,14 @@ config PWM_STI
To compile this driver as a module, choose M here: the module
will be called pwm-sti.
+config PWM_STM32
+ bool "STMicroelectronics STM32 PWM"
+ depends on ARCH_STM32
+ depends on OF
+ select MFD_STM32_GP_TIMER
+ help
+ Generic PWM framework driver for STM32 SoCs.
+
config PWM_STMPE
bool "STMPE expander PWM export"
depends on MFD_STMPE
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 1194c54..5aa9308 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
+obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
new file mode 100644
index 0000000..a362f63
--- /dev/null
+++ b/drivers/pwm/pwm-stm32.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Gerald Baeza <gerald.baeza@st.com>
+ * License terms: GNU General Public License (GPL), version 2
+ *
+ * Inspired by timer-stm32.c from Maxime Coquelin
+ * pwm-atmel.c from Bo Shen
+ */
+
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#include <linux/mfd/stm32-gptimer.h>
+
+#define DRIVER_NAME "stm32-pwm"
+
+#define CAP_COMPLEMENTARY BIT(0)
+#define CAP_32BITS_COUNTER BIT(1)
+#define CAP_BREAKINPUT BIT(2)
+#define CAP_BREAKINPUT_POLARITY BIT(3)
+
+struct stm32_pwm_dev {
+ struct device *dev;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct pwm_chip chip;
+ int caps;
+ int npwm;
+ u32 polarity;
+};
+
+#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
+
+static u32 __active_channels(struct stm32_pwm_dev *pwm_dev)
+{
+ u32 ccer;
+
+ regmap_read(pwm_dev->regmap, TIM_CCER, &ccer);
+
+ return ccer & TIM_CCER_CCXE;
+}
+
+static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm,
+ u32 ccr)
+{
+ switch (pwm->hwpwm) {
+ case 0:
+ return regmap_write(dev->regmap, TIM_CCR1, ccr);
+ case 1:
+ return regmap_write(dev->regmap, TIM_CCR2, ccr);
+ case 2:
+ return regmap_write(dev->regmap, TIM_CCR3, ccr);
+ case 3:
+ return regmap_write(dev->regmap, TIM_CCR4, ccr);
+ }
+ return -EINVAL;
+}
+
+static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+ unsigned long long prd, div, dty;
+ int prescaler = 0;
+ u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr;
+
+ if (dev->caps & CAP_32BITS_COUNTER)
+ max_arr = 0xFFFFFFFF;
+
+ /* Period and prescaler values depends of clock rate */
+ div = (unsigned long long)clk_get_rate(dev->clk) * period_ns;
+
+ do_div(div, NSEC_PER_SEC);
+ prd = div;
+
+ while (div > max_arr) {
+ prescaler++;
+ div = prd;
+ do_div(div, (prescaler + 1));
+ }
+ prd = div;
+
+ if (prescaler > MAX_TIM_PSC) {
+ dev_err(chip->dev, "prescaler exceeds the maximum value\n");
+ return -EINVAL;
+ }
+
+ /* All channels share the same prescaler and counter so
+ * when two channels are active at the same we can't change them
+ */
+ if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) {
+ u32 psc, arr;
+
+ regmap_read(dev->regmap, TIM_PSC, &psc);
+ regmap_read(dev->regmap, TIM_ARR, &arr);
+
+ if ((psc != prescaler) || (arr != prd - 1))
+ return -EINVAL;
+ }
+
+ regmap_write(dev->regmap, TIM_PSC, prescaler);
+ regmap_write(dev->regmap, TIM_ARR, prd - 1);
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
+
+ /* Calculate the duty cycles */
+ dty = prd * duty_ns;
+ do_div(dty, period_ns);
+
+ write_ccrx(dev, pwm, dty);
+
+ /* Configure output mode */
+ shift = (pwm->hwpwm & 0x1) * 8;
+ ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
+ mask = 0xFF << shift;
+
+ if (pwm->hwpwm & 0x2)
+ regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr);
+ else
+ regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr);
+
+ if (!(dev->caps & CAP_BREAKINPUT))
+ return 0;
+
+ bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE;
+
+ if (dev->caps & CAP_BREAKINPUT_POLARITY)
+ bdtr |= TIM_BDTR_BKE;
+
+ if (dev->polarity)
+ bdtr |= TIM_BDTR_BKP;
+
+ regmap_update_bits(dev->regmap, TIM_BDTR,
+ TIM_BDTR_MOE | TIM_BDTR_AOE |
+ TIM_BDTR_BKP | TIM_BDTR_BKE,
+ bdtr);
+
+ return 0;
+}
+
+static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
+ if (dev->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask,
+ polarity == PWM_POLARITY_NORMAL ? 0 : mask);
+
+ return 0;
+}
+
+static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ clk_enable(dev->clk);
+
+ /* Enable channel */
+ mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
+ if (dev->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask, mask);
+
+ /* Make sure that registers are updated */
+ regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+
+ /* Enable controller */
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
+
+ return 0;
+}
+
+static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ u32 mask;
+ struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
+
+ /* Disable channel */
+ mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
+ if (dev->caps & CAP_COMPLEMENTARY)
+ mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
+
+ regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
+
+ /* When all channels are disabled, we can disable the controller */
+ if (!__active_channels(dev))
+ regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+
+ clk_disable(dev->clk);
+}
+
+static const struct pwm_ops stm32pwm_ops = {
+ .config = stm32_pwm_config,
+ .set_polarity = stm32_pwm_set_polarity,
+ .enable = stm32_pwm_enable,
+ .disable = stm32_pwm_disable,
+};
+
+static int stm32_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent);
+ struct stm32_pwm_dev *pwm;
+ int ret;
+
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ pwm->regmap = mfd->regmap;
+ pwm->clk = mfd->clk;
+
+ if (!pwm->regmap || !pwm->clk)
+ return -EINVAL;
+
+ if (of_property_read_bool(np, "st,complementary"))
+ pwm->caps |= CAP_COMPLEMENTARY;
+
+ if (of_property_read_bool(np, "st,32bits-counter"))
+ pwm->caps |= CAP_32BITS_COUNTER;
+
+ if (of_property_read_bool(np, "st,breakinput"))
+ pwm->caps |= CAP_BREAKINPUT;
+
+ if (!of_property_read_u32(np, "st,breakinput-polarity", &pwm->polarity))
+ pwm->caps |= CAP_BREAKINPUT_POLARITY;
+
+ of_property_read_u32(np, "st,pwm-num-chan", &pwm->npwm);
+
+ pwm->chip.base = -1;
+ pwm->chip.dev = dev;
+ pwm->chip.ops = &stm32pwm_ops;
+ pwm->chip.npwm = pwm->npwm;
+
+ ret = pwmchip_add(&pwm->chip);
+ if (ret < 0)
+ return ret;
+
+ platform_set_drvdata(pdev, pwm);
+
+ return 0;
+}
+
+static int stm32_pwm_remove(struct platform_device *pdev)
+{
+ struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < pwm->npwm; i++)
+ pwm_disable(&pwm->chip.pwms[i]);
+
+ pwmchip_remove(&pwm->chip);
+
+ return 0;
+}
+
+static const struct of_device_id stm32_pwm_of_match[] = {
+ {
+ .compatible = "st,stm32-pwm",
+ },
+};
+MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
+
+static struct platform_driver stm32_pwm_driver = {
+ .probe = stm32_pwm_probe,
+ .remove = stm32_pwm_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = stm32_pwm_of_match,
+ },
+};
+module_platform_driver(stm32_pwm_driver);
+
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-12-05 08:30 +0100 |
| Subject | Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm |
| Message-ID | <sKVSN-1tp-7@gated-at.bofh.it> |
| In reply to | #1534798 |
[Multipart message — attachments visible in raw view] — view raw
On Fri, Dec 02, 2016 at 11:17:19AM +0100, Benjamin Gaignard wrote:
> This driver add support for pwm driver on stm32 platform.
"adds". Also please use PWM in prose because it's an abbreviation.
> The SoC have multiple instances of the hardware IP and each
> of them could have small differences: number of channels,
> complementary output, counter register size...
> Use DT parameters to handle those differentes configuration
"different configurations"
>
> version 2:
> - only keep one comptatible
> - use DT paramaters to discover hardware block configuration
"parameters"
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> drivers/pwm/Kconfig | 8 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 294 insertions(+)
> create mode 100644 drivers/pwm/pwm-stm32.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index bf01288..a89fdba 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -388,6 +388,14 @@ config PWM_STI
> To compile this driver as a module, choose M here: the module
> will be called pwm-sti.
>
> +config PWM_STM32
> + bool "STMicroelectronics STM32 PWM"
> + depends on ARCH_STM32
> + depends on OF
> + select MFD_STM32_GP_TIMER
Should that be a "depends on"?
> + help
> + Generic PWM framework driver for STM32 SoCs.
> +
> config PWM_STMPE
> bool "STMPE expander PWM export"
> depends on MFD_STMPE
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 1194c54..5aa9308 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
> obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> obj-$(CONFIG_PWM_STI) += pwm-sti.o
> +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
> obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
> obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
> diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
> new file mode 100644
> index 0000000..a362f63
> --- /dev/null
> +++ b/drivers/pwm/pwm-stm32.c
> @@ -0,0 +1,285 @@
> +/*
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Gerald Baeza <gerald.baeza@st.com>
Could use a blank line between the above. Also, please use a single
space after : for consistency.
> + * License terms: GNU General Public License (GPL), version 2
Here too.
> + *
> + * Inspired by timer-stm32.c from Maxime Coquelin
> + * pwm-atmel.c from Bo Shen
> + */
> +
> +#include <linux/of.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
Please sort these alphabetically.
> +
> +#include <linux/mfd/stm32-gptimer.h>
> +
> +#define DRIVER_NAME "stm32-pwm"
> +
> +#define CAP_COMPLEMENTARY BIT(0)
> +#define CAP_32BITS_COUNTER BIT(1)
> +#define CAP_BREAKINPUT BIT(2)
> +#define CAP_BREAKINPUT_POLARITY BIT(3)
Just make these boolean. Makes the conditionals a lot simpler to read.
> +
> +struct stm32_pwm_dev {
No need for the _dev suffix.
> + struct device *dev;
> + struct clk *clk;
> + struct regmap *regmap;
> + struct pwm_chip chip;
It's slightly more efficient to put this as first field because then
to_stm32_pwm() becomes a no-op.
> + int caps;
> + int npwm;
unsigned int, please.
> + u32 polarity;
Maybe use a prefix here to stress that it is the polarity of the
complementary output. Otherwise one might take it for the PWM signal's
polarity that's already part of the PWM state.
> +};
> +
> +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
Please turn this into a static inline.
> +
> +static u32 __active_channels(struct stm32_pwm_dev *pwm_dev)
No need for a __ prefix.
> +{
> + u32 ccer;
> +
> + regmap_read(pwm_dev->regmap, TIM_CCER, &ccer);
> +
> + return ccer & TIM_CCER_CCXE;
> +}
> +
> +static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm,
> + u32 ccr)
u32 value, perhaps? I first mistook this to be a register offset.
> +{
> + switch (pwm->hwpwm) {
> + case 0:
> + return regmap_write(dev->regmap, TIM_CCR1, ccr);
> + case 1:
> + return regmap_write(dev->regmap, TIM_CCR2, ccr);
> + case 2:
> + return regmap_write(dev->regmap, TIM_CCR3, ccr);
> + case 3:
> + return regmap_write(dev->regmap, TIM_CCR4, ccr);
> + }
> + return -EINVAL;
> +}
> +
> +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> + int duty_ns, int period_ns)
Please implement this as an atomic PWM driver, I don't want new drivers
to use the legacy callbacks.
> +{
> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
I think something like "stm", or "priv" would be more appropriate here.
If you ever need access to a struct device, you'll be hard-pressed to
find a good name for it.
> + unsigned long long prd, div, dty;
> + int prescaler = 0;
If this can never be negative, please make it unsigned int.
> + u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr;
> +
> + if (dev->caps & CAP_32BITS_COUNTER)
> + max_arr = 0xFFFFFFFF;
I prefer lower-case hexadecimal digits.
> +
> + /* Period and prescaler values depends of clock rate */
"depend on"
> + div = (unsigned long long)clk_get_rate(dev->clk) * period_ns;
> +
> + do_div(div, NSEC_PER_SEC);
> + prd = div;
> +
> + while (div > max_arr) {
> + prescaler++;
> + div = prd;
> + do_div(div, (prescaler + 1));
> + }
> + prd = div;
Blank line after blocks, please.
> +
> + if (prescaler > MAX_TIM_PSC) {
> + dev_err(chip->dev, "prescaler exceeds the maximum value\n");
> + return -EINVAL;
> + }
> +
> + /* All channels share the same prescaler and counter so
> + * when two channels are active at the same we can't change them
> + */
This isn't proper block comment style. Also, please use all of the
columns at your disposal.
> + if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) {
> + u32 psc, arr;
> +
> + regmap_read(dev->regmap, TIM_PSC, &psc);
> + regmap_read(dev->regmap, TIM_ARR, &arr);
> +
> + if ((psc != prescaler) || (arr != prd - 1))
> + return -EINVAL;
Maybe -EBUSY to differentiate from other error cases?
> + }
> +
> + regmap_write(dev->regmap, TIM_PSC, prescaler);
> + regmap_write(dev->regmap, TIM_ARR, prd - 1);
> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
> +
> + /* Calculate the duty cycles */
> + dty = prd * duty_ns;
> + do_div(dty, period_ns);
> +
> + write_ccrx(dev, pwm, dty);
> +
> + /* Configure output mode */
> + shift = (pwm->hwpwm & 0x1) * 8;
> + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
> + mask = 0xFF << shift;
> +
> + if (pwm->hwpwm & 0x2)
This looks as though TIM_CCMR1 is used for channels 0 and 1, while
TIM_CCMR2 is used for channels 2 and 3. Wouldn't it be more natural to
make the conditional above:
if (pwm->hwpwm >= 2)
? Or perhaps better yet:
if (pwm->hwpwm < 2)
/* update TIM_CCMR1 */
else
/* update TIM_CCMR2 */
The other alternative, which might make the code slightly more readable,
would be to get rid of all these conditionals by parameterizing the
offsets per PWM channel. The PWM subsystem has a means of storing per-
channel chip-specific data (see pwm_{set,get}_chip_data()). It might be
a little overkill for this particular driver, given that the number of
conditionals is fairly small.
> + regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr);
> + else
> + regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr);
> +
> + if (!(dev->caps & CAP_BREAKINPUT))
> + return 0;
If you make these capabilities boolean, it becomes much more readable,
especially for negations:
if (!dev->has_breakinput)
> +
> + bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE;
> +
> + if (dev->caps & CAP_BREAKINPUT_POLARITY)
> + bdtr |= TIM_BDTR_BKE;
> +
> + if (dev->polarity)
> + bdtr |= TIM_BDTR_BKP;
> +
> + regmap_update_bits(dev->regmap, TIM_BDTR,
> + TIM_BDTR_MOE | TIM_BDTR_AOE |
> + TIM_BDTR_BKP | TIM_BDTR_BKE,
> + bdtr);
> +
> + return 0;
> +}
> +
> +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> + enum pwm_polarity polarity)
> +{
> + u32 mask;
> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> +
> + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
> + if (dev->caps & CAP_COMPLEMENTARY)
> + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
> +
> + regmap_update_bits(dev->regmap, TIM_CCER, mask,
> + polarity == PWM_POLARITY_NORMAL ? 0 : mask);
> +
> + return 0;
> +}
> +
> +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
> +{
> + u32 mask;
> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> +
> + clk_enable(dev->clk);
> +
> + /* Enable channel */
> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
> + if (dev->caps & CAP_COMPLEMENTARY)
> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
> +
> + regmap_update_bits(dev->regmap, TIM_CCER, mask, mask);
> +
> + /* Make sure that registers are updated */
> + regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
> +
> + /* Enable controller */
> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
> +
> + return 0;
> +}
> +
> +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> +{
> + u32 mask;
> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> +
> + /* Disable channel */
> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
> + if (dev->caps & CAP_COMPLEMENTARY)
> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
> +
> + regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
> +
> + /* When all channels are disabled, we can disable the controller */
> + if (!__active_channels(dev))
> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
> +
> + clk_disable(dev->clk);
> +}
All of the above can be folded into the ->apply() hook for atomic PWM
support.
Also, in the above you use clk_enable() in the ->enable() callback and
clk_disable() in ->disable(). If you need the clock to access registers
you'll have to enabled it in the others as well because there are no
guarantees that configuration will only happen between ->enable() and
->disable(). Atomic PWM simplifies this a bit, but you still need to be
careful about when to enable the clock in your ->apply() hook.
> +
> +static const struct pwm_ops stm32pwm_ops = {
> + .config = stm32_pwm_config,
> + .set_polarity = stm32_pwm_set_polarity,
> + .enable = stm32_pwm_enable,
> + .disable = stm32_pwm_disable,
> +};
You need to set the .owner field as well.
> +
> +static int stm32_pwm_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent);
> + struct stm32_pwm_dev *pwm;
> + int ret;
> +
> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> + if (!pwm)
> + return -ENOMEM;
> +
> + pwm->regmap = mfd->regmap;
> + pwm->clk = mfd->clk;
> +
> + if (!pwm->regmap || !pwm->clk)
> + return -EINVAL;
> +
> + if (of_property_read_bool(np, "st,complementary"))
> + pwm->caps |= CAP_COMPLEMENTARY;
> +
> + if (of_property_read_bool(np, "st,32bits-counter"))
> + pwm->caps |= CAP_32BITS_COUNTER;
> +
> + if (of_property_read_bool(np, "st,breakinput"))
> + pwm->caps |= CAP_BREAKINPUT;
> +
> + if (!of_property_read_u32(np, "st,breakinput-polarity", &pwm->polarity))
> + pwm->caps |= CAP_BREAKINPUT_POLARITY;
> +
> + of_property_read_u32(np, "st,pwm-num-chan", &pwm->npwm);
> +
> + pwm->chip.base = -1;
> + pwm->chip.dev = dev;
> + pwm->chip.ops = &stm32pwm_ops;
> + pwm->chip.npwm = pwm->npwm;
> +
> + ret = pwmchip_add(&pwm->chip);
> + if (ret < 0)
> + return ret;
> +
> + platform_set_drvdata(pdev, pwm);
> +
> + return 0;
> +}
> +
> +static int stm32_pwm_remove(struct platform_device *pdev)
> +{
> + struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev);
> + int i;
unsigned int, please.
> +
> + for (i = 0; i < pwm->npwm; i++)
> + pwm_disable(&pwm->chip.pwms[i]);
> +
> + pwmchip_remove(&pwm->chip);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_pwm_of_match[] = {
> + {
> + .compatible = "st,stm32-pwm",
> + },
The above can be collapsed into a single line.
> +};
> +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
> +
> +static struct platform_driver stm32_pwm_driver = {
> + .probe = stm32_pwm_probe,
> + .remove = stm32_pwm_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = stm32_pwm_of_match,
> + },
> +};
Please don't use tabs for padding within the structure definition since
it doesn't align properly anyway.
> +module_platform_driver(stm32_pwm_driver);
> +
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
> +MODULE_LICENSE("GPL");
According to the header comment this should be "GPL v2".
Thanks,
Thierry
[toc] | [prev] | [next] | [standalone]
| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-12-05 09:30 +0100 |
| Subject | Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm |
| Message-ID | <sKWOR-2aU-7@gated-at.bofh.it> |
| In reply to | #1535864 |
On Mon, 05 Dec 2016, Thierry Reding wrote:
> On Fri, Dec 02, 2016 at 11:17:19AM +0100, Benjamin Gaignard wrote:
> > This driver add support for pwm driver on stm32 platform.
>
> "adds". Also please use PWM in prose because it's an abbreviation.
>
> > The SoC have multiple instances of the hardware IP and each
> > of them could have small differences: number of channels,
> > complementary output, counter register size...
> > Use DT parameters to handle those differentes configuration
>
> "different configurations"
>
> >
> > version 2:
> > - only keep one comptatible
> > - use DT paramaters to discover hardware block configuration
>
> "parameters"
>
> >
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> > ---
> > drivers/pwm/Kconfig | 8 ++
> > drivers/pwm/Makefile | 1 +
> > drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 294 insertions(+)
> > create mode 100644 drivers/pwm/pwm-stm32.c
> >
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index bf01288..a89fdba 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -388,6 +388,14 @@ config PWM_STI
> > To compile this driver as a module, choose M here: the module
> > will be called pwm-sti.
> >
> > +config PWM_STM32
> > + bool "STMicroelectronics STM32 PWM"
> > + depends on ARCH_STM32
> > + depends on OF
> > + select MFD_STM32_GP_TIMER
>
> Should that be a "depends on"?
>
> > + help
> > + Generic PWM framework driver for STM32 SoCs.
> > +
> > config PWM_STMPE
> > bool "STMPE expander PWM export"
> > depends on MFD_STMPE
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index 1194c54..5aa9308 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
> > obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
> > obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> > obj-$(CONFIG_PWM_STI) += pwm-sti.o
> > +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> > obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
> > obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
> > obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
> > diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
> > new file mode 100644
> > index 0000000..a362f63
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-stm32.c
> > @@ -0,0 +1,285 @@
> > +/*
> > + * Copyright (C) STMicroelectronics 2016
> > + * Author: Gerald Baeza <gerald.baeza@st.com>
>
> Could use a blank line between the above. Also, please use a single
> space after : for consistency.
>
> > + * License terms: GNU General Public License (GPL), version 2
>
> Here too.
>
> > + *
> > + * Inspired by timer-stm32.c from Maxime Coquelin
> > + * pwm-atmel.c from Bo Shen
> > + */
> > +
> > +#include <linux/of.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pwm.h>
>
> Please sort these alphabetically.
>
> > +
> > +#include <linux/mfd/stm32-gptimer.h>
> > +
> > +#define DRIVER_NAME "stm32-pwm"
> > +
> > +#define CAP_COMPLEMENTARY BIT(0)
> > +#define CAP_32BITS_COUNTER BIT(1)
> > +#define CAP_BREAKINPUT BIT(2)
> > +#define CAP_BREAKINPUT_POLARITY BIT(3)
>
> Just make these boolean. Makes the conditionals a lot simpler to read.
>
> > +
> > +struct stm32_pwm_dev {
>
> No need for the _dev suffix.
I usually like ddata (short for device data, which is what it is).
I'll be asking for the same in the MFD driver too.
> > + struct device *dev;
> > + struct clk *clk;
> > + struct regmap *regmap;
> > + struct pwm_chip chip;
>
> It's slightly more efficient to put this as first field because then
> to_stm32_pwm() becomes a no-op.
Niiiice!
> > + int caps;
> > + int npwm;
>
> unsigned int, please.
>
> > + u32 polarity;
>
> Maybe use a prefix here to stress that it is the polarity of the
> complementary output. Otherwise one might take it for the PWM signal's
> polarity that's already part of the PWM state.
>
> > +};
> > +
> > +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
>
> Please turn this into a static inline.
>
> > +
> > +static u32 __active_channels(struct stm32_pwm_dev *pwm_dev)
>
> No need for a __ prefix.
>
> > +{
> > + u32 ccer;
> > +
> > + regmap_read(pwm_dev->regmap, TIM_CCER, &ccer);
> > +
> > + return ccer & TIM_CCER_CCXE;
> > +}
> > +
> > +static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm,
> > + u32 ccr)
>
> u32 value, perhaps? I first mistook this to be a register offset.
>
> > +{
> > + switch (pwm->hwpwm) {
> > + case 0:
> > + return regmap_write(dev->regmap, TIM_CCR1, ccr);
> > + case 1:
> > + return regmap_write(dev->regmap, TIM_CCR2, ccr);
> > + case 2:
> > + return regmap_write(dev->regmap, TIM_CCR3, ccr);
> > + case 3:
> > + return regmap_write(dev->regmap, TIM_CCR4, ccr);
> > + }
> > + return -EINVAL;
> > +}
> > +
> > +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > + int duty_ns, int period_ns)
>
> Please implement this as an atomic PWM driver, I don't want new drivers
> to use the legacy callbacks.
>
> > +{
> > + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
>
> I think something like "stm", or "priv" would be more appropriate here.
> If you ever need access to a struct device, you'll be hard-pressed to
> find a good name for it.
See above.
> > + unsigned long long prd, div, dty;
> > + int prescaler = 0;
>
> If this can never be negative, please make it unsigned int.
>
> > + u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr;
> > +
> > + if (dev->caps & CAP_32BITS_COUNTER)
> > + max_arr = 0xFFFFFFFF;
>
> I prefer lower-case hexadecimal digits.
Even better to define the max values.
> > +
> > + /* Period and prescaler values depends of clock rate */
>
> "depend on"
>
> > + div = (unsigned long long)clk_get_rate(dev->clk) * period_ns;
> > +
> > + do_div(div, NSEC_PER_SEC);
> > + prd = div;
> > +
> > + while (div > max_arr) {
> > + prescaler++;
> > + div = prd;
> > + do_div(div, (prescaler + 1));
> > + }
> > + prd = div;
>
> Blank line after blocks, please.
... unless directly related to the block, which I think this is. It's
the '\n' *before* the block which confuses me.
> > + if (prescaler > MAX_TIM_PSC) {
> > + dev_err(chip->dev, "prescaler exceeds the maximum value\n");
> > + return -EINVAL;
> > + }
> > +
> > + /* All channels share the same prescaler and counter so
> > + * when two channels are active at the same we can't change them
> > + */
>
> This isn't proper block comment style. Also, please use all of the
> columns at your disposal.
>
> > + if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) {
> > + u32 psc, arr;
> > +
> > + regmap_read(dev->regmap, TIM_PSC, &psc);
> > + regmap_read(dev->regmap, TIM_ARR, &arr);
> > +
> > + if ((psc != prescaler) || (arr != prd - 1))
> > + return -EINVAL;
>
> Maybe -EBUSY to differentiate from other error cases?
>
> > + }
> > +
> > + regmap_write(dev->regmap, TIM_PSC, prescaler);
> > + regmap_write(dev->regmap, TIM_ARR, prd - 1);
> > + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
> > +
> > + /* Calculate the duty cycles */
> > + dty = prd * duty_ns;
> > + do_div(dty, period_ns);
> > +
> > + write_ccrx(dev, pwm, dty);
> > +
> > + /* Configure output mode */
> > + shift = (pwm->hwpwm & 0x1) * 8;
> > + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
> > + mask = 0xFF << shift;
> > +
> > + if (pwm->hwpwm & 0x2)
>
> This looks as though TIM_CCMR1 is used for channels 0 and 1, while
> TIM_CCMR2 is used for channels 2 and 3. Wouldn't it be more natural to
> make the conditional above:
>
> if (pwm->hwpwm >= 2)
>
> ? Or perhaps better yet:
>
> if (pwm->hwpwm < 2)
> /* update TIM_CCMR1 */
> else
> /* update TIM_CCMR2 */
And please define the magic numbers.
*_MASK
*_SHIFT
> The other alternative, which might make the code slightly more readable,
> would be to get rid of all these conditionals by parameterizing the
> offsets per PWM channel. The PWM subsystem has a means of storing per-
> channel chip-specific data (see pwm_{set,get}_chip_data()). It might be
> a little overkill for this particular driver, given that the number of
> conditionals is fairly small.
>
> > + regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr);
> > + else
> > + regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr);
> > +
> > + if (!(dev->caps & CAP_BREAKINPUT))
> > + return 0;
>
> If you make these capabilities boolean, it becomes much more readable,
> especially for negations:
>
> if (!dev->has_breakinput)
+1
> > +
> > + bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE;
> > +
> > + if (dev->caps & CAP_BREAKINPUT_POLARITY)
> > + bdtr |= TIM_BDTR_BKE;
> > +
> > + if (dev->polarity)
> > + bdtr |= TIM_BDTR_BKP;
> > +
> > + regmap_update_bits(dev->regmap, TIM_BDTR,
> > + TIM_BDTR_MOE | TIM_BDTR_AOE |
> > + TIM_BDTR_BKP | TIM_BDTR_BKE,
> > + bdtr);
> > +
> > + return 0;
> > +}
> > +
> > +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> > + enum pwm_polarity polarity)
> > +{
> > + u32 mask;
> > + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> > +
> > + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
> > + if (dev->caps & CAP_COMPLEMENTARY)
> > + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
> > +
> > + regmap_update_bits(dev->regmap, TIM_CCER, mask,
> > + polarity == PWM_POLARITY_NORMAL ? 0 : mask);
> > +
> > + return 0;
> > +}
> > +
> > +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
> > +{
> > + u32 mask;
> > + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> > +
> > + clk_enable(dev->clk);
> > +
> > + /* Enable channel */
> > + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
> > + if (dev->caps & CAP_COMPLEMENTARY)
> > + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
> > +
> > + regmap_update_bits(dev->regmap, TIM_CCER, mask, mask);
> > +
> > + /* Make sure that registers are updated */
> > + regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
> > +
> > + /* Enable controller */
> > + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
> > +
> > + return 0;
> > +}
> > +
> > +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> > +{
> > + u32 mask;
> > + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> > +
> > + /* Disable channel */
> > + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
> > + if (dev->caps & CAP_COMPLEMENTARY)
> > + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
> > +
> > + regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
> > +
> > + /* When all channels are disabled, we can disable the controller */
> > + if (!__active_channels(dev))
> > + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
> > +
> > + clk_disable(dev->clk);
> > +}
>
> All of the above can be folded into the ->apply() hook for atomic PWM
> support.
>
> Also, in the above you use clk_enable() in the ->enable() callback and
> clk_disable() in ->disable(). If you need the clock to access registers
> you'll have to enabled it in the others as well because there are no
> guarantees that configuration will only happen between ->enable() and
> ->disable(). Atomic PWM simplifies this a bit, but you still need to be
> careful about when to enable the clock in your ->apply() hook.
>
> > +
> > +static const struct pwm_ops stm32pwm_ops = {
> > + .config = stm32_pwm_config,
> > + .set_polarity = stm32_pwm_set_polarity,
> > + .enable = stm32_pwm_enable,
> > + .disable = stm32_pwm_disable,
> > +};
>
> You need to set the .owner field as well.
>
> > +
> > +static int stm32_pwm_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent);
> > + struct stm32_pwm_dev *pwm;
pwm is okay. Please also consider using ddata for consistency across
the driver-set.
> > + int ret;
> > +
> > + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> > + if (!pwm)
> > + return -ENOMEM;
> > +
> > + pwm->regmap = mfd->regmap;
> > + pwm->clk = mfd->clk;
> > +
> > + if (!pwm->regmap || !pwm->clk)
> > + return -EINVAL;
> > +
> > + if (of_property_read_bool(np, "st,complementary"))
> > + pwm->caps |= CAP_COMPLEMENTARY;
> > +
> > + if (of_property_read_bool(np, "st,32bits-counter"))
> > + pwm->caps |= CAP_32BITS_COUNTER;
> > +
> > + if (of_property_read_bool(np, "st,breakinput"))
> > + pwm->caps |= CAP_BREAKINPUT;
> > +
> > + if (!of_property_read_u32(np, "st,breakinput-polarity", &pwm->polarity))
> > + pwm->caps |= CAP_BREAKINPUT_POLARITY;
> > +
> > + of_property_read_u32(np, "st,pwm-num-chan", &pwm->npwm);
> > +
> > + pwm->chip.base = -1;
> > + pwm->chip.dev = dev;
> > + pwm->chip.ops = &stm32pwm_ops;
> > + pwm->chip.npwm = pwm->npwm;
> > +
> > + ret = pwmchip_add(&pwm->chip);
> > + if (ret < 0)
> > + return ret;
> > +
> > + platform_set_drvdata(pdev, pwm);
> > +
> > + return 0;
> > +}
> > +
> > +static int stm32_pwm_remove(struct platform_device *pdev)
> > +{
> > + struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev);
> > + int i;
>
> unsigned int, please.
>
> > +
> > + for (i = 0; i < pwm->npwm; i++)
> > + pwm_disable(&pwm->chip.pwms[i]);
> > +
> > + pwmchip_remove(&pwm->chip);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id stm32_pwm_of_match[] = {
> > + {
> > + .compatible = "st,stm32-pwm",
> > + },
>
> The above can be collapsed into a single line.
+1
> > +};
> > +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
> > +
> > +static struct platform_driver stm32_pwm_driver = {
> > + .probe = stm32_pwm_probe,
> > + .remove = stm32_pwm_remove,
> > + .driver = {
> > + .name = DRIVER_NAME,
> > + .of_match_table = stm32_pwm_of_match,
> > + },
> > +};
>
> Please don't use tabs for padding within the structure definition since
> it doesn't align properly anyway.
+1
> > +module_platform_driver(stm32_pwm_driver);
> > +
> > +MODULE_ALIAS("platform:" DRIVER_NAME);
> > +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
> > +MODULE_LICENSE("GPL");
>
> According to the header comment this should be "GPL v2".
+1
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-05 12:10 +0100 |
| Subject | Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm |
| Message-ID | <sKZjH-3M4-13@gated-at.bofh.it> |
| In reply to | #1535864 |
2016-12-05 8:23 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>:
> On Fri, Dec 02, 2016 at 11:17:19AM +0100, Benjamin Gaignard wrote:
>> This driver add support for pwm driver on stm32 platform.
>
> "adds". Also please use PWM in prose because it's an abbreviation.
>
>> The SoC have multiple instances of the hardware IP and each
>> of them could have small differences: number of channels,
>> complementary output, counter register size...
>> Use DT parameters to handle those differentes configuration
>
> "different configurations"
ok
>
>>
>> version 2:
>> - only keep one comptatible
>> - use DT paramaters to discover hardware block configuration
>
> "parameters"
ok
>
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> drivers/pwm/Kconfig | 8 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 294 insertions(+)
>> create mode 100644 drivers/pwm/pwm-stm32.c
>>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index bf01288..a89fdba 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -388,6 +388,14 @@ config PWM_STI
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-sti.
>>
>> +config PWM_STM32
>> + bool "STMicroelectronics STM32 PWM"
>> + depends on ARCH_STM32
>> + depends on OF
>> + select MFD_STM32_GP_TIMER
>
> Should that be a "depends on"?
I think select is fine because the wanted feature is PWM not the mfd part
>
>> + help
>> + Generic PWM framework driver for STM32 SoCs.
>> +
>> config PWM_STMPE
>> bool "STMPE expander PWM export"
>> depends on MFD_STMPE
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index 1194c54..5aa9308 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
>> obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
>> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
>> obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
>> obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
>> diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
>> new file mode 100644
>> index 0000000..a362f63
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-stm32.c
>> @@ -0,0 +1,285 @@
>> +/*
>> + * Copyright (C) STMicroelectronics 2016
>> + * Author: Gerald Baeza <gerald.baeza@st.com>
>
> Could use a blank line between the above. Also, please use a single
> space after : for consistency.
ok
>
>> + * License terms: GNU General Public License (GPL), version 2
>
> Here too.
OK
>
>> + *
>> + * Inspired by timer-stm32.c from Maxime Coquelin
>> + * pwm-atmel.c from Bo Shen
>> + */
>> +
>> +#include <linux/of.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pwm.h>
>
> Please sort these alphabetically.
ok
>> +
>> +#include <linux/mfd/stm32-gptimer.h>
>> +
>> +#define DRIVER_NAME "stm32-pwm"
>> +
>> +#define CAP_COMPLEMENTARY BIT(0)
>> +#define CAP_32BITS_COUNTER BIT(1)
>> +#define CAP_BREAKINPUT BIT(2)
>> +#define CAP_BREAKINPUT_POLARITY BIT(3)
>
> Just make these boolean. Makes the conditionals a lot simpler to read.
I will do that for v4
>> +
>> +struct stm32_pwm_dev {
>
> No need for the _dev suffix.
>
>> + struct device *dev;
>> + struct clk *clk;
>> + struct regmap *regmap;
>> + struct pwm_chip chip;
>
> It's slightly more efficient to put this as first field because then
> to_stm32_pwm() becomes a no-op.
Ok I will remove it
>
>> + int caps;
>> + int npwm;
>
> unsigned int, please.
>
>> + u32 polarity;
>
> Maybe use a prefix here to stress that it is the polarity of the
> complementary output. Otherwise one might take it for the PWM signal's
> polarity that's already part of the PWM state.
I will rename it
>
>> +};
>> +
>> +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
>
> Please turn this into a static inline.
with putting struct pwm_chip as first filed I will just cast the structure
>> +
>> +static u32 __active_channels(struct stm32_pwm_dev *pwm_dev)
>
> No need for a __ prefix.
I wlll remove it
>
>> +{
>> + u32 ccer;
>> +
>> + regmap_read(pwm_dev->regmap, TIM_CCER, &ccer);
>> +
>> + return ccer & TIM_CCER_CCXE;
>> +}
>> +
>> +static int write_ccrx(struct stm32_pwm_dev *dev, struct pwm_device *pwm,
>> + u32 ccr)
>
> u32 value, perhaps? I first mistook this to be a register offset.
OK
>
>> +{
>> + switch (pwm->hwpwm) {
>> + case 0:
>> + return regmap_write(dev->regmap, TIM_CCR1, ccr);
>> + case 1:
>> + return regmap_write(dev->regmap, TIM_CCR2, ccr);
>> + case 2:
>> + return regmap_write(dev->regmap, TIM_CCR3, ccr);
>> + case 3:
>> + return regmap_write(dev->regmap, TIM_CCR4, ccr);
>> + }
>> + return -EINVAL;
>> +}
>> +
>> +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>> + int duty_ns, int period_ns)
>
> Please implement this as an atomic PWM driver, I don't want new drivers
> to use the legacy callbacks.
Ok I will just use .apply ops.
>
>> +{
>> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
>
> I think something like "stm", or "priv" would be more appropriate here.
> If you ever need access to a struct device, you'll be hard-pressed to
> find a good name for it.
I will use priv
>
>> + unsigned long long prd, div, dty;
>> + int prescaler = 0;
>
> If this can never be negative, please make it unsigned int.
>
>> + u32 max_arr = 0xFFFF, ccmr, mask, shift, bdtr;
>> +
>> + if (dev->caps & CAP_32BITS_COUNTER)
>> + max_arr = 0xFFFFFFFF;
>
> I prefer lower-case hexadecimal digits.
I have found a way to remove this code
>
>> +
>> + /* Period and prescaler values depends of clock rate */
>
> "depend on"
fixed
>
>> + div = (unsigned long long)clk_get_rate(dev->clk) * period_ns;
>> +
>> + do_div(div, NSEC_PER_SEC);
>> + prd = div;
>> +
>> + while (div > max_arr) {
>> + prescaler++;
>> + div = prd;
>> + do_div(div, (prescaler + 1));
>> + }
>> + prd = div;
>
> Blank line after blocks, please.
fixed
>
>> +
>> + if (prescaler > MAX_TIM_PSC) {
>> + dev_err(chip->dev, "prescaler exceeds the maximum value\n");
>> + return -EINVAL;
>> + }
>> +
>> + /* All channels share the same prescaler and counter so
>> + * when two channels are active at the same we can't change them
>> + */
>
> This isn't proper block comment style. Also, please use all of the
> columns at your disposal.
done
>
>> + if (__active_channels(dev) & ~(1 << pwm->hwpwm * 4)) {
>> + u32 psc, arr;
>> +
>> + regmap_read(dev->regmap, TIM_PSC, &psc);
>> + regmap_read(dev->regmap, TIM_ARR, &arr);
>> +
>> + if ((psc != prescaler) || (arr != prd - 1))
>> + return -EINVAL;
>
> Maybe -EBUSY to differentiate from other error cases?
done
>
>> + }
>> +
>> + regmap_write(dev->regmap, TIM_PSC, prescaler);
>> + regmap_write(dev->regmap, TIM_ARR, prd - 1);
>> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>> +
>> + /* Calculate the duty cycles */
>> + dty = prd * duty_ns;
>> + do_div(dty, period_ns);
>> +
>> + write_ccrx(dev, pwm, dty);
>> +
>> + /* Configure output mode */
>> + shift = (pwm->hwpwm & 0x1) * 8;
>> + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
>> + mask = 0xFF << shift;
>> +
>> + if (pwm->hwpwm & 0x2)
>
> This looks as though TIM_CCMR1 is used for channels 0 and 1, while
> TIM_CCMR2 is used for channels 2 and 3. Wouldn't it be more natural to
> make the conditional above:
>
> if (pwm->hwpwm >= 2)
>
> ? Or perhaps better yet:
>
> if (pwm->hwpwm < 2)
> /* update TIM_CCMR1 */
> else
> /* update TIM_CCMR2 */
I will code it that, thanks.
>
> The other alternative, which might make the code slightly more readable,
> would be to get rid of all these conditionals by parameterizing the
> offsets per PWM channel. The PWM subsystem has a means of storing per-
> channel chip-specific data (see pwm_{set,get}_chip_data()). It might be
> a little overkill for this particular driver, given that the number of
> conditionals is fairly small.
>
>> + regmap_update_bits(dev->regmap, TIM_CCMR2, mask, ccmr);
>> + else
>> + regmap_update_bits(dev->regmap, TIM_CCMR1, mask, ccmr);
>> +
>> + if (!(dev->caps & CAP_BREAKINPUT))
>> + return 0;
>
> If you make these capabilities boolean, it becomes much more readable,
> especially for negations:
Yes I will fix that
>
> if (!dev->has_breakinput)
>
>> +
>> + bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE;
>> +
>> + if (dev->caps & CAP_BREAKINPUT_POLARITY)
>> + bdtr |= TIM_BDTR_BKE;
>> +
>> + if (dev->polarity)
>> + bdtr |= TIM_BDTR_BKP;
>> +
>> + regmap_update_bits(dev->regmap, TIM_BDTR,
>> + TIM_BDTR_MOE | TIM_BDTR_AOE |
>> + TIM_BDTR_BKP | TIM_BDTR_BKE,
>> + bdtr);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
>> + enum pwm_polarity polarity)
>> +{
>> + u32 mask;
>> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
>> +
>> + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
>> + if (dev->caps & CAP_COMPLEMENTARY)
>> + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(dev->regmap, TIM_CCER, mask,
>> + polarity == PWM_POLARITY_NORMAL ? 0 : mask);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>> +{
>> + u32 mask;
>> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
>> +
>> + clk_enable(dev->clk);
>> +
>> + /* Enable channel */
>> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
>> + if (dev->caps & CAP_COMPLEMENTARY)
>> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(dev->regmap, TIM_CCER, mask, mask);
>> +
>> + /* Make sure that registers are updated */
>> + regmap_update_bits(dev->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>> +
>> + /* Enable controller */
>> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>> +
>> + return 0;
>> +}
>> +
>> +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>> +{
>> + u32 mask;
>> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
>> +
>> + /* Disable channel */
>> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
>> + if (dev->caps & CAP_COMPLEMENTARY)
>> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
>> +
>> + /* When all channels are disabled, we can disable the controller */
>> + if (!__active_channels(dev))
>> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>> +
>> + clk_disable(dev->clk);
>> +}
>
> All of the above can be folded into the ->apply() hook for atomic PWM
> support.
>
> Also, in the above you use clk_enable() in the ->enable() callback and
> clk_disable() in ->disable(). If you need the clock to access registers
> you'll have to enabled it in the others as well because there are no
> guarantees that configuration will only happen between ->enable() and
> ->disable(). Atomic PWM simplifies this a bit, but you still need to be
> careful about when to enable the clock in your ->apply() hook.
I have used regmap functions enable/disable clk for me when accessing to
the registers.
I only have to take care of clk enable/disable when PWM state change.
>
>> +
>> +static const struct pwm_ops stm32pwm_ops = {
>> + .config = stm32_pwm_config,
>> + .set_polarity = stm32_pwm_set_polarity,
>> + .enable = stm32_pwm_enable,
>> + .disable = stm32_pwm_disable,
>> +};
>
> You need to set the .owner field as well.
OK and I will remove legacy ops to use only apply.
>
>> +
>> +static int stm32_pwm_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent);
>> + struct stm32_pwm_dev *pwm;
>> + int ret;
>> +
>> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + pwm->regmap = mfd->regmap;
>> + pwm->clk = mfd->clk;
>> +
>> + if (!pwm->regmap || !pwm->clk)
>> + return -EINVAL;
>> +
>> + if (of_property_read_bool(np, "st,complementary"))
>> + pwm->caps |= CAP_COMPLEMENTARY;
>> +
>> + if (of_property_read_bool(np, "st,32bits-counter"))
>> + pwm->caps |= CAP_32BITS_COUNTER;
>> +
>> + if (of_property_read_bool(np, "st,breakinput"))
>> + pwm->caps |= CAP_BREAKINPUT;
>> +
>> + if (!of_property_read_u32(np, "st,breakinput-polarity", &pwm->polarity))
>> + pwm->caps |= CAP_BREAKINPUT_POLARITY;
>> +
>> + of_property_read_u32(np, "st,pwm-num-chan", &pwm->npwm);
>> +
>> + pwm->chip.base = -1;
>> + pwm->chip.dev = dev;
>> + pwm->chip.ops = &stm32pwm_ops;
>> + pwm->chip.npwm = pwm->npwm;
>> +
>> + ret = pwmchip_add(&pwm->chip);
>> + if (ret < 0)
>> + return ret;
>> +
>> + platform_set_drvdata(pdev, pwm);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_pwm_remove(struct platform_device *pdev)
>> +{
>> + struct stm32_pwm_dev *pwm = platform_get_drvdata(pdev);
>> + int i;
>
> unsigned int, please.
OK
>
>> +
>> + for (i = 0; i < pwm->npwm; i++)
>> + pwm_disable(&pwm->chip.pwms[i]);
>> +
>> + pwmchip_remove(&pwm->chip);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id stm32_pwm_of_match[] = {
>> + {
>> + .compatible = "st,stm32-pwm",
>> + },
>
> The above can be collapsed into a single line.
OK
>
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
>> +
>> +static struct platform_driver stm32_pwm_driver = {
>> + .probe = stm32_pwm_probe,
>> + .remove = stm32_pwm_remove,
>> + .driver = {
>> + .name = DRIVER_NAME,
>> + .of_match_table = stm32_pwm_of_match,
>> + },
>> +};
>
> Please don't use tabs for padding within the structure definition since
> it doesn't align properly anyway.
OK
>
>> +module_platform_driver(stm32_pwm_driver);
>> +
>> +MODULE_ALIAS("platform:" DRIVER_NAME);
>> +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
>> +MODULE_LICENSE("GPL");
>
> According to the header comment this should be "GPL v2".
done
>
> Thanks,
> Thierry
[toc] | [prev] | [next] | [standalone]
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-12-05 12:40 +0100 |
| Subject | Re: [PATCH v3 4/7] PWM: add pwm driver for stm32 plaftorm |
| Message-ID | <sKZMK-3Vo-19@gated-at.bofh.it> |
| In reply to | #1536003 |
[Multipart message — attachments visible in raw view] — view raw
On Mon, Dec 05, 2016 at 12:02:45PM +0100, Benjamin Gaignard wrote:
> 2016-12-05 8:23 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>:
> > On Fri, Dec 02, 2016 at 11:17:19AM +0100, Benjamin Gaignard wrote:
> >> This driver add support for pwm driver on stm32 platform.
> >
> > "adds". Also please use PWM in prose because it's an abbreviation.
> >
> >> The SoC have multiple instances of the hardware IP and each
> >> of them could have small differences: number of channels,
> >> complementary output, counter register size...
> >> Use DT parameters to handle those differentes configuration
> >
> > "different configurations"
>
> ok
>
> >
> >>
> >> version 2:
> >> - only keep one comptatible
> >> - use DT paramaters to discover hardware block configuration
> >
> > "parameters"
>
> ok
>
> >
> >>
> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> >> ---
> >> drivers/pwm/Kconfig | 8 ++
> >> drivers/pwm/Makefile | 1 +
> >> drivers/pwm/pwm-stm32.c | 285 ++++++++++++++++++++++++++++++++++++++++++++++++
> >> 3 files changed, 294 insertions(+)
> >> create mode 100644 drivers/pwm/pwm-stm32.c
> >>
> >> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> >> index bf01288..a89fdba 100644
> >> --- a/drivers/pwm/Kconfig
> >> +++ b/drivers/pwm/Kconfig
> >> @@ -388,6 +388,14 @@ config PWM_STI
> >> To compile this driver as a module, choose M here: the module
> >> will be called pwm-sti.
> >>
> >> +config PWM_STM32
> >> + bool "STMicroelectronics STM32 PWM"
> >> + depends on ARCH_STM32
> >> + depends on OF
> >> + select MFD_STM32_GP_TIMER
> >
> > Should that be a "depends on"?
>
> I think select is fine because the wanted feature is PWM not the mfd part
I think in that case you may want to hide the MFD Kconfig option. See
Documentation/kbuild/kconfig-language.txt (notes about select) for the
details.
[...]
> >> +};
> >> +
> >> +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm_dev, chip)
> >
> > Please turn this into a static inline.
>
> with putting struct pwm_chip as first filed I will just cast the structure
Don't do that, please. container_of() is still preferred because it is
correct and won't break even if you (or somebody else) changes the order
in the future. The fact that it might be optimized away is a detail, or
a micro-optimization. Force-casting is a bad idea because it won't catch
errors if for some reason the field doesn't remain in the first position
forever.
> >> +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> >> +{
> >> + u32 mask;
> >> + struct stm32_pwm_dev *dev = to_stm32_pwm_dev(chip);
> >> +
> >> + /* Disable channel */
> >> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
> >> + if (dev->caps & CAP_COMPLEMENTARY)
> >> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
> >> +
> >> + regmap_update_bits(dev->regmap, TIM_CCER, mask, 0);
> >> +
> >> + /* When all channels are disabled, we can disable the controller */
> >> + if (!__active_channels(dev))
> >> + regmap_update_bits(dev->regmap, TIM_CR1, TIM_CR1_CEN, 0);
> >> +
> >> + clk_disable(dev->clk);
> >> +}
> >
> > All of the above can be folded into the ->apply() hook for atomic PWM
> > support.
> >
> > Also, in the above you use clk_enable() in the ->enable() callback and
> > clk_disable() in ->disable(). If you need the clock to access registers
> > you'll have to enabled it in the others as well because there are no
> > guarantees that configuration will only happen between ->enable() and
> > ->disable(). Atomic PWM simplifies this a bit, but you still need to be
> > careful about when to enable the clock in your ->apply() hook.
>
> I have used regmap functions enable/disable clk for me when accessing to
> the registers.
> I only have to take care of clk enable/disable when PWM state change.
Okay, that's fine then.
Thierry
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-02 11:20 +0100 |
| Subject | [PATCH v3 2/7] MFD: add stm32 general purpose timer driver |
| Message-ID | <sJT6G-2yH-35@gated-at.bofh.it> |
| In reply to | #1534789 |
This hardware block could at used at same time for PWM generation
and IIO timer for other IPs like DAC, ADC or other timers.
PWM and IIO timer configuration are mixed in the same registers
so we need a multi fonction driver to be able to share those registers.
version 2:
- rename driver "stm32-gptimer" to be align with SoC documentation
- only keep one compatible
- use of_platform_populate() instead of devm_mfd_add_devices()
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
drivers/mfd/Kconfig | 10 ++++++
drivers/mfd/Makefile | 2 ++
drivers/mfd/stm32-gptimer.c | 73 +++++++++++++++++++++++++++++++++++++++
include/linux/mfd/stm32-gptimer.h | 62 +++++++++++++++++++++++++++++++++
4 files changed, 147 insertions(+)
create mode 100644 drivers/mfd/stm32-gptimer.c
create mode 100644 include/linux/mfd/stm32-gptimer.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..e75abcb 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1607,6 +1607,15 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_STM32_GP_TIMER
+ tristate "Support for STM32 General Purpose Timer"
+ select MFD_CORE
+ select REGMAP
+ depends on ARCH_STM32
+ depends on OF
+ help
+ Select this option to enable stm32 general purpose timer
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
@@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
on the ARM Ltd. Versatile Express board.
endmenu
+
endif
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..86353b9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
+
+obj-$(CONFIG_MFD_STM32_GP_TIMER) += stm32-gptimer.o
diff --git a/drivers/mfd/stm32-gptimer.c b/drivers/mfd/stm32-gptimer.c
new file mode 100644
index 0000000..54fb95c
--- /dev/null
+++ b/drivers/mfd/stm32-gptimer.c
@@ -0,0 +1,73 @@
+/*
+ * stm32-gptimer.c
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+
+#include <linux/mfd/stm32-gptimer.h>
+
+static const struct regmap_config stm32_gptimer_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = sizeof(u32),
+ .max_register = 0x400,
+ .fast_io = true,
+};
+
+static int stm32_gptimer_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct stm32_gptimer_dev *mfd;
+ struct resource *res;
+ void __iomem *mmio;
+
+ mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
+ if (!mfd)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOMEM;
+
+ mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mmio))
+ return PTR_ERR(mmio);
+
+ mfd->regmap = devm_regmap_init_mmio_clk(dev, "clk_int", mmio,
+ &stm32_gptimer_regmap_cfg);
+ if (IS_ERR(mfd->regmap))
+ return PTR_ERR(mfd->regmap);
+
+ mfd->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(mfd->clk))
+ return PTR_ERR(mfd->clk);
+
+ platform_set_drvdata(pdev, mfd);
+
+ return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+}
+
+static const struct of_device_id stm32_gptimer_of_match[] = {
+ {
+ .compatible = "st,stm32-gptimer",
+ },
+};
+MODULE_DEVICE_TABLE(of, stm32_gptimer_of_match);
+
+static struct platform_driver stm32_gptimer_driver = {
+ .probe = stm32_gptimer_probe,
+ .driver = {
+ .name = "stm32-gptimer",
+ .of_match_table = stm32_gptimer_of_match,
+ },
+};
+module_platform_driver(stm32_gptimer_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics STM32 general purpose timer");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/stm32-gptimer.h b/include/linux/mfd/stm32-gptimer.h
new file mode 100644
index 0000000..f8c92de
--- /dev/null
+++ b/include/linux/mfd/stm32-gptimer.h
@@ -0,0 +1,62 @@
+/*
+ * stm32-gptimer.h
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LINUX_STM32_GPTIMER_H_
+#define _LINUX_STM32_GPTIMER_H_
+
+#include <linux/clk.h>
+#include <linux/regmap.h>
+
+#define TIM_CR1 0x00 /* Control Register 1 */
+#define TIM_CR2 0x04 /* Control Register 2 */
+#define TIM_SMCR 0x08 /* Slave mode control reg */
+#define TIM_DIER 0x0C /* DMA/interrupt register */
+#define TIM_SR 0x10 /* Status register */
+#define TIM_EGR 0x14 /* Event Generation Reg */
+#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
+#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
+#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
+#define TIM_PSC 0x28 /* Prescaler */
+#define TIM_ARR 0x2c /* Auto-Reload Register */
+#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
+#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
+#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
+#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
+#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
+
+#define TIM_CR1_CEN BIT(0) /* Counter Enable */
+#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
+#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
+#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
+#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
+#define TIM_DIER_UIE BIT(0) /* Update interrupt */
+#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
+#define TIM_EGR_UG BIT(0) /* Update Generation */
+#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
+#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
+#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
+#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
+#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
+#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
+#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
+#define TIM_BDTR_BKE BIT(12) /* Break input enable */
+#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
+#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
+#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
+
+#define MAX_TIM_PSC 0xFFFF
+
+struct stm32_gptimer_dev {
+ /* Device data */
+ struct clk *clk;
+
+ /* Registers mapping */
+ struct regmap *regmap;
+};
+
+#endif
--
1.9.1
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-12-02 15:30 +0100 |
| Subject | Re: [PATCH v3 2/7] MFD: add stm32 general purpose timer driver |
| Message-ID | <sJX0B-4ZC-5@gated-at.bofh.it> |
| In reply to | #1534799 |
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
> This hardware block could at used at same time for PWM generation
> and IIO timer for other IPs like DAC, ADC or other timers.
> PWM and IIO timer configuration are mixed in the same registers
> so we need a multi fonction driver to be able to share those registers.
>
> version 2:
> - rename driver "stm32-gptimer" to be align with SoC documentation
> - only keep one compatible
> - use of_platform_populate() instead of devm_mfd_add_devices()
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> drivers/mfd/Kconfig | 10 ++++++
> drivers/mfd/Makefile | 2 ++
> drivers/mfd/stm32-gptimer.c | 73 +++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/stm32-gptimer.h | 62 +++++++++++++++++++++++++++++++++
> 4 files changed, 147 insertions(+)
> create mode 100644 drivers/mfd/stm32-gptimer.c
> create mode 100644 include/linux/mfd/stm32-gptimer.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c6df644..e75abcb 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1607,6 +1607,15 @@ config MFD_STW481X
> in various ST Microelectronics and ST-Ericsson embedded
> Nomadik series.
>
> +config MFD_STM32_GP_TIMER
> + tristate "Support for STM32 General Purpose Timer"
> + select MFD_CORE
> + select REGMAP
> + depends on ARCH_STM32
> + depends on OF
"|| COMPILE_TEST"?
> + help
> + Select this option to enable stm32 general purpose timer
I can see that. Tell us more about the device and what it does.
s/stm32/STM32/
> menu "Multimedia Capabilities Port drivers"
> depends on ARCH_SA1100
>
> @@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
> on the ARM Ltd. Versatile Express board.
>
> endmenu
> +
Please remove this change. It has nothing to do with the set.
> endif
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 9834e66..86353b9 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> +
> +obj-$(CONFIG_MFD_STM32_GP_TIMER) += stm32-gptimer.o
> diff --git a/drivers/mfd/stm32-gptimer.c b/drivers/mfd/stm32-gptimer.c
> new file mode 100644
> index 0000000..54fb95c
> --- /dev/null
> +++ b/drivers/mfd/stm32-gptimer.c
> @@ -0,0 +1,73 @@
> +/*
> + * stm32-gptimer.c
Swap this out for a description.
> + * Copyright (C) STMicroelectronics 2016
'\n'
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/reset.h>
> +
> +#include <linux/mfd/stm32-gptimer.h>
> +
> +static const struct regmap_config stm32_gptimer_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = sizeof(u32),
> + .max_register = 0x400,
> + .fast_io = true,
> +};
> +
> +static int stm32_gptimer_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_gptimer_dev *mfd;
s/mfd/ddata/
> + struct resource *res;
> + void __iomem *mmio;
> +
> + mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
> + if (!mfd)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENOMEM;
> +
Remove this 3 lines.
devm_ioremap_resource() does the checking and error printing for you.
> + mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(mmio))
> + return PTR_ERR(mmio);
> +
> + mfd->regmap = devm_regmap_init_mmio_clk(dev, "clk_int", mmio,
> + &stm32_gptimer_regmap_cfg);
> + if (IS_ERR(mfd->regmap))
> + return PTR_ERR(mfd->regmap);
> +
> + mfd->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(mfd->clk))
> + return PTR_ERR(mfd->clk);
> +
> + platform_set_drvdata(pdev, mfd);
> +
> + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
> +}
> +
> +static const struct of_device_id stm32_gptimer_of_match[] = {
> + {
> + .compatible = "st,stm32-gptimer",
> + },
One line:
{ .compatible = "st,stm32-gptimer" },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_gptimer_of_match);
> +
> +static struct platform_driver stm32_gptimer_driver = {
> + .probe = stm32_gptimer_probe,
> + .driver = {
> + .name = "stm32-gptimer",
> + .of_match_table = stm32_gptimer_of_match,
> + },
Remove tabs before the '='s.
> +module_platform_driver(stm32_gptimer_driver);
> +
> +MODULE_DESCRIPTION("STMicroelectronics STM32 general purpose timer");
"General Purpose Timer"
> +MODULE_LICENSE("GPL");
"GPL v2"
> diff --git a/include/linux/mfd/stm32-gptimer.h b/include/linux/mfd/stm32-gptimer.h
> new file mode 100644
> index 0000000..f8c92de
> --- /dev/null
> +++ b/include/linux/mfd/stm32-gptimer.h
> @@ -0,0 +1,62 @@
> +/*
> + * stm32-gptimer.h
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
Same comments as before.
> +#ifndef _LINUX_STM32_GPTIMER_H_
> +#define _LINUX_STM32_GPTIMER_H_
> +
> +#include <linux/clk.h>
> +#include <linux/regmap.h>
> +
> +#define TIM_CR1 0x00 /* Control Register 1 */
> +#define TIM_CR2 0x04 /* Control Register 2 */
> +#define TIM_SMCR 0x08 /* Slave mode control reg */
> +#define TIM_DIER 0x0C /* DMA/interrupt register */
> +#define TIM_SR 0x10 /* Status register */
> +#define TIM_EGR 0x14 /* Event Generation Reg */
> +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> +#define TIM_PSC 0x28 /* Prescaler */
> +#define TIM_ARR 0x2c /* Auto-Reload Register */
> +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> +
> +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> +#define TIM_EGR_UG BIT(0) /* Update Generation */
> +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
> +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
> +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> +
> +#define MAX_TIM_PSC 0xFFFF
> +
> +struct stm32_gptimer_dev {
Drop the "_dev" or replace with ddata.
> + /* Device data */
No need for this.
> + struct clk *clk;
> +
> + /* Registers mapping */
No need for this.
> + struct regmap *regmap;
> +};
> +
> +#endif
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-12-02 11:20 +0100 |
| Subject | [PATCH v3 1/7] MFD: add bindings for stm32 general purpose timer driver |
| Message-ID | <sJT6G-2yH-39@gated-at.bofh.it> |
| In reply to | #1534789 |
Add bindings information for stm32 general purpose timer
version 2:
- rename stm32-mfd-timer to stm32-gptimer
- only keep one compatible string
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../bindings/mfd/stm32-general-purpose-timer.txt | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
diff --git a/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
new file mode 100644
index 0000000..4fc55d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
@@ -0,0 +1,47 @@
+STM32 general purpose timer driver
+
+Required parameters:
+- compatible: must be "st,stm32-gptimer"
+
+- reg: Physical base address and length of the controller's
+ registers.
+- clock-names: Set to "clk_int".
+- clocks: Phandle to the clock used by the timer module.
+ For Clk properties, please refer to ../clock/clock-bindings.txt
+
+Optional parameters:
+- resets: Phandle to the parent reset controller.
+ See ../reset/st,stm32-rcc.txt
+
+Optional subnodes:
+- pwm: See ../pwm/pwm-stm32.txt
+- timer: See ../iio/timer/stm32-timer-trigger.txt
+
+Example:
+ gptimer1: gptimer1@40010000 {
+ compatible = "st,stm32-gptimer";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+
+ pwm1@0 {
+ compatible = "st,stm32-pwm";
+ st,pwm-num-chan = <4>;
+ st,breakinput;
+ st,complementary;
+ };
+
+ timer1@0 {
+ compatible = "st,stm32-timer-trigger";
+ interrupts = <27>;
+ st,input-triggers-names = TIM5_TRGO,
+ TIM2_TRGO,
+ TIM4_TRGO,
+ TIM3_TRGO;
+ st,output-triggers-names = TIM1_TRGO,
+ TIM1_CH1,
+ TIM1_CH2,
+ TIM1_CH3,
+ TIM1_CH4;
+ };
+ };
--
1.9.1
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| From | Jonathan Cameron <jic23@kernel.org> |
|---|---|
| Date | 2016-12-03 15:50 +0100 |
| Message-ID | <sKjNx-2Bb-43@gated-at.bofh.it> |
| In reply to | #1534789 |
On 02/12/16 10:17, Benjamin Gaignard wrote: > version 3: > - no change on mfd and pwm divers patches > - add cross reference between bindings > - change compatible to "st,stm32-timer-trigger" > - fix attributes access rights > - use string instead of int for master_mode and slave_mode > - document device attributes in sysfs-bus-iio-timer-stm32 > - udpate DT with the new compatible > > version 2: > - keep only one compatible per driver > - use DT parameters to describe hardware block configuration: > - pwm channels, complementary output, counter size, break input > - triggers accepted and create by IIO timers > - change DT to limite use of reference to the node > - interrupt is now in IIO timer driver > - rename stm32-mfd-timer to stm32-gptimer (for general purpose timer) > > The following patches enable pwm and IIO Timer features for stm32 platforms. > > Those two features are mixed into the registers of the same hardware block > (named general purpose timer) which lead to introduce a multifunctions driver > on the top of them to be able to share the registers. > > In stm32 14 instances of timer hardware block exist, even if they all have > the same register mapping they could have a different number of pwm channels > and/or different triggers capabilities. We use various parameters in DT to > describe the differences between hardware blocks > > The MFD (stm32-gptimer.c) takes care of clock and register mapping > by using regmap. stm32_gptimer_dev structure is provided to its sub-node to > share those information. > > PWM driver is implemented into pwm-stm32.c. Depending of the instance we may > have up to 4 channels, sometime with complementary outputs or 32 bits counter > instead of 16 bits. Some hardware blocks may also have a break input function > which allows to stop pwm depending of a level, defined in devicetree, on an > external pin. > > IIO timer driver (stm32-iio-timer.c and stm32-iio-timers.h) define a list of > hardware triggers usable by hardware blocks like ADC, DAC or other timers. > > The matrix of possible connections between blocks is quite complex so we use > trigger names and is_stm32_iio_timer_trigger() function to be sure that > triggers are valid and configure the IPs. > Possible triggers ar listed in include/dt-bindings/iio/timer/st,stm32-iio-timer.h > > At run time IIO timer hardware blocks can configure (through "master_mode" > IIO device attribute) which internal signal (counter enable, reset, > comparison block, etc...) is used to generate the trigger. > > By using "slave_mode" IIO device attribute timer can also configure on which > event (level, rising edge) of the block is enabled. > > Since we can use trigger from one hardware to control an other block, we can > use a pwm to control an other one. The following example shows how to configure > pwm1 and pwm3 to make pwm3 generate pulse only when pwm1 pulse level is high. > > /sys/bus/iio/devices # ls > iio:device0 iio:device1 trigger0 trigger1 > > configure timer1 to use pwm1 channel 0 as output trigger > /sys/bus/iio/devices # echo 'OC1REF' > iio\:device0/master_mode > configure timer3 to enable only when input is high > /sys/bus/iio/devices # echo 'gated' > iio\:device1/slave_mode > /sys/bus/iio/devices # cat trigger0/name > tim1_trgo > configure timer2 to use timer1 trigger is input > /sys/bus/iio/devices # echo "tim1_trgo" > iio\:device1/trigger/current_trigger > > configure pwm3 channel 0 to generate a signal with a period of 100ms and a > duty cycle of 50% > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 0 > export > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 100000000 > pwm0/period > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 50000000 > pwm0/duty_cycle > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4# echo 1 > pwm0/enable > here pwm3 channel 0, as expected, doesn't start because has to be triggered by > pwm1 channel 0 > > configure pwm1 channel 0 to generate a signal with a period of 1s and a > duty cycle of 50% > /sys/devices/platform/soc/40010000.gptimer1/40010000.gptimer1:pwm1@0/pwm/pwmchip0 # echo 0 > export > /sys/devices/platform/soc/40010000.gptimer1/40010000.gptimer1:pwm1@0/pwm/pwmchip0 # echo 1000000000 > pwm0/period > /sys/devices/platform/soc/40010000.gptimer1/40010000.gptimer1:pwm1@0/pwm/pwmchip0 # echo 500000000 > pwm0/duty_cycle > /sys/devices/platform/soc/40010000.gptimer1/40010000.gptimer1:pwm1@0/pwm/pwmchip0 # echo 1 > pwm0/enable > finally pwm1 starts and pwm3 only generates pulse when pwm1 signal is high > > An other example to use a timer as source of clock for another device. > Here timer1 is used a source clock for pwm3: > > /sys/bus/iio/devices # echo 100000 > trigger0/sampling_frequency > /sys/bus/iio/devices # echo tim1_trgo > iio\:device1/trigger/current_trigger > /sys/bus/iio/devices # echo 'external_clock' > iio\:device1/slave_mode > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 0 > export > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 1000000 > pwm0/period > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 500000 > pwm0/duty_cycle > /sys/devices/platform/soc/40000400.gptimer3/40000400.gptimer3:pwm3@0/pwm/pwmchip4 # echo 1 > pwm0/enable This is good thorough documentation. Could we have an additional patch adding just this documentation to the tree (probably under Documentation/mfd?). Documentation in general is a bit in flux at the moment so we'll may want to sphixify it afterwards but plain text is fine for now. Jonathan > > Benjamin Gaignard (7): > MFD: add bindings for stm32 general purpose timer driver > MFD: add stm32 general purpose timer driver > PWM: add pwm-stm32 DT bindings > PWM: add pwm driver for stm32 plaftorm > IIO: add bindings for stm32 timer trigger driver > IIO: add STM32 timer trigger driver > ARM: dts: stm32: add stm32 general purpose timer driver in DT > > .../ABI/testing/sysfs-bus-iio-timer-stm32 | 47 ++ > .../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++ > .../bindings/mfd/stm32-general-purpose-timer.txt | 47 ++ > .../devicetree/bindings/pwm/pwm-stm32.txt | 38 ++ > arch/arm/boot/dts/stm32f429.dtsi | 333 +++++++++++++- > arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ > drivers/iio/Kconfig | 2 +- > drivers/iio/Makefile | 1 + > drivers/iio/timer/Kconfig | 15 + > drivers/iio/timer/Makefile | 1 + > drivers/iio/timer/stm32-timer-trigger.c | 477 +++++++++++++++++++++ > drivers/iio/trigger/Kconfig | 1 - > drivers/mfd/Kconfig | 10 + > drivers/mfd/Makefile | 2 + > drivers/mfd/stm32-gptimer.c | 73 ++++ > drivers/pwm/Kconfig | 8 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-stm32.c | 285 ++++++++++++ > .../iio/timer/st,stm32-timer-triggers.h | 60 +++ > include/linux/iio/timer/stm32-timer-trigger.h | 16 + > include/linux/mfd/stm32-gptimer.h | 62 +++ > 21 files changed, 1543 insertions(+), 3 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 > create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt > create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt > create mode 100644 drivers/iio/timer/Kconfig > create mode 100644 drivers/iio/timer/Makefile > create mode 100644 drivers/iio/timer/stm32-timer-trigger.c > create mode 100644 drivers/mfd/stm32-gptimer.c > create mode 100644 drivers/pwm/pwm-stm32.c > create mode 100644 include/dt-bindings/iio/timer/st,stm32-timer-triggers.h > create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h > create mode 100644 include/linux/mfd/stm32-gptimer.h >
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