Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1531322 > unrolled thread
| Started by | Zumeng Chen <zumeng.chen@windriver.com> |
|---|---|
| First post | 2016-11-28 15:00 +0100 |
| Last post | 2016-11-30 02:40 +0100 |
| Articles | 3 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen <zumeng.chen@windriver.com> - 2016-11-28 15:00 +0100
Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly Nicolas Ferre <nicolas.ferre@atmel.com> - 2016-11-28 15:10 +0100
Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly David Miller <davem@davemloft.net> - 2016-11-30 02:40 +0100
| From | Zumeng Chen <zumeng.chen@windriver.com> |
|---|---|
| Date | 2016-11-28 15:00 +0100 |
| Subject | [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sIuDo-2Mu-23@gated-at.bofh.it> |
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:
<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>
There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
---
V2 changes:
Add the same wmb for at91ether as well based on reviewer's suggestion.
Cheers,
drivers/net/ethernet/cadence/macb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..6d7cfa7 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
if (status & MACB_BIT(RXUBR)) {
ctrl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+ wmb();
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
@@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
if (intstatus & MACB_BIT(RXUBR)) {
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
+ wmb();
macb_writel(lp, NCR, ctl | MACB_BIT(RE));
}
--
2.4.11
[toc] | [next] | [standalone]
| From | Nicolas Ferre <nicolas.ferre@atmel.com> |
|---|---|
| Date | 2016-11-28 15:10 +0100 |
| Subject | Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sIuN3-36B-5@gated-at.bofh.it> |
| In reply to | #1531322 |
Le 28/11/2016 à 14:55, Zumeng Chen a écrit :
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Thanks, best regards,
> ---
>
> V2 changes:
>
> Add the same wmb for at91ether as well based on reviewer's suggestion.
>
> Cheers,
> drivers/net/ethernet/cadence/macb.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 533653b..6d7cfa7 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> if (status & MACB_BIT(RXUBR)) {
> ctrl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> @@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
> if (intstatus & MACB_BIT(RXUBR)) {
> ctl = macb_readl(lp, NCR);
> macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(lp, NCR, ctl | MACB_BIT(RE));
> }
>
>
--
Nicolas Ferre
[toc] | [prev] | [next] | [standalone]
| From | David Miller <davem@davemloft.net> |
|---|---|
| Date | 2016-11-30 02:40 +0100 |
| Subject | Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sJ22m-7Nz-17@gated-at.bofh.it> |
| In reply to | #1531322 |
From: Zumeng Chen <zumeng.chen@windriver.com> Date: Mon, 28 Nov 2016 21:55:00 +0800 > When a hardware issue happened as described by inline comments, the register > write pattern looks like the following: > > <write ~MACB_BIT(RE)> > + wmb(); > <write MACB_BIT(RE)> > > There might be a memory barrier between these two write operations, so add wmb > to ensure an flip from 0 to 1 for NCR. > > Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com> > --- > > V2 changes: > > Add the same wmb for at91ether as well based on reviewer's suggestion. Applied, thanks.
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web