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Groups > linux.kernel > #1527799 > unrolled thread
| Started by | "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> |
|---|---|
| First post | 2016-11-22 19:10 +0100 |
| Last post | 2016-11-23 01:40 +0100 |
| Articles | 4 — 3 participants |
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[PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> - 2016-11-22 19:10 +0100
Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online Michael Ellerman <mpe@ellerman.id.au> - 2016-11-23 00:40 +0100
Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online Michael Neuling <mikey@neuling.org> - 2016-11-23 00:40 +0100
Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online Michael Neuling <mikey@neuling.org> - 2016-11-23 01:40 +0100
| From | "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> |
|---|---|
| Date | 2016-11-22 19:10 +0100 |
| Subject | [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online |
| Message-ID | <sGnG2-2it-9@gated-at.bofh.it> |
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> Ensure that PSSCR is set to a safe value corresponding to no state-loss each time a POWER9 CPU comes online. Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> --- arch/powerpc/kernel/cpu_setup_power.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 52ff3f0..37ad045 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -96,6 +96,7 @@ _GLOBAL(__setup_cpu_power9) mtlr r11 beqlr li r0,0 + mtspr SPRN_PSSCR,r0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR ori r3, r3, LPCR_PECEDH @@ -116,6 +117,7 @@ _GLOBAL(__restore_cpu_power9) mtlr r11 beqlr li r0,0 + mtspr SPRN_PSSCR,r0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR ori r3, r3, LPCR_PECEDH -- 1.9.4
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| From | Michael Ellerman <mpe@ellerman.id.au> |
|---|---|
| Date | 2016-11-23 00:40 +0100 |
| Message-ID | <sGsPn-5rk-3@gated-at.bofh.it> |
| In reply to | #1527799 |
"Gautham R. Shenoy" <ego@linux.vnet.ibm.com> writes: > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > Ensure that PSSCR is set to a safe value corresponding to no > state-loss each time a POWER9 CPU comes online. Is this a bug fix? I can't tell from the change log. cheers
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| From | Michael Neuling <mikey@neuling.org> |
|---|---|
| Date | 2016-11-23 00:40 +0100 |
| Message-ID | <sGsPo-5rk-11@gated-at.bofh.it> |
| In reply to | #1528025 |
On Wed, 2016-11-23 at 10:30 +1100, Michael Ellerman wrote: > "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> writes: > > > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > > > Ensure that PSSCR is set to a safe value corresponding to no > > state-loss each time a POWER9 CPU comes online. > > Is this a bug fix? I can't tell from the change log. There are no known bugs it's fixing. It's just safer to run with a known default value, rather than what we randomly inherit from previous firmware. Mikey
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| From | Michael Neuling <mikey@neuling.org> |
|---|---|
| Date | 2016-11-23 01:40 +0100 |
| Message-ID | <sGtLs-63s-21@gated-at.bofh.it> |
| In reply to | #1527799 |
On Tue, 2016-11-22 at 23:36 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > Ensure that PSSCR is set to a safe value corresponding to no > state-loss each time a POWER9 CPU comes online. > > Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Tested here on my configuration... FWIW Acked-By: Michael Neuling <mikey@neuling.org> > --- > arch/powerpc/kernel/cpu_setup_power.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/kernel/cpu_setup_power.S > b/arch/powerpc/kernel/cpu_setup_power.S > index 52ff3f0..37ad045 100644 > --- a/arch/powerpc/kernel/cpu_setup_power.S > +++ b/arch/powerpc/kernel/cpu_setup_power.S > @@ -96,6 +96,7 @@ _GLOBAL(__setup_cpu_power9) > mtlr r11 > beqlr > li r0,0 > + mtspr SPRN_PSSCR,r0 > mtspr SPRN_LPID,r0 > mfspr r3,SPRN_LPCR > ori r3, r3, LPCR_PECEDH > @@ -116,6 +117,7 @@ _GLOBAL(__restore_cpu_power9) > mtlr r11 > beqlr > li r0,0 > + mtspr SPRN_PSSCR,r0 > mtspr SPRN_LPID,r0 > mfspr r3,SPRN_LPCR > ori r3, r3, LPCR_PECEDH
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