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Groups > linux.kernel > #1527652 > unrolled thread
| Started by | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| First post | 2016-11-22 17:20 +0100 |
| Last post | 2016-11-22 17:30 +0100 |
| Articles | 15 — 4 participants |
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[PATCH 0/7] Add pwm and IIO timer drivers for stm32 Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:20 +0100
[PATCH 5/7] add bindings for stm32 IIO timer drivers Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:20 +0100
Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers Lars-Peter Clausen <lars@metafoo.de> - 2016-11-22 18:00 +0100
Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers Lars-Peter Clausen <lars@metafoo.de> - 2016-11-22 18:10 +0100
Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 18:10 +0100
Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers Lee Jones <lee.jones@linaro.org> - 2016-11-22 18:20 +0100
Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-23 09:20 +0100
Re: [PATCH 2/7] add MFD for stm32 timer IP Lee Jones <lee.jones@linaro.org> - 2016-11-22 17:30 +0100
Re: [PATCH 2/7] add MFD for stm32 timer IP Lee Jones <lee.jones@linaro.org> - 2016-11-22 17:40 +0100
Re: [PATCH 2/7] add MFD for stm32 timer IP Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:50 +0100
[PATCH 3/7] add pwm-stm32 DT bindings Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:30 +0100
[PATCH 7/7] add stm32 multi-functions timer driver in DT Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:30 +0100
Re: [PATCH 7/7] add stm32 multi-functions timer driver in DT Alexandre Torgue <alexandre.torgue@st.com> - 2016-11-22 18:10 +0100
Re: [PATCH 7/7] add stm32 multi-functions timer driver in DT Lee Jones <lee.jones@linaro.org> - 2016-11-23 11:00 +0100
[PATCH 2/7] add MFD for stm32 timer IP Benjamin Gaignard <benjamin.gaignard@linaro.org> - 2016-11-22 17:30 +0100
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:20 +0100 |
| Subject | [PATCH 0/7] Add pwm and IIO timer drivers for stm32 |
| Message-ID | <sGlXz-18B-3@gated-at.bofh.it> |
The following patches enable pwm and IIO Timer features for stm32 platforms. Those two features are mixed into the registers of the same hardware block (named timer) which lead to introduce a multifunctions driver on the top to be able to share the registers. In stm32 14 instances of timer hardware block exist, even if they all have the same register mapping they could have a different number of pwm channels and/or different triggers capabilities. To keep the code as simple as possible we use compatible and platform_data to distinguish them. The MFD (stm32-mfd-timer.c) takes care of clock, interrupt and register mapping by using regmap. stm32_mfd_timer_dev structure is provided to its children to share those information. PWM driver is implemented into pwm-stm32.c. Depending of the instance we may have up to 4 channels, sometime with complementary outputs or 32 bits counter instead of 16 bits. Some hardware blocks may also have a break input function which allows to stop pwm depending of a level, defined in devicetree, on an external pin. IIO timer driver (stm32-iio-timer.c and stm32-iio-timers.h) define a list of hardware triggers usable by hardware blocks like ADC, DAC or other timers. The matrix of possible connections between blocks is quite complex so we use trigger names and is_stm32_iio_timer_trigger() function to be sure that triggers are valid and configure the IPs. Timer hardware blocks can configure (through "master_mode" IIO device attribute) which internal signal (counter enable, reset, comparison block, etc...) is used to generate the trigger. By using "slave_mode" IIO device attribute timer can also configure on which event (level, rising edge) of the block is enabled. Since we can use trigger from one hardware to control an other block, we can use a pwm to control an other one. The following example shows how to configure pwm1 and pwm3 to make pwm3 generate pulse only when pwm1 pulse level is high. /sys/bus/iio/devices # ls iio:device0 iio:device1 trigger0 trigger1 configure timer1 to use pwm1 channel 0 as output trigger /sys/bus/iio/devices # echo 4 > iio\:device0/master_mode configure timer3 to enable only when input is high /sys/bus/iio/devices # echo 5 > iio\:device1/slave_mode /sys/bus/iio/devices # cat trigger0/name tim1_trgo configure timer2 to use timer1 trigger is input /sys/bus/iio/devices # echo "tim1_trgo" > iio\:device1/trigger/current_trigger configure pwm3 channel 0 to generate a signal with a period of 100ms and a duty cycle of 50% /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 0 > export /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 100000000 > pwm0/period /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 50000000 > pwm0/duty_cycle /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1 > pwm0/enable here pwm3 channel 0, as expected, doesn't start because has to be triggered by pwm1 channel 0 configure pwm1 channel 0 to generate a signal with a period of 1s and a duty cycle of 50% /sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 0 > export /sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 1000000000 > pwm0/period /sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 500000000 > pwm0/duty_cycle /sys/devices/platform/soc/40010000.mfdtimer1/pwm1/pwm/pwmchip0 # echo 1 > pwm0/enable finally pwm1 starts and pwm3 only generates pulse when pwm1 signal is high An other example to use a timer as source of clock for another device. Here timer1 is used a source clock for pwm3: /sys/bus/iio/devices # echo 100000 > trigger0/sampling_frequency /sys/bus/iio/devices # echo tim1_trgo > iio\:device1/trigger/current_trigger /sys/bus/iio/devices # echo 7 > iio\:device1/slave_mode /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 0 > export /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1000000 > pwm0/period /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 500000 > pwm0/duty_cycle /sys/devices/platform/soc/40000400.mfdtimer3/pwm3/pwm/pwmchip4 # echo 1 > pwm0/enable Benjamin Gaignard (7): add binding for stm32 multifunctions timer driver add MFD for stm32 timer IP add pwm-stm32 DT bindings add pwm driver for stm32 plaftorm add bindings for stm32 IIO timer drivers add STM32 IIO timer driver add stm32 multi-functions timer driver in DT .../bindings/iio/timer/stm32-iio-timer.txt | 33 + .../devicetree/bindings/mfd/stm32-timer.txt | 53 ++ .../devicetree/bindings/pwm/pwm-stm32.txt | 43 ++ arch/arm/boot/dts/stm32f429.dtsi | 246 +++++++ arch/arm/boot/dts/stm32f469-disco.dts | 29 + drivers/iio/Kconfig | 2 +- drivers/iio/Makefile | 1 + drivers/iio/timer/Kconfig | 15 + drivers/iio/timer/Makefile | 1 + drivers/iio/timer/stm32-iio-timer.c | 766 +++++++++++++++++++++ drivers/iio/trigger/Kconfig | 1 - drivers/mfd/Kconfig | 10 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-mfd-timer.c | 236 +++++++ drivers/pwm/Kconfig | 8 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 358 ++++++++++ include/linux/iio/timer/stm32-iio-timers.h | 25 + include/linux/mfd/stm32-mfd-timer.h | 78 +++ 19 files changed, 1906 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/timer/Kconfig create mode 100644 drivers/iio/timer/Makefile create mode 100644 drivers/iio/timer/stm32-iio-timer.c create mode 100644 drivers/mfd/stm32-mfd-timer.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-iio-timers.h create mode 100644 include/linux/mfd/stm32-mfd-timer.h -- 1.9.1
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:20 +0100 |
| Subject | [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGlXA-18B-31@gated-at.bofh.it> |
| In reply to | #1527652 |
Define bindings for stm32 IIO timer
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../bindings/iio/timer/stm32-iio-timer.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
new file mode 100644
index 0000000..b80025e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
@@ -0,0 +1,33 @@
+timer IIO trigger bindings for STM32
+
+Must be a child of STM32 multifunctions timer driver
+
+Required parameters:
+- compatible: must be one of the follow value:
+ "st,stm32-iio-timer1"
+ "st,stm32-iio-timer2"
+ "st,stm32-iio-timer3"
+ "st,stm32-iio-timer4"
+ "st,stm32-iio-timer5"
+ "st,stm32-iio-timer6"
+ "st,stm32-iio-timer7"
+ "st,stm32-iio-timer8"
+ "st,stm32-iio-timer9"
+ "st,stm32-iio-timer10"
+ "st,stm32-iio-timer11"
+ "st,stm32-iio-timer12"
+ "st,stm32-iio-timer13"
+ "st,stm32-iio-timer14"
+
+Example:
+ mfd_timer1: mfdtimer1@40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+
+ trigger1: trigger1@40010000 {
+ compatible = "st,stm32-iio-timer1";
+ };
+ };
--
1.9.1
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| From | Lars-Peter Clausen <lars@metafoo.de> |
|---|---|
| Date | 2016-11-22 18:00 +0100 |
| Subject | Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGmAn-1lo-17@gated-at.bofh.it> |
| In reply to | #1527656 |
On 11/22/2016 05:13 PM, Benjamin Gaignard wrote: > Define bindings for stm32 IIO timer > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> > --- > .../bindings/iio/timer/stm32-iio-timer.txt | 33 ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt > > diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt > new file mode 100644 > index 0000000..b80025e > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt > @@ -0,0 +1,33 @@ > +timer IIO trigger bindings for STM32 > + > +Must be a child of STM32 multifunctions timer driver > + > +Required parameters: > +- compatible: must be one of the follow value: > + "st,stm32-iio-timer1" > + "st,stm32-iio-timer2" > + "st,stm32-iio-timer3" > + "st,stm32-iio-timer4" > + "st,stm32-iio-timer5" > + "st,stm32-iio-timer6" > + "st,stm32-iio-timer7" > + "st,stm32-iio-timer8" > + "st,stm32-iio-timer9" > + "st,stm32-iio-timer10" > + "st,stm32-iio-timer11" > + "st,stm32-iio-timer12" > + "st,stm32-iio-timer13" > + "st,stm32-iio-timer14" We can't do this. This is a binding for a driver, not for the hardware.
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| From | Lars-Peter Clausen <lars@metafoo.de> |
|---|---|
| Date | 2016-11-22 18:10 +0100 |
| Subject | Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGmJX-1DN-1@gated-at.bofh.it> |
| In reply to | #1527698 |
On 11/22/2016 06:01 PM, Benjamin Gaignard wrote: > [snip] >>> + "st,stm32-iio-timer5" >>> + "st,stm32-iio-timer6" >>> + "st,stm32-iio-timer7" >>> + "st,stm32-iio-timer8" >>> + "st,stm32-iio-timer9" >>> + "st,stm32-iio-timer10" >>> + "st,stm32-iio-timer11" >>> + "st,stm32-iio-timer12" >>> + "st,stm32-iio-timer13" >>> + "st,stm32-iio-timer14" >> >> We can't do this. This is a binding for a driver, not for the hardware. >> > > Unfortunately each instance for the hardware IP have little > differences like which triggers they could accept or size of the > counter register, > and I doesn't have value inside the hardware to distinguish them so > the only way I found is to use compatible. But IIO is not a piece of hardware, its a software framework in the Linux kernel.
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 18:10 +0100 |
| Subject | Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGmJX-1DN-3@gated-at.bofh.it> |
| In reply to | #1527698 |
[snip] >> + "st,stm32-iio-timer5" >> + "st,stm32-iio-timer6" >> + "st,stm32-iio-timer7" >> + "st,stm32-iio-timer8" >> + "st,stm32-iio-timer9" >> + "st,stm32-iio-timer10" >> + "st,stm32-iio-timer11" >> + "st,stm32-iio-timer12" >> + "st,stm32-iio-timer13" >> + "st,stm32-iio-timer14" > > We can't do this. This is a binding for a driver, not for the hardware. > Unfortunately each instance for the hardware IP have little differences like which triggers they could accept or size of the counter register, and I doesn't have value inside the hardware to distinguish them so the only way I found is to use compatible.
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-11-22 18:20 +0100 |
| Subject | Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGmTD-1H7-37@gated-at.bofh.it> |
| In reply to | #1527713 |
On Tue, 22 Nov 2016, Benjamin Gaignard wrote: > [snip] > >> + "st,stm32-iio-timer5" > >> + "st,stm32-iio-timer6" > >> + "st,stm32-iio-timer7" > >> + "st,stm32-iio-timer8" > >> + "st,stm32-iio-timer9" > >> + "st,stm32-iio-timer10" > >> + "st,stm32-iio-timer11" > >> + "st,stm32-iio-timer12" > >> + "st,stm32-iio-timer13" > >> + "st,stm32-iio-timer14" > > > > We can't do this. This is a binding for a driver, not for the hardware. > > > > Unfortunately each instance for the hardware IP have little > differences like which triggers they could accept or size of the > counter register, > and I doesn't have value inside the hardware to distinguish them so > the only way I found is to use compatible. Can't you represent these as properties? -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-23 09:20 +0100 |
| Subject | Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers |
| Message-ID | <sGAWB-2ox-3@gated-at.bofh.it> |
| In reply to | #1527726 |
If it is ok for you I will add "id" parameter in mfd driver and forward it to the sub-devices drivers to be able to distinguish the hardware blocks 2016-11-22 18:18 GMT+01:00 Lee Jones <lee.jones@linaro.org>: > On Tue, 22 Nov 2016, Benjamin Gaignard wrote: > >> [snip] >> >> + "st,stm32-iio-timer5" >> >> + "st,stm32-iio-timer6" >> >> + "st,stm32-iio-timer7" >> >> + "st,stm32-iio-timer8" >> >> + "st,stm32-iio-timer9" >> >> + "st,stm32-iio-timer10" >> >> + "st,stm32-iio-timer11" >> >> + "st,stm32-iio-timer12" >> >> + "st,stm32-iio-timer13" >> >> + "st,stm32-iio-timer14" >> > >> > We can't do this. This is a binding for a driver, not for the hardware. >> > >> >> Unfortunately each instance for the hardware IP have little >> differences like which triggers they could accept or size of the >> counter register, >> and I doesn't have value inside the hardware to distinguish them so >> the only way I found is to use compatible. > > Can't you represent these as properties? > > -- > Lee Jones > Linaro STMicroelectronics Landing Team Lead > Linaro.org │ Open source software for ARM SoCs > Follow Linaro: Facebook | Twitter | Blog -- Benjamin Gaignard Graphic Study Group Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-11-22 17:30 +0100 |
| Subject | Re: [PATCH 2/7] add MFD for stm32 timer IP |
| Message-ID | <sGm7g-1bI-13@gated-at.bofh.it> |
| In reply to | #1527652 |
On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
> This hardware block could at used at same time for PWM generation
> and IIO timer for other IPs like DAC, ADC or other timers.
> PWM and IIO timer configuration are mixed in the same registers
> so we need a MFD to be able to share those registers.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> drivers/mfd/Kconfig | 10 ++
> drivers/mfd/Makefile | 2 +
> drivers/mfd/stm32-mfd-timer.c | 236 ++++++++++++++++++++++++++++++++++++
> include/linux/mfd/stm32-mfd-timer.h | 78 ++++++++++++
> 4 files changed, 326 insertions(+)
> create mode 100644 drivers/mfd/stm32-mfd-timer.c
> create mode 100644 include/linux/mfd/stm32-mfd-timer.h
This driver is going to need a re-write.
However, it's difficult to provide suggestions, since I've been left
off of the Cc: list for all the other patches.
Please re-send the set with all of the Maintainers Cc'ed on all of
the patches.
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c6df644..63aee36 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1607,6 +1607,15 @@ config MFD_STW481X
> in various ST Microelectronics and ST-Ericsson embedded
> Nomadik series.
>
> +config MFD_STM32_TIMER
> + tristate "Support for STM32 multifunctions timer"
> + select MFD_CORE
> + select REGMAP
> + depends on ARCH_STM32
> + depends on OF
> + help
> + Select multifunction driver (pwm, IIO trigger) for stm32 timers
> +
> menu "Multimedia Capabilities Port drivers"
> depends on ARCH_SA1100
>
> @@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
> on the ARM Ltd. Versatile Express board.
>
> endmenu
> +
> endif
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 9834e66..b348c3e 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> +
> +obj-$(CONFIG_MFD_STM32_TIMER) += stm32-mfd-timer.o
> diff --git a/drivers/mfd/stm32-mfd-timer.c b/drivers/mfd/stm32-mfd-timer.c
> new file mode 100644
> index 0000000..67e7db3
> --- /dev/null
> +++ b/drivers/mfd/stm32-mfd-timer.c
> @@ -0,0 +1,236 @@
> +/*
> + * stm32-timer.c
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include <linux/mfd/stm32-mfd-timer.h>
> +
> +static const struct stm32_mfd_timer_cfg mfd_cells_cfg[] = {
> + {
> + .pwm_name = "pwm1",
> + .pwm_compatible = "st,stm32-pwm1",
> + .trigger_name = "iiotimer1",
> + .trigger_compatible = "st,stm32-iio-timer1",
> + },
> + {
> + .pwm_name = "pwm2",
> + .pwm_compatible = "st,stm32-pwm2",
> + .trigger_name = "iiotimer2",
> + .trigger_compatible = "st,stm32-iio-timer2",
> + },
> + {
> + .pwm_name = "pwm3",
> + .pwm_compatible = "st,stm32-pwm3",
> + .trigger_name = "iiotimer3",
> + .trigger_compatible = "st,stm32-iio-timer3",
> + },
> + {
> + .pwm_name = "pwm4",
> + .pwm_compatible = "st,stm32-pwm4",
> + .trigger_name = "iiotimer4",
> + .trigger_compatible = "st,stm32-iio-timer4",
> + },
> + {
> + .pwm_name = "pwm5",
> + .pwm_compatible = "st,stm32-pwm5",
> + .trigger_name = "iiotimer5",
> + .trigger_compatible = "st,stm32-iio-timer5",
> + },
> + {
> + .trigger_name = "iiotimer6",
> + .trigger_compatible = "st,stm32-iio-timer6",
> + },
> + {
> + .trigger_name = "iiotimer7",
> + .trigger_compatible = "st,stm32-iio-timer7",
> + },
> + {
> + .pwm_name = "pwm8",
> + .pwm_compatible = "st,stm32-pwm8",
> + .trigger_name = "iiotimer8",
> + .trigger_compatible = "st,stm32-iio-timer8",
> + },
> + {
> + .pwm_name = "pwm9",
> + .pwm_compatible = "st,stm32-pwm9",
> + .trigger_name = "iiotimer9",
> + .trigger_compatible = "st,stm32-iio-timer9",
> + },
> + {
> + .pwm_name = "pwm10",
> + .pwm_compatible = "st,stm32-pwm10",
> + },
> + {
> + .pwm_name = "pwm11",
> + .pwm_compatible = "st,stm32-pwm11",
> + },
> + {
> + .pwm_name = "pwm12",
> + .pwm_compatible = "st,stm32-pwm12",
> + .trigger_name = "iiotimer12",
> + .trigger_compatible = "st,stm32-iio-timer12",
> + },
> + {
> + .pwm_name = "pwm13",
> + .pwm_compatible = "st,stm32-pwm13",
> + },
> + {
> + .pwm_name = "pwm14",
> + .pwm_compatible = "st,stm32-pwm14",
> + },
> +};
> +
> +static const struct of_device_id stm32_timer_of_match[] = {
> + {
> + .compatible = "st,stm32-mfd-timer1",
> + .data = &mfd_cells_cfg[0],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer2",
> + .data = &mfd_cells_cfg[1],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer3",
> + .data = &mfd_cells_cfg[2],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer4",
> + .data = &mfd_cells_cfg[3],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer5",
> + .data = &mfd_cells_cfg[4],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer6",
> + .data = &mfd_cells_cfg[5],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer7",
> + .data = &mfd_cells_cfg[6],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer8",
> + .data = &mfd_cells_cfg[7],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer9",
> + .data = &mfd_cells_cfg[8],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer10",
> + .data = &mfd_cells_cfg[9],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer11",
> + .data = &mfd_cells_cfg[10],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer12",
> + .data = &mfd_cells_cfg[11],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer13",
> + .data = &mfd_cells_cfg[12],
> + },
> + {
> + .compatible = "st,stm32-mfd-timer14",
> + .data = &mfd_cells_cfg[13],
> + },
> +};
> +
> +static const struct regmap_config stm32_timer_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = sizeof(u32),
> + .max_register = 0x400,
> + .fast_io = true,
> +};
> +
> +static int stm32_mfd_timer_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct stm32_mfd_timer_dev *mfd;
> + struct resource *res;
> + int ret, nb_cells = 0;
> + struct mfd_cell *cell = NULL;
> + void __iomem *mmio;
> +
> + mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
> + if (!mfd)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENOMEM;
> +
> + mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(mmio))
> + return PTR_ERR(mmio);
> +
> + mfd->regmap = devm_regmap_init_mmio_clk(dev, "mfd_timer_clk", mmio,
> + &stm32_timer_regmap_cfg);
> + if (IS_ERR(mfd->regmap))
> + return PTR_ERR(mfd->regmap);
> +
> + mfd->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(mfd->clk))
> + return PTR_ERR(mfd->clk);
> +
> + mfd->irq = platform_get_irq(pdev, 0);
> + if (mfd->irq < 0)
> + return -EINVAL;
> +
> + /* populate data structure depending on compatibility */
> + if (!of_match_node(stm32_timer_of_match, np)->data)
> + return -EINVAL;
> +
> + mfd->cfg =
> + (struct stm32_mfd_timer_cfg *)of_match_node(stm32_timer_of_match, np)->data;
> +
> + if (mfd->cfg->pwm_name && mfd->cfg->pwm_compatible) {
> + cell = &mfd->cells[nb_cells++];
> + cell->name = mfd->cfg->pwm_name;
> + cell->of_compatible = mfd->cfg->pwm_compatible;
> + cell->platform_data = mfd;
> + cell->pdata_size = sizeof(*mfd);
> + }
> +
> + if (mfd->cfg->trigger_name && mfd->cfg->trigger_compatible) {
> + cell = &mfd->cells[nb_cells++];
> + cell->name = mfd->cfg->trigger_name;
> + cell->of_compatible = mfd->cfg->trigger_compatible;
> + cell->platform_data = mfd;
> + cell->pdata_size = sizeof(*mfd);
> + }
> +
> + ret = devm_mfd_add_devices(&pdev->dev, pdev->id, mfd->cells,
> + nb_cells, NULL, 0, NULL);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, mfd);
> +
> + return 0;
> +}
> +
> +static struct platform_driver stm32_mfd_timer_driver = {
> + .probe = stm32_mfd_timer_probe,
> + .driver = {
> + .name = "stm32-mfd-timer",
> + .of_match_table = stm32_timer_of_match,
> + },
> +};
> +module_platform_driver(stm32_mfd_timer_driver);
> +
> +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer MFD");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/mfd/stm32-mfd-timer.h b/include/linux/mfd/stm32-mfd-timer.h
> new file mode 100644
> index 0000000..4a79c22
> --- /dev/null
> +++ b/include/linux/mfd/stm32-mfd-timer.h
> @@ -0,0 +1,78 @@
> +/*
> + * stm32-mfd-timer.h
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _LINUX_MFD_STM32_TIMER_H_
> +#define _LINUX_MFD_STM32_TIMER_H_
> +
> +#include <linux/clk.h>
> +#include <linux/mfd/core.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#define TIM_CR1 0x00 /* Control Register 1 */
> +#define TIM_CR2 0x04 /* Control Register 2 */
> +#define TIM_SMCR 0x08 /* Slave mode control reg */
> +#define TIM_DIER 0x0C /* DMA/interrupt register */
> +#define TIM_SR 0x10 /* Status register */
> +#define TIM_EGR 0x14 /* Event Generation Reg */
> +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> +#define TIM_PSC 0x28 /* Prescaler */
> +#define TIM_ARR 0x2c /* Auto-Reload Register */
> +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> +
> +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> +#define TIM_EGR_UG BIT(0) /* Update Generation */
> +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
> +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
> +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> +
> +#define STM32_TIMER_CELLS 2
> +#define MAX_TIM_PSC 0xFFFF
> +
> +struct stm32_mfd_timer_cfg {
> + const char *pwm_name;
> + const char *pwm_compatible;
> + const char *trigger_name;
> + const char *trigger_compatible;
> +};
> +
> +struct stm32_mfd_timer_dev {
> + /* Device data */
> + struct device *dev;
> + struct clk *clk;
> + int irq;
> +
> + /* Registers mapping */
> + struct regmap *regmap;
> +
> + /* Private data */
> + struct mfd_cell cells[STM32_TIMER_CELLS];
> + struct stm32_mfd_timer_cfg *cfg;
> +};
> +
> +#endif
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-11-22 17:40 +0100 |
| Subject | Re: [PATCH 2/7] add MFD for stm32 timer IP |
| Message-ID | <sGmgW-1eL-25@gated-at.bofh.it> |
| In reply to | #1527663 |
On Tue, 22 Nov 2016, Lee Jones wrote:
> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>
> > This hardware block could at used at same time for PWM generation
> > and IIO timer for other IPs like DAC, ADC or other timers.
> > PWM and IIO timer configuration are mixed in the same registers
> > so we need a MFD to be able to share those registers.
> >
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> > ---
> > drivers/mfd/Kconfig | 10 ++
> > drivers/mfd/Makefile | 2 +
> > drivers/mfd/stm32-mfd-timer.c | 236 ++++++++++++++++++++++++++++++++++++
> > include/linux/mfd/stm32-mfd-timer.h | 78 ++++++++++++
> > 4 files changed, 326 insertions(+)
> > create mode 100644 drivers/mfd/stm32-mfd-timer.c
> > create mode 100644 include/linux/mfd/stm32-mfd-timer.h
>
> This driver is going to need a re-write.
>
> However, it's difficult to provide suggestions, since I've been left
> off of the Cc: list for all the other patches.
>
> Please re-send the set with all of the Maintainers Cc'ed on all of
> the patches.
Scrap that -- they all just came trickling through!
> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> > index c6df644..63aee36 100644
> > --- a/drivers/mfd/Kconfig
> > +++ b/drivers/mfd/Kconfig
> > @@ -1607,6 +1607,15 @@ config MFD_STW481X
> > in various ST Microelectronics and ST-Ericsson embedded
> > Nomadik series.
> >
> > +config MFD_STM32_TIMER
> > + tristate "Support for STM32 multifunctions timer"
> > + select MFD_CORE
> > + select REGMAP
> > + depends on ARCH_STM32
> > + depends on OF
> > + help
> > + Select multifunction driver (pwm, IIO trigger) for stm32 timers
> > +
> > menu "Multimedia Capabilities Port drivers"
> > depends on ARCH_SA1100
> >
> > @@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
> > on the ARM Ltd. Versatile Express board.
> >
> > endmenu
> > +
> > endif
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> > index 9834e66..b348c3e 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
> >
> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> > +
> > +obj-$(CONFIG_MFD_STM32_TIMER) += stm32-mfd-timer.o
> > diff --git a/drivers/mfd/stm32-mfd-timer.c b/drivers/mfd/stm32-mfd-timer.c
> > new file mode 100644
> > index 0000000..67e7db3
> > --- /dev/null
> > +++ b/drivers/mfd/stm32-mfd-timer.c
> > @@ -0,0 +1,236 @@
> > +/*
> > + * stm32-timer.c
> > + *
> > + * Copyright (C) STMicroelectronics 2016
> > + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> > + * License terms: GNU General Public License (GPL), version 2
> > + */
> > +
> > +#include <linux/device.h>
> > +#include <linux/init.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +
> > +#include <linux/mfd/stm32-mfd-timer.h>
> > +
> > +static const struct stm32_mfd_timer_cfg mfd_cells_cfg[] = {
> > + {
> > + .pwm_name = "pwm1",
> > + .pwm_compatible = "st,stm32-pwm1",
> > + .trigger_name = "iiotimer1",
> > + .trigger_compatible = "st,stm32-iio-timer1",
> > + },
> > + {
> > + .pwm_name = "pwm2",
> > + .pwm_compatible = "st,stm32-pwm2",
> > + .trigger_name = "iiotimer2",
> > + .trigger_compatible = "st,stm32-iio-timer2",
> > + },
> > + {
> > + .pwm_name = "pwm3",
> > + .pwm_compatible = "st,stm32-pwm3",
> > + .trigger_name = "iiotimer3",
> > + .trigger_compatible = "st,stm32-iio-timer3",
> > + },
> > + {
> > + .pwm_name = "pwm4",
> > + .pwm_compatible = "st,stm32-pwm4",
> > + .trigger_name = "iiotimer4",
> > + .trigger_compatible = "st,stm32-iio-timer4",
> > + },
> > + {
> > + .pwm_name = "pwm5",
> > + .pwm_compatible = "st,stm32-pwm5",
> > + .trigger_name = "iiotimer5",
> > + .trigger_compatible = "st,stm32-iio-timer5",
> > + },
> > + {
> > + .trigger_name = "iiotimer6",
> > + .trigger_compatible = "st,stm32-iio-timer6",
> > + },
> > + {
> > + .trigger_name = "iiotimer7",
> > + .trigger_compatible = "st,stm32-iio-timer7",
> > + },
> > + {
> > + .pwm_name = "pwm8",
> > + .pwm_compatible = "st,stm32-pwm8",
> > + .trigger_name = "iiotimer8",
> > + .trigger_compatible = "st,stm32-iio-timer8",
> > + },
> > + {
> > + .pwm_name = "pwm9",
> > + .pwm_compatible = "st,stm32-pwm9",
> > + .trigger_name = "iiotimer9",
> > + .trigger_compatible = "st,stm32-iio-timer9",
> > + },
> > + {
> > + .pwm_name = "pwm10",
> > + .pwm_compatible = "st,stm32-pwm10",
> > + },
> > + {
> > + .pwm_name = "pwm11",
> > + .pwm_compatible = "st,stm32-pwm11",
> > + },
> > + {
> > + .pwm_name = "pwm12",
> > + .pwm_compatible = "st,stm32-pwm12",
> > + .trigger_name = "iiotimer12",
> > + .trigger_compatible = "st,stm32-iio-timer12",
> > + },
> > + {
> > + .pwm_name = "pwm13",
> > + .pwm_compatible = "st,stm32-pwm13",
> > + },
> > + {
> > + .pwm_name = "pwm14",
> > + .pwm_compatible = "st,stm32-pwm14",
> > + },
> > +};
> > +
> > +static const struct of_device_id stm32_timer_of_match[] = {
> > + {
> > + .compatible = "st,stm32-mfd-timer1",
> > + .data = &mfd_cells_cfg[0],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer2",
> > + .data = &mfd_cells_cfg[1],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer3",
> > + .data = &mfd_cells_cfg[2],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer4",
> > + .data = &mfd_cells_cfg[3],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer5",
> > + .data = &mfd_cells_cfg[4],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer6",
> > + .data = &mfd_cells_cfg[5],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer7",
> > + .data = &mfd_cells_cfg[6],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer8",
> > + .data = &mfd_cells_cfg[7],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer9",
> > + .data = &mfd_cells_cfg[8],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer10",
> > + .data = &mfd_cells_cfg[9],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer11",
> > + .data = &mfd_cells_cfg[10],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer12",
> > + .data = &mfd_cells_cfg[11],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer13",
> > + .data = &mfd_cells_cfg[12],
> > + },
> > + {
> > + .compatible = "st,stm32-mfd-timer14",
> > + .data = &mfd_cells_cfg[13],
> > + },
> > +};
> > +
> > +static const struct regmap_config stm32_timer_regmap_cfg = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = sizeof(u32),
> > + .max_register = 0x400,
> > + .fast_io = true,
> > +};
> > +
> > +static int stm32_mfd_timer_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct stm32_mfd_timer_dev *mfd;
> > + struct resource *res;
> > + int ret, nb_cells = 0;
> > + struct mfd_cell *cell = NULL;
> > + void __iomem *mmio;
> > +
> > + mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
> > + if (!mfd)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -ENOMEM;
> > +
> > + mmio = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(mmio))
> > + return PTR_ERR(mmio);
> > +
> > + mfd->regmap = devm_regmap_init_mmio_clk(dev, "mfd_timer_clk", mmio,
> > + &stm32_timer_regmap_cfg);
> > + if (IS_ERR(mfd->regmap))
> > + return PTR_ERR(mfd->regmap);
> > +
> > + mfd->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(mfd->clk))
> > + return PTR_ERR(mfd->clk);
> > +
> > + mfd->irq = platform_get_irq(pdev, 0);
> > + if (mfd->irq < 0)
> > + return -EINVAL;
> > +
> > + /* populate data structure depending on compatibility */
> > + if (!of_match_node(stm32_timer_of_match, np)->data)
> > + return -EINVAL;
> > +
> > + mfd->cfg =
> > + (struct stm32_mfd_timer_cfg *)of_match_node(stm32_timer_of_match, np)->data;
> > +
> > + if (mfd->cfg->pwm_name && mfd->cfg->pwm_compatible) {
> > + cell = &mfd->cells[nb_cells++];
> > + cell->name = mfd->cfg->pwm_name;
> > + cell->of_compatible = mfd->cfg->pwm_compatible;
> > + cell->platform_data = mfd;
> > + cell->pdata_size = sizeof(*mfd);
> > + }
> > +
> > + if (mfd->cfg->trigger_name && mfd->cfg->trigger_compatible) {
> > + cell = &mfd->cells[nb_cells++];
> > + cell->name = mfd->cfg->trigger_name;
> > + cell->of_compatible = mfd->cfg->trigger_compatible;
> > + cell->platform_data = mfd;
> > + cell->pdata_size = sizeof(*mfd);
> > + }
> > +
> > + ret = devm_mfd_add_devices(&pdev->dev, pdev->id, mfd->cells,
> > + nb_cells, NULL, 0, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + platform_set_drvdata(pdev, mfd);
> > +
> > + return 0;
> > +}
> > +
> > +static struct platform_driver stm32_mfd_timer_driver = {
> > + .probe = stm32_mfd_timer_probe,
> > + .driver = {
> > + .name = "stm32-mfd-timer",
> > + .of_match_table = stm32_timer_of_match,
> > + },
> > +};
> > +module_platform_driver(stm32_mfd_timer_driver);
> > +
> > +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer MFD");
> > +MODULE_LICENSE("GPL");
> > diff --git a/include/linux/mfd/stm32-mfd-timer.h b/include/linux/mfd/stm32-mfd-timer.h
> > new file mode 100644
> > index 0000000..4a79c22
> > --- /dev/null
> > +++ b/include/linux/mfd/stm32-mfd-timer.h
> > @@ -0,0 +1,78 @@
> > +/*
> > + * stm32-mfd-timer.h
> > + *
> > + * Copyright (C) STMicroelectronics 2016
> > + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
> > + * License terms: GNU General Public License (GPL), version 2
> > + */
> > +
> > +#ifndef _LINUX_MFD_STM32_TIMER_H_
> > +#define _LINUX_MFD_STM32_TIMER_H_
> > +
> > +#include <linux/clk.h>
> > +#include <linux/mfd/core.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +
> > +#define TIM_CR1 0x00 /* Control Register 1 */
> > +#define TIM_CR2 0x04 /* Control Register 2 */
> > +#define TIM_SMCR 0x08 /* Slave mode control reg */
> > +#define TIM_DIER 0x0C /* DMA/interrupt register */
> > +#define TIM_SR 0x10 /* Status register */
> > +#define TIM_EGR 0x14 /* Event Generation Reg */
> > +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> > +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> > +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> > +#define TIM_PSC 0x28 /* Prescaler */
> > +#define TIM_ARR 0x2c /* Auto-Reload Register */
> > +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> > +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> > +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> > +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> > +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> > +
> > +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> > +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> > +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> > +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> > +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> > +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> > +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> > +#define TIM_EGR_UG BIT(0) /* Update Generation */
> > +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> > +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> > +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> > +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> > +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> > +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> > +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> > +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
> > +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
> > +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> > +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> > +
> > +#define STM32_TIMER_CELLS 2
> > +#define MAX_TIM_PSC 0xFFFF
> > +
> > +struct stm32_mfd_timer_cfg {
> > + const char *pwm_name;
> > + const char *pwm_compatible;
> > + const char *trigger_name;
> > + const char *trigger_compatible;
> > +};
> > +
> > +struct stm32_mfd_timer_dev {
> > + /* Device data */
> > + struct device *dev;
> > + struct clk *clk;
> > + int irq;
> > +
> > + /* Registers mapping */
> > + struct regmap *regmap;
> > +
> > + /* Private data */
> > + struct mfd_cell cells[STM32_TIMER_CELLS];
> > + struct stm32_mfd_timer_cfg *cfg;
> > +};
> > +
> > +#endif
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:50 +0100 |
| Subject | Re: [PATCH 2/7] add MFD for stm32 timer IP |
| Message-ID | <sGmqC-1ia-19@gated-at.bofh.it> |
| In reply to | #1527681 |
Your comments are welcome on all of them ;-)
2016-11-22 17:41 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Tue, 22 Nov 2016, Lee Jones wrote:
>
>> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>>
>> > This hardware block could at used at same time for PWM generation
>> > and IIO timer for other IPs like DAC, ADC or other timers.
>> > PWM and IIO timer configuration are mixed in the same registers
>> > so we need a MFD to be able to share those registers.
>> >
>> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> > ---
>> > drivers/mfd/Kconfig | 10 ++
>> > drivers/mfd/Makefile | 2 +
>> > drivers/mfd/stm32-mfd-timer.c | 236 ++++++++++++++++++++++++++++++++++++
>> > include/linux/mfd/stm32-mfd-timer.h | 78 ++++++++++++
>> > 4 files changed, 326 insertions(+)
>> > create mode 100644 drivers/mfd/stm32-mfd-timer.c
>> > create mode 100644 include/linux/mfd/stm32-mfd-timer.h
>>
>> This driver is going to need a re-write.
>>
>> However, it's difficult to provide suggestions, since I've been left
>> off of the Cc: list for all the other patches.
>>
>> Please re-send the set with all of the Maintainers Cc'ed on all of
>> the patches.
>
> Scrap that -- they all just came trickling through!
>
>> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>> > index c6df644..63aee36 100644
>> > --- a/drivers/mfd/Kconfig
>> > +++ b/drivers/mfd/Kconfig
>> > @@ -1607,6 +1607,15 @@ config MFD_STW481X
>> > in various ST Microelectronics and ST-Ericsson embedded
>> > Nomadik series.
>> >
>> > +config MFD_STM32_TIMER
>> > + tristate "Support for STM32 multifunctions timer"
>> > + select MFD_CORE
>> > + select REGMAP
>> > + depends on ARCH_STM32
>> > + depends on OF
>> > + help
>> > + Select multifunction driver (pwm, IIO trigger) for stm32 timers
>> > +
>> > menu "Multimedia Capabilities Port drivers"
>> > depends on ARCH_SA1100
>> >
>> > @@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
>> > on the ARM Ltd. Versatile Express board.
>> >
>> > endmenu
>> > +
>> > endif
>> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>> > index 9834e66..b348c3e 100644
>> > --- a/drivers/mfd/Makefile
>> > +++ b/drivers/mfd/Makefile
>> > @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
>> > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>> >
>> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
>> > +
>> > +obj-$(CONFIG_MFD_STM32_TIMER) += stm32-mfd-timer.o
>> > diff --git a/drivers/mfd/stm32-mfd-timer.c b/drivers/mfd/stm32-mfd-timer.c
>> > new file mode 100644
>> > index 0000000..67e7db3
>> > --- /dev/null
>> > +++ b/drivers/mfd/stm32-mfd-timer.c
>> > @@ -0,0 +1,236 @@
>> > +/*
>> > + * stm32-timer.c
>> > + *
>> > + * Copyright (C) STMicroelectronics 2016
>> > + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
>> > + * License terms: GNU General Public License (GPL), version 2
>> > + */
>> > +
>> > +#include <linux/device.h>
>> > +#include <linux/init.h>
>> > +#include <linux/module.h>
>> > +#include <linux/of.h>
>> > +
>> > +#include <linux/mfd/stm32-mfd-timer.h>
>> > +
>> > +static const struct stm32_mfd_timer_cfg mfd_cells_cfg[] = {
>> > + {
>> > + .pwm_name = "pwm1",
>> > + .pwm_compatible = "st,stm32-pwm1",
>> > + .trigger_name = "iiotimer1",
>> > + .trigger_compatible = "st,stm32-iio-timer1",
>> > + },
>> > + {
>> > + .pwm_name = "pwm2",
>> > + .pwm_compatible = "st,stm32-pwm2",
>> > + .trigger_name = "iiotimer2",
>> > + .trigger_compatible = "st,stm32-iio-timer2",
>> > + },
>> > + {
>> > + .pwm_name = "pwm3",
>> > + .pwm_compatible = "st,stm32-pwm3",
>> > + .trigger_name = "iiotimer3",
>> > + .trigger_compatible = "st,stm32-iio-timer3",
>> > + },
>> > + {
>> > + .pwm_name = "pwm4",
>> > + .pwm_compatible = "st,stm32-pwm4",
>> > + .trigger_name = "iiotimer4",
>> > + .trigger_compatible = "st,stm32-iio-timer4",
>> > + },
>> > + {
>> > + .pwm_name = "pwm5",
>> > + .pwm_compatible = "st,stm32-pwm5",
>> > + .trigger_name = "iiotimer5",
>> > + .trigger_compatible = "st,stm32-iio-timer5",
>> > + },
>> > + {
>> > + .trigger_name = "iiotimer6",
>> > + .trigger_compatible = "st,stm32-iio-timer6",
>> > + },
>> > + {
>> > + .trigger_name = "iiotimer7",
>> > + .trigger_compatible = "st,stm32-iio-timer7",
>> > + },
>> > + {
>> > + .pwm_name = "pwm8",
>> > + .pwm_compatible = "st,stm32-pwm8",
>> > + .trigger_name = "iiotimer8",
>> > + .trigger_compatible = "st,stm32-iio-timer8",
>> > + },
>> > + {
>> > + .pwm_name = "pwm9",
>> > + .pwm_compatible = "st,stm32-pwm9",
>> > + .trigger_name = "iiotimer9",
>> > + .trigger_compatible = "st,stm32-iio-timer9",
>> > + },
>> > + {
>> > + .pwm_name = "pwm10",
>> > + .pwm_compatible = "st,stm32-pwm10",
>> > + },
>> > + {
>> > + .pwm_name = "pwm11",
>> > + .pwm_compatible = "st,stm32-pwm11",
>> > + },
>> > + {
>> > + .pwm_name = "pwm12",
>> > + .pwm_compatible = "st,stm32-pwm12",
>> > + .trigger_name = "iiotimer12",
>> > + .trigger_compatible = "st,stm32-iio-timer12",
>> > + },
>> > + {
>> > + .pwm_name = "pwm13",
>> > + .pwm_compatible = "st,stm32-pwm13",
>> > + },
>> > + {
>> > + .pwm_name = "pwm14",
>> > + .pwm_compatible = "st,stm32-pwm14",
>> > + },
>> > +};
>> > +
>> > +static const struct of_device_id stm32_timer_of_match[] = {
>> > + {
>> > + .compatible = "st,stm32-mfd-timer1",
>> > + .data = &mfd_cells_cfg[0],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer2",
>> > + .data = &mfd_cells_cfg[1],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer3",
>> > + .data = &mfd_cells_cfg[2],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer4",
>> > + .data = &mfd_cells_cfg[3],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer5",
>> > + .data = &mfd_cells_cfg[4],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer6",
>> > + .data = &mfd_cells_cfg[5],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer7",
>> > + .data = &mfd_cells_cfg[6],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer8",
>> > + .data = &mfd_cells_cfg[7],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer9",
>> > + .data = &mfd_cells_cfg[8],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer10",
>> > + .data = &mfd_cells_cfg[9],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer11",
>> > + .data = &mfd_cells_cfg[10],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer12",
>> > + .data = &mfd_cells_cfg[11],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer13",
>> > + .data = &mfd_cells_cfg[12],
>> > + },
>> > + {
>> > + .compatible = "st,stm32-mfd-timer14",
>> > + .data = &mfd_cells_cfg[13],
>> > + },
>> > +};
>> > +
>> > +static const struct regmap_config stm32_timer_regmap_cfg = {
>> > + .reg_bits = 32,
>> > + .val_bits = 32,
>> > + .reg_stride = sizeof(u32),
>> > + .max_register = 0x400,
>> > + .fast_io = true,
>> > +};
>> > +
>> > +static int stm32_mfd_timer_probe(struct platform_device *pdev)
>> > +{
>> > + struct device *dev = &pdev->dev;
>> > + struct device_node *np = dev->of_node;
>> > + struct stm32_mfd_timer_dev *mfd;
>> > + struct resource *res;
>> > + int ret, nb_cells = 0;
>> > + struct mfd_cell *cell = NULL;
>> > + void __iomem *mmio;
>> > +
>> > + mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
>> > + if (!mfd)
>> > + return -ENOMEM;
>> > +
>> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> > + if (!res)
>> > + return -ENOMEM;
>> > +
>> > + mmio = devm_ioremap_resource(dev, res);
>> > + if (IS_ERR(mmio))
>> > + return PTR_ERR(mmio);
>> > +
>> > + mfd->regmap = devm_regmap_init_mmio_clk(dev, "mfd_timer_clk", mmio,
>> > + &stm32_timer_regmap_cfg);
>> > + if (IS_ERR(mfd->regmap))
>> > + return PTR_ERR(mfd->regmap);
>> > +
>> > + mfd->clk = devm_clk_get(dev, NULL);
>> > + if (IS_ERR(mfd->clk))
>> > + return PTR_ERR(mfd->clk);
>> > +
>> > + mfd->irq = platform_get_irq(pdev, 0);
>> > + if (mfd->irq < 0)
>> > + return -EINVAL;
>> > +
>> > + /* populate data structure depending on compatibility */
>> > + if (!of_match_node(stm32_timer_of_match, np)->data)
>> > + return -EINVAL;
>> > +
>> > + mfd->cfg =
>> > + (struct stm32_mfd_timer_cfg *)of_match_node(stm32_timer_of_match, np)->data;
>> > +
>> > + if (mfd->cfg->pwm_name && mfd->cfg->pwm_compatible) {
>> > + cell = &mfd->cells[nb_cells++];
>> > + cell->name = mfd->cfg->pwm_name;
>> > + cell->of_compatible = mfd->cfg->pwm_compatible;
>> > + cell->platform_data = mfd;
>> > + cell->pdata_size = sizeof(*mfd);
>> > + }
>> > +
>> > + if (mfd->cfg->trigger_name && mfd->cfg->trigger_compatible) {
>> > + cell = &mfd->cells[nb_cells++];
>> > + cell->name = mfd->cfg->trigger_name;
>> > + cell->of_compatible = mfd->cfg->trigger_compatible;
>> > + cell->platform_data = mfd;
>> > + cell->pdata_size = sizeof(*mfd);
>> > + }
>> > +
>> > + ret = devm_mfd_add_devices(&pdev->dev, pdev->id, mfd->cells,
>> > + nb_cells, NULL, 0, NULL);
>> > + if (ret)
>> > + return ret;
>> > +
>> > + platform_set_drvdata(pdev, mfd);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static struct platform_driver stm32_mfd_timer_driver = {
>> > + .probe = stm32_mfd_timer_probe,
>> > + .driver = {
>> > + .name = "stm32-mfd-timer",
>> > + .of_match_table = stm32_timer_of_match,
>> > + },
>> > +};
>> > +module_platform_driver(stm32_mfd_timer_driver);
>> > +
>> > +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer MFD");
>> > +MODULE_LICENSE("GPL");
>> > diff --git a/include/linux/mfd/stm32-mfd-timer.h b/include/linux/mfd/stm32-mfd-timer.h
>> > new file mode 100644
>> > index 0000000..4a79c22
>> > --- /dev/null
>> > +++ b/include/linux/mfd/stm32-mfd-timer.h
>> > @@ -0,0 +1,78 @@
>> > +/*
>> > + * stm32-mfd-timer.h
>> > + *
>> > + * Copyright (C) STMicroelectronics 2016
>> > + * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
>> > + * License terms: GNU General Public License (GPL), version 2
>> > + */
>> > +
>> > +#ifndef _LINUX_MFD_STM32_TIMER_H_
>> > +#define _LINUX_MFD_STM32_TIMER_H_
>> > +
>> > +#include <linux/clk.h>
>> > +#include <linux/mfd/core.h>
>> > +#include <linux/regmap.h>
>> > +#include <linux/reset.h>
>> > +
>> > +#define TIM_CR1 0x00 /* Control Register 1 */
>> > +#define TIM_CR2 0x04 /* Control Register 2 */
>> > +#define TIM_SMCR 0x08 /* Slave mode control reg */
>> > +#define TIM_DIER 0x0C /* DMA/interrupt register */
>> > +#define TIM_SR 0x10 /* Status register */
>> > +#define TIM_EGR 0x14 /* Event Generation Reg */
>> > +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
>> > +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
>> > +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
>> > +#define TIM_PSC 0x28 /* Prescaler */
>> > +#define TIM_ARR 0x2c /* Auto-Reload Register */
>> > +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
>> > +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
>> > +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
>> > +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
>> > +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
>> > +
>> > +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
>> > +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
>> > +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
>> > +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
>> > +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
>> > +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
>> > +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
>> > +#define TIM_EGR_UG BIT(0) /* Update Generation */
>> > +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
>> > +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
>> > +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
>> > +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
>> > +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
>> > +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
>> > +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
>> > +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
>> > +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
>> > +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
>> > +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
>> > +
>> > +#define STM32_TIMER_CELLS 2
>> > +#define MAX_TIM_PSC 0xFFFF
>> > +
>> > +struct stm32_mfd_timer_cfg {
>> > + const char *pwm_name;
>> > + const char *pwm_compatible;
>> > + const char *trigger_name;
>> > + const char *trigger_compatible;
>> > +};
>> > +
>> > +struct stm32_mfd_timer_dev {
>> > + /* Device data */
>> > + struct device *dev;
>> > + struct clk *clk;
>> > + int irq;
>> > +
>> > + /* Registers mapping */
>> > + struct regmap *regmap;
>> > +
>> > + /* Private data */
>> > + struct mfd_cell cells[STM32_TIMER_CELLS];
>> > + struct stm32_mfd_timer_cfg *cfg;
>> > +};
>> > +
>> > +#endif
>>
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:30 +0100 |
| Subject | [PATCH 3/7] add pwm-stm32 DT bindings |
| Message-ID | <sGm7g-1bI-21@gated-at.bofh.it> |
| In reply to | #1527652 |
Define binding for pwm-stm32
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../devicetree/bindings/pwm/pwm-stm32.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
new file mode 100644
index 0000000..819e024
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
@@ -0,0 +1,43 @@
+STMicroelectronics PWM driver bindings for STM32
+--------------------------------------
+
+Must be a child of STM32 multifunctions timer driver
+
+Required parameters:
+- compatible : "st,stm32-pwm1"
+ "st,stm32-pwm2"
+ "st,stm32-pwm3"
+ "st,stm32-pwm4"
+ "st,stm32-pwm5"
+ "st,stm32-pwm8"
+ "st,stm32-pwm9"
+ "st,stm32-pwm10"
+ "st,stm32-pwm11"
+ "st,stm32-pwm12"
+ "st,stm32-pwm13"
+ "st,stm32-pwm14"
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes
+ for PWM module.
+ For Pinctrl properties, please refer to [1].
+
+Optional parameters:
+- st,breakinput-polarity if set enable break input feature.
+ The value define the active polarity:
+ - 0 (active LOW)
+ - 1 (active HIGH)
+
+[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example:
+ mfd_timer1: mfdtimer1@40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+
+ pwm1: pwm1@40010000 {
+ compatible = "st,stm32-pwm1";
+ };
+ };
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:30 +0100 |
| Subject | [PATCH 7/7] add stm32 multi-functions timer driver in DT |
| Message-ID | <sGm7g-1bI-27@gated-at.bofh.it> |
| In reply to | #1527652 |
Add timers MFD and childs into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 246 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stm32f469-disco.dts | 29 ++++
2 files changed, 275 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index bca491d..28a0fe9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -355,6 +355,21 @@
slew-rate = <2>;
};
};
+
+ pwm1_pins: pwm@1 {
+ pins {
+ pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
+ <STM32F429_PB13_FUNC_TIM1_CH1N>,
+ <STM32F429_PB12_FUNC_TIM1_BKIN>;
+ };
+ };
+
+ pwm3_pins: pwm@3 {
+ pins {
+ pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
+ <STM32F429_PB5_FUNC_TIM3_CH2>;
+ };
+ };
};
rcc: rcc@40023810 {
@@ -426,6 +441,237 @@
interrupts = <80>;
clocks = <&rcc 0 38>;
};
+
+ mfd_timer1: mfdtimer1@40010000 {
+ compatible = "st,stm32-mfd-timer1";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <27>;
+ status = "disabled";
+
+ pwm1: pwm1@40010000 {
+ compatible = "st,stm32-pwm1";
+ status = "disabled";
+ };
+
+ iiotimer1: iiotimer1@40010000 {
+ compatible = "st,stm32-iio-timer1";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer2: mfdtimer2@40000000 {
+ compatible = "st,stm32-mfd-timer2";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc 0 128>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <28>;
+ status = "disabled";
+
+ pwm2: pwm2@40000000 {
+ compatible = "st,stm32-pwm2";
+ status = "disabled";
+ };
+ iiotimer2: iiotimer2@40000000 {
+ compatible = "st,stm32-iio-timer2";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer3: mfdtimer3@40000400 {
+ compatible = "st,stm32-mfd-timer3";
+ reg = <0x40000400 0x400>;
+ clocks = <&rcc 0 129>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <29>;
+ status = "disabled";
+
+ pwm3: pwm3@40000400 {
+ compatible = "st,stm32-pwm3";
+ status = "disabled";
+ };
+ iiotimer3: iiotimer3@40000400 {
+ compatible = "st,stm32-iio-timer3";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer4: mfdtimer4@40000800 {
+ compatible = "st,stm32-mfd-timer4";
+ reg = <0x40000800 0x400>;
+ clocks = <&rcc 0 130>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <30>;
+ status = "disabled";
+
+ pwm4: pwm4@40000800 {
+ compatible = "st,stm32-pwm4";
+ status = "disabled";
+ };
+ iiotimer4: iiotimer4@40000800 {
+ compatible = "st,stm32-iio-timer4";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer5: mfdtimer5@40000C00 {
+ compatible = "st,stm32-mfd-timer5";
+ reg = <0x40000C00 0x400>;
+ clocks = <&rcc 0 131>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <50>;
+ status = "disabled";
+
+ pwm5: pwm5@40000C00 {
+ compatible = "st,stm32-pwm5";
+ status = "disabled";
+ };
+ iiotimer5: iiotimer5@40000800 {
+ compatible = "st,stm32-iio-timer5";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer6: mfdtimer6@40001000 {
+ compatible = "st,stm32-mfd-timer6";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc 0 132>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <54>;
+ status = "disabled";
+
+ iiotimer6: iiotimer6@40001000 {
+ compatible = "st,stm32-iio-timer6";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer7: mfdtimer7@40001400 {
+ compatible = "st,stm32-mfd-timer7";
+ reg = <0x40001400 0x400>;
+ clocks = <&rcc 0 133>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <55>;
+ status = "disabled";
+
+ iiotimer7: iiotimer7@40001400 {
+ compatible = "st,stm32-iio-timer7";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer8: mfdtimer8@40010400 {
+ compatible = "st,stm32-mfd-timer8";
+ reg = <0x40010400 0x400>;
+ clocks = <&rcc 0 161>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <46>;
+ status = "disabled";
+
+ pwm8: pwm8@40010400 {
+ compatible = "st,stm32-pwm8";
+ status = "disabled";
+ };
+
+ iiotimer8: iiotimer7@40010400 {
+ compatible = "st,stm32-iio-timer8";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer9: mfdtimer9@40014000 {
+ compatible = "st,stm32-mfd-timer9";
+ reg = <0x40014000 0x400>;
+ clocks = <&rcc 0 176>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <24>;
+ status = "disabled";
+
+ pwm9: pwm9@40014000 {
+ compatible = "st,stm32-pwm9";
+ status = "disabled";
+ };
+
+ iiotimer9: iiotimer9@40014000 {
+ compatible = "st,stm32-iio-timer9";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer10: mfdtimer10@40014400 {
+ compatible = "st,stm32-mfd-timer10";
+ reg = <0x40014400 0x400>;
+ clocks = <&rcc 0 177>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <25>;
+ status = "disabled";
+
+ pwm10: pwm10@40014400 {
+ compatible = "st,stm32-pwm10";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer11: mfdtimer11@40014800 {
+ compatible = "st,stm32-mfd-timer11";
+ reg = <0x40014800 0x400>;
+ clocks = <&rcc 0 178>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <26>;
+ status = "disabled";
+
+ pwm11: pwm11@40014800 {
+ compatible = "st,stm32-pwm11";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer12: mfdtimer12@40001800 {
+ compatible = "st,stm32-mfd-timer12";
+ reg = <0x40001800 0x400>;
+ clocks = <&rcc 0 134>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <43>;
+ status = "disabled";
+
+ pwm12: pwm12@40001800 {
+ compatible = "st,stm32-pwm12";
+ status = "disabled";
+ };
+ iiotimer12: iiotimer12@40001800 {
+ compatible = "st,stm32-iio-timer12";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer13: mfdtimer13@40001C00 {
+ compatible = "st,stm32-mfd-timer13";
+ reg = <0x40001C00 0x400>;
+ clocks = <&rcc 0 135>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <44>;
+ status = "disabled";
+
+ pwm13: pwm13@40001C00 {
+ compatible = "st,stm32-pwm13";
+ status = "disabled";
+ };
+ };
+
+ mfd_timer14: mfdtimer14@40002000 {
+ compatible = "st,stm32-mfd-timer14";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc 0 136>;
+ clock-names = "mfd_timer_clk";
+ interrupts = <45>;
+ status = "disabled";
+
+ pwm14: pwm14@40002000 {
+ compatible = "st,stm32-pwm14";
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 8a163d7..a8f1788 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -81,3 +81,32 @@
&usart3 {
status = "okay";
};
+
+&mfd_timer1 {
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ st,breakinput-polarity = <0>;
+ status = "okay";
+};
+
+&iiotimer1 {
+ status = "okay";
+};
+
+&mfd_timer3 {
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&iiotimer3 {
+ status = "okay";
+};
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Alexandre Torgue <alexandre.torgue@st.com> |
|---|---|
| Date | 2016-11-22 18:10 +0100 |
| Subject | Re: [PATCH 7/7] add stm32 multi-functions timer driver in DT |
| Message-ID | <sGmJY-1DN-41@gated-at.bofh.it> |
| In reply to | #1527667 |
Hi Benjamin,
On 11/22/2016 05:13 PM, Benjamin Gaignard wrote:
> Add timers MFD and childs into DT for stm32f4.
> Define and enable pwm1 and pwm3 for stm32f469 discovery board
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
If you have to send a v2 for this series please change commit header by:
"ARM: dts: stm32: ..." (if not I will do it by myself)
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 246 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stm32f469-disco.dts | 29 ++++
> 2 files changed, 275 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index bca491d..28a0fe9 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -355,6 +355,21 @@
> slew-rate = <2>;
> };
> };
> +
> + pwm1_pins: pwm@1 {
> + pins {
> + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
> + <STM32F429_PB13_FUNC_TIM1_CH1N>,
> + <STM32F429_PB12_FUNC_TIM1_BKIN>;
> + };
> + };
> +
> + pwm3_pins: pwm@3 {
> + pins {
> + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
> + <STM32F429_PB5_FUNC_TIM3_CH2>;
> + };
> + };
> };
>
> rcc: rcc@40023810 {
> @@ -426,6 +441,237 @@
> interrupts = <80>;
> clocks = <&rcc 0 38>;
> };
> +
> + mfd_timer1: mfdtimer1@40010000 {
> + compatible = "st,stm32-mfd-timer1";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <27>;
> + status = "disabled";
> +
> + pwm1: pwm1@40010000 {
> + compatible = "st,stm32-pwm1";
> + status = "disabled";
> + };
> +
> + iiotimer1: iiotimer1@40010000 {
> + compatible = "st,stm32-iio-timer1";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer2: mfdtimer2@40000000 {
> + compatible = "st,stm32-mfd-timer2";
> + reg = <0x40000000 0x400>;
> + clocks = <&rcc 0 128>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <28>;
> + status = "disabled";
> +
> + pwm2: pwm2@40000000 {
> + compatible = "st,stm32-pwm2";
> + status = "disabled";
> + };
> + iiotimer2: iiotimer2@40000000 {
> + compatible = "st,stm32-iio-timer2";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer3: mfdtimer3@40000400 {
> + compatible = "st,stm32-mfd-timer3";
> + reg = <0x40000400 0x400>;
> + clocks = <&rcc 0 129>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <29>;
> + status = "disabled";
> +
> + pwm3: pwm3@40000400 {
> + compatible = "st,stm32-pwm3";
> + status = "disabled";
> + };
> + iiotimer3: iiotimer3@40000400 {
> + compatible = "st,stm32-iio-timer3";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer4: mfdtimer4@40000800 {
> + compatible = "st,stm32-mfd-timer4";
> + reg = <0x40000800 0x400>;
> + clocks = <&rcc 0 130>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <30>;
> + status = "disabled";
> +
> + pwm4: pwm4@40000800 {
> + compatible = "st,stm32-pwm4";
> + status = "disabled";
> + };
> + iiotimer4: iiotimer4@40000800 {
> + compatible = "st,stm32-iio-timer4";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer5: mfdtimer5@40000C00 {
> + compatible = "st,stm32-mfd-timer5";
> + reg = <0x40000C00 0x400>;
> + clocks = <&rcc 0 131>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <50>;
> + status = "disabled";
> +
> + pwm5: pwm5@40000C00 {
> + compatible = "st,stm32-pwm5";
> + status = "disabled";
> + };
> + iiotimer5: iiotimer5@40000800 {
> + compatible = "st,stm32-iio-timer5";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer6: mfdtimer6@40001000 {
> + compatible = "st,stm32-mfd-timer6";
> + reg = <0x40001000 0x400>;
> + clocks = <&rcc 0 132>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <54>;
> + status = "disabled";
> +
> + iiotimer6: iiotimer6@40001000 {
> + compatible = "st,stm32-iio-timer6";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer7: mfdtimer7@40001400 {
> + compatible = "st,stm32-mfd-timer7";
> + reg = <0x40001400 0x400>;
> + clocks = <&rcc 0 133>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <55>;
> + status = "disabled";
> +
> + iiotimer7: iiotimer7@40001400 {
> + compatible = "st,stm32-iio-timer7";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer8: mfdtimer8@40010400 {
> + compatible = "st,stm32-mfd-timer8";
> + reg = <0x40010400 0x400>;
> + clocks = <&rcc 0 161>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <46>;
> + status = "disabled";
> +
> + pwm8: pwm8@40010400 {
> + compatible = "st,stm32-pwm8";
> + status = "disabled";
> + };
> +
> + iiotimer8: iiotimer7@40010400 {
> + compatible = "st,stm32-iio-timer8";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer9: mfdtimer9@40014000 {
> + compatible = "st,stm32-mfd-timer9";
> + reg = <0x40014000 0x400>;
> + clocks = <&rcc 0 176>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <24>;
> + status = "disabled";
> +
> + pwm9: pwm9@40014000 {
> + compatible = "st,stm32-pwm9";
> + status = "disabled";
> + };
> +
> + iiotimer9: iiotimer9@40014000 {
> + compatible = "st,stm32-iio-timer9";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer10: mfdtimer10@40014400 {
> + compatible = "st,stm32-mfd-timer10";
> + reg = <0x40014400 0x400>;
> + clocks = <&rcc 0 177>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <25>;
> + status = "disabled";
> +
> + pwm10: pwm10@40014400 {
> + compatible = "st,stm32-pwm10";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer11: mfdtimer11@40014800 {
> + compatible = "st,stm32-mfd-timer11";
> + reg = <0x40014800 0x400>;
> + clocks = <&rcc 0 178>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <26>;
> + status = "disabled";
> +
> + pwm11: pwm11@40014800 {
> + compatible = "st,stm32-pwm11";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer12: mfdtimer12@40001800 {
> + compatible = "st,stm32-mfd-timer12";
> + reg = <0x40001800 0x400>;
> + clocks = <&rcc 0 134>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <43>;
> + status = "disabled";
> +
> + pwm12: pwm12@40001800 {
> + compatible = "st,stm32-pwm12";
> + status = "disabled";
> + };
> + iiotimer12: iiotimer12@40001800 {
> + compatible = "st,stm32-iio-timer12";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer13: mfdtimer13@40001C00 {
> + compatible = "st,stm32-mfd-timer13";
> + reg = <0x40001C00 0x400>;
> + clocks = <&rcc 0 135>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <44>;
> + status = "disabled";
> +
> + pwm13: pwm13@40001C00 {
> + compatible = "st,stm32-pwm13";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer14: mfdtimer14@40002000 {
> + compatible = "st,stm32-mfd-timer14";
> + reg = <0x40002000 0x400>;
> + clocks = <&rcc 0 136>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <45>;
> + status = "disabled";
> +
> + pwm14: pwm14@40002000 {
> + compatible = "st,stm32-pwm14";
> + status = "disabled";
> + };
> + };
> };
> };
>
> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
> index 8a163d7..a8f1788 100644
> --- a/arch/arm/boot/dts/stm32f469-disco.dts
> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
> @@ -81,3 +81,32 @@
> &usart3 {
> status = "okay";
> };
> +
> +&mfd_timer1 {
> + status = "okay";
> +};
> +
> +&pwm1 {
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + st,breakinput-polarity = <0>;
> + status = "okay";
> +};
> +
> +&iiotimer1 {
> + status = "okay";
> +};
> +
> +&mfd_timer3 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + pinctrl-0 = <&pwm3_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&iiotimer3 {
> + status = "okay";
> +};
>
[toc] | [prev] | [next] | [standalone]
| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-11-23 11:00 +0100 |
| Subject | Re: [PATCH 7/7] add stm32 multi-functions timer driver in DT |
| Message-ID | <sGCvn-3a3-5@gated-at.bofh.it> |
| In reply to | #1527667 |
On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
> Add timers MFD and childs into DT for stm32f4.
> Define and enable pwm1 and pwm3 for stm32f469 discovery board
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 246 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stm32f469-disco.dts | 29 ++++
> 2 files changed, 275 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index bca491d..28a0fe9 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -355,6 +355,21 @@
> slew-rate = <2>;
> };
> };
> +
> + pwm1_pins: pwm@1 {
> + pins {
> + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
> + <STM32F429_PB13_FUNC_TIM1_CH1N>,
> + <STM32F429_PB12_FUNC_TIM1_BKIN>;
> + };
> + };
> +
> + pwm3_pins: pwm@3 {
> + pins {
> + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
> + <STM32F429_PB5_FUNC_TIM3_CH2>;
> + };
> + };
> };
>
> rcc: rcc@40023810 {
> @@ -426,6 +441,237 @@
> interrupts = <80>;
> clocks = <&rcc 0 38>;
> };
> +
> + mfd_timer1: mfdtimer1@40010000 {
Do you reference this node?
If not, it should read:
advanced-control@40010000
> + compatible = "st,stm32-mfd-timer1";
"st,stm32-advanced-control"
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "mfd_timer_clk";
"clk_int"
> + interrupts = <27>;
This is a timer property.
Also move the associated registration C code into the timer driver.
> + status = "disabled";
> +
> + pwm1: pwm1@40010000 {
pwm@0 {
> + compatible = "st,stm32-pwm1";
st,stm32-advanced-control-pwm
> + status = "disabled";
> + };
> +
> + iiotimer1: iiotimer1@40010000 {
Same here:
timer@0
> + compatible = "st,stm32-iio-timer1";
st,stm32-advanced-control-timer
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer2: mfdtimer2@40000000 {
> + compatible = "st,stm32-mfd-timer2";
> + reg = <0x40000000 0x400>;
> + clocks = <&rcc 0 128>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <28>;
> + status = "disabled";
> +
> + pwm2: pwm2@40000000 {
> + compatible = "st,stm32-pwm2";
> + status = "disabled";
> + };
> + iiotimer2: iiotimer2@40000000 {
> + compatible = "st,stm32-iio-timer2";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer3: mfdtimer3@40000400 {
> + compatible = "st,stm32-mfd-timer3";
> + reg = <0x40000400 0x400>;
> + clocks = <&rcc 0 129>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <29>;
> + status = "disabled";
> +
> + pwm3: pwm3@40000400 {
> + compatible = "st,stm32-pwm3";
> + status = "disabled";
> + };
> + iiotimer3: iiotimer3@40000400 {
> + compatible = "st,stm32-iio-timer3";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer4: mfdtimer4@40000800 {
> + compatible = "st,stm32-mfd-timer4";
> + reg = <0x40000800 0x400>;
> + clocks = <&rcc 0 130>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <30>;
> + status = "disabled";
> +
> + pwm4: pwm4@40000800 {
> + compatible = "st,stm32-pwm4";
> + status = "disabled";
> + };
> + iiotimer4: iiotimer4@40000800 {
> + compatible = "st,stm32-iio-timer4";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer5: mfdtimer5@40000C00 {
> + compatible = "st,stm32-mfd-timer5";
> + reg = <0x40000C00 0x400>;
> + clocks = <&rcc 0 131>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <50>;
> + status = "disabled";
> +
> + pwm5: pwm5@40000C00 {
> + compatible = "st,stm32-pwm5";
> + status = "disabled";
> + };
> + iiotimer5: iiotimer5@40000800 {
> + compatible = "st,stm32-iio-timer5";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer6: mfdtimer6@40001000 {
> + compatible = "st,stm32-mfd-timer6";
> + reg = <0x40001000 0x400>;
> + clocks = <&rcc 0 132>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <54>;
> + status = "disabled";
> +
> + iiotimer6: iiotimer6@40001000 {
> + compatible = "st,stm32-iio-timer6";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer7: mfdtimer7@40001400 {
> + compatible = "st,stm32-mfd-timer7";
> + reg = <0x40001400 0x400>;
> + clocks = <&rcc 0 133>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <55>;
> + status = "disabled";
> +
> + iiotimer7: iiotimer7@40001400 {
> + compatible = "st,stm32-iio-timer7";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer8: mfdtimer8@40010400 {
> + compatible = "st,stm32-mfd-timer8";
> + reg = <0x40010400 0x400>;
> + clocks = <&rcc 0 161>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <46>;
> + status = "disabled";
> +
> + pwm8: pwm8@40010400 {
> + compatible = "st,stm32-pwm8";
> + status = "disabled";
> + };
> +
> + iiotimer8: iiotimer7@40010400 {
> + compatible = "st,stm32-iio-timer8";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer9: mfdtimer9@40014000 {
> + compatible = "st,stm32-mfd-timer9";
> + reg = <0x40014000 0x400>;
> + clocks = <&rcc 0 176>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <24>;
> + status = "disabled";
> +
> + pwm9: pwm9@40014000 {
> + compatible = "st,stm32-pwm9";
> + status = "disabled";
> + };
> +
> + iiotimer9: iiotimer9@40014000 {
> + compatible = "st,stm32-iio-timer9";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer10: mfdtimer10@40014400 {
> + compatible = "st,stm32-mfd-timer10";
> + reg = <0x40014400 0x400>;
> + clocks = <&rcc 0 177>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <25>;
> + status = "disabled";
> +
> + pwm10: pwm10@40014400 {
> + compatible = "st,stm32-pwm10";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer11: mfdtimer11@40014800 {
> + compatible = "st,stm32-mfd-timer11";
> + reg = <0x40014800 0x400>;
> + clocks = <&rcc 0 178>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <26>;
> + status = "disabled";
> +
> + pwm11: pwm11@40014800 {
> + compatible = "st,stm32-pwm11";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer12: mfdtimer12@40001800 {
> + compatible = "st,stm32-mfd-timer12";
> + reg = <0x40001800 0x400>;
> + clocks = <&rcc 0 134>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <43>;
> + status = "disabled";
> +
> + pwm12: pwm12@40001800 {
> + compatible = "st,stm32-pwm12";
> + status = "disabled";
> + };
> + iiotimer12: iiotimer12@40001800 {
> + compatible = "st,stm32-iio-timer12";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer13: mfdtimer13@40001C00 {
> + compatible = "st,stm32-mfd-timer13";
> + reg = <0x40001C00 0x400>;
> + clocks = <&rcc 0 135>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <44>;
> + status = "disabled";
> +
> + pwm13: pwm13@40001C00 {
> + compatible = "st,stm32-pwm13";
> + status = "disabled";
> + };
> + };
> +
> + mfd_timer14: mfdtimer14@40002000 {
> + compatible = "st,stm32-mfd-timer14";
> + reg = <0x40002000 0x400>;
> + clocks = <&rcc 0 136>;
> + clock-names = "mfd_timer_clk";
> + interrupts = <45>;
> + status = "disabled";
> +
> + pwm14: pwm14@40002000 {
> + compatible = "st,stm32-pwm14";
> + status = "disabled";
> + };
> + };
> };
> };
>
> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
> index 8a163d7..a8f1788 100644
> --- a/arch/arm/boot/dts/stm32f469-disco.dts
> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
> @@ -81,3 +81,32 @@
> &usart3 {
> status = "okay";
> };
> +
> +&mfd_timer1 {
> + status = "okay";
> +};
> +
> +&pwm1 {
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + st,breakinput-polarity = <0>;
Is this documented?
I'm sure we have generic polarity properties somewhere already?
> + status = "okay";
> +};
> +
> +&iiotimer1 {
> + status = "okay";
> +};
> +
> +&mfd_timer3 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + pinctrl-0 = <&pwm3_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&iiotimer3 {
> + status = "okay";
> +};
I've always disliked this way of referencing nodes!
Any chance we can represent them in a hierarchy, so we don't lose that
information and we can get rid of all those horrible labels?
I'm happy to do the work.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Benjamin Gaignard <benjamin.gaignard@linaro.org> |
|---|---|
| Date | 2016-11-22 17:30 +0100 |
| Subject | [PATCH 2/7] add MFD for stm32 timer IP |
| Message-ID | <sGm7g-1bI-15@gated-at.bofh.it> |
| In reply to | #1527652 |
This hardware block could at used at same time for PWM generation
and IIO timer for other IPs like DAC, ADC or other timers.
PWM and IIO timer configuration are mixed in the same registers
so we need a MFD to be able to share those registers.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile | 2 +
drivers/mfd/stm32-mfd-timer.c | 236 ++++++++++++++++++++++++++++++++++++
include/linux/mfd/stm32-mfd-timer.h | 78 ++++++++++++
4 files changed, 326 insertions(+)
create mode 100644 drivers/mfd/stm32-mfd-timer.c
create mode 100644 include/linux/mfd/stm32-mfd-timer.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..63aee36 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1607,6 +1607,15 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_STM32_TIMER
+ tristate "Support for STM32 multifunctions timer"
+ select MFD_CORE
+ select REGMAP
+ depends on ARCH_STM32
+ depends on OF
+ help
+ Select multifunction driver (pwm, IIO trigger) for stm32 timers
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
@@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
on the ARM Ltd. Versatile Express board.
endmenu
+
endif
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..b348c3e 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
+
+obj-$(CONFIG_MFD_STM32_TIMER) += stm32-mfd-timer.o
diff --git a/drivers/mfd/stm32-mfd-timer.c b/drivers/mfd/stm32-mfd-timer.c
new file mode 100644
index 0000000..67e7db3
--- /dev/null
+++ b/drivers/mfd/stm32-mfd-timer.c
@@ -0,0 +1,236 @@
+/*
+ * stm32-timer.c
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <linux/mfd/stm32-mfd-timer.h>
+
+static const struct stm32_mfd_timer_cfg mfd_cells_cfg[] = {
+ {
+ .pwm_name = "pwm1",
+ .pwm_compatible = "st,stm32-pwm1",
+ .trigger_name = "iiotimer1",
+ .trigger_compatible = "st,stm32-iio-timer1",
+ },
+ {
+ .pwm_name = "pwm2",
+ .pwm_compatible = "st,stm32-pwm2",
+ .trigger_name = "iiotimer2",
+ .trigger_compatible = "st,stm32-iio-timer2",
+ },
+ {
+ .pwm_name = "pwm3",
+ .pwm_compatible = "st,stm32-pwm3",
+ .trigger_name = "iiotimer3",
+ .trigger_compatible = "st,stm32-iio-timer3",
+ },
+ {
+ .pwm_name = "pwm4",
+ .pwm_compatible = "st,stm32-pwm4",
+ .trigger_name = "iiotimer4",
+ .trigger_compatible = "st,stm32-iio-timer4",
+ },
+ {
+ .pwm_name = "pwm5",
+ .pwm_compatible = "st,stm32-pwm5",
+ .trigger_name = "iiotimer5",
+ .trigger_compatible = "st,stm32-iio-timer5",
+ },
+ {
+ .trigger_name = "iiotimer6",
+ .trigger_compatible = "st,stm32-iio-timer6",
+ },
+ {
+ .trigger_name = "iiotimer7",
+ .trigger_compatible = "st,stm32-iio-timer7",
+ },
+ {
+ .pwm_name = "pwm8",
+ .pwm_compatible = "st,stm32-pwm8",
+ .trigger_name = "iiotimer8",
+ .trigger_compatible = "st,stm32-iio-timer8",
+ },
+ {
+ .pwm_name = "pwm9",
+ .pwm_compatible = "st,stm32-pwm9",
+ .trigger_name = "iiotimer9",
+ .trigger_compatible = "st,stm32-iio-timer9",
+ },
+ {
+ .pwm_name = "pwm10",
+ .pwm_compatible = "st,stm32-pwm10",
+ },
+ {
+ .pwm_name = "pwm11",
+ .pwm_compatible = "st,stm32-pwm11",
+ },
+ {
+ .pwm_name = "pwm12",
+ .pwm_compatible = "st,stm32-pwm12",
+ .trigger_name = "iiotimer12",
+ .trigger_compatible = "st,stm32-iio-timer12",
+ },
+ {
+ .pwm_name = "pwm13",
+ .pwm_compatible = "st,stm32-pwm13",
+ },
+ {
+ .pwm_name = "pwm14",
+ .pwm_compatible = "st,stm32-pwm14",
+ },
+};
+
+static const struct of_device_id stm32_timer_of_match[] = {
+ {
+ .compatible = "st,stm32-mfd-timer1",
+ .data = &mfd_cells_cfg[0],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer2",
+ .data = &mfd_cells_cfg[1],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer3",
+ .data = &mfd_cells_cfg[2],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer4",
+ .data = &mfd_cells_cfg[3],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer5",
+ .data = &mfd_cells_cfg[4],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer6",
+ .data = &mfd_cells_cfg[5],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer7",
+ .data = &mfd_cells_cfg[6],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer8",
+ .data = &mfd_cells_cfg[7],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer9",
+ .data = &mfd_cells_cfg[8],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer10",
+ .data = &mfd_cells_cfg[9],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer11",
+ .data = &mfd_cells_cfg[10],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer12",
+ .data = &mfd_cells_cfg[11],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer13",
+ .data = &mfd_cells_cfg[12],
+ },
+ {
+ .compatible = "st,stm32-mfd-timer14",
+ .data = &mfd_cells_cfg[13],
+ },
+};
+
+static const struct regmap_config stm32_timer_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = sizeof(u32),
+ .max_register = 0x400,
+ .fast_io = true,
+};
+
+static int stm32_mfd_timer_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct stm32_mfd_timer_dev *mfd;
+ struct resource *res;
+ int ret, nb_cells = 0;
+ struct mfd_cell *cell = NULL;
+ void __iomem *mmio;
+
+ mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
+ if (!mfd)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOMEM;
+
+ mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mmio))
+ return PTR_ERR(mmio);
+
+ mfd->regmap = devm_regmap_init_mmio_clk(dev, "mfd_timer_clk", mmio,
+ &stm32_timer_regmap_cfg);
+ if (IS_ERR(mfd->regmap))
+ return PTR_ERR(mfd->regmap);
+
+ mfd->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(mfd->clk))
+ return PTR_ERR(mfd->clk);
+
+ mfd->irq = platform_get_irq(pdev, 0);
+ if (mfd->irq < 0)
+ return -EINVAL;
+
+ /* populate data structure depending on compatibility */
+ if (!of_match_node(stm32_timer_of_match, np)->data)
+ return -EINVAL;
+
+ mfd->cfg =
+ (struct stm32_mfd_timer_cfg *)of_match_node(stm32_timer_of_match, np)->data;
+
+ if (mfd->cfg->pwm_name && mfd->cfg->pwm_compatible) {
+ cell = &mfd->cells[nb_cells++];
+ cell->name = mfd->cfg->pwm_name;
+ cell->of_compatible = mfd->cfg->pwm_compatible;
+ cell->platform_data = mfd;
+ cell->pdata_size = sizeof(*mfd);
+ }
+
+ if (mfd->cfg->trigger_name && mfd->cfg->trigger_compatible) {
+ cell = &mfd->cells[nb_cells++];
+ cell->name = mfd->cfg->trigger_name;
+ cell->of_compatible = mfd->cfg->trigger_compatible;
+ cell->platform_data = mfd;
+ cell->pdata_size = sizeof(*mfd);
+ }
+
+ ret = devm_mfd_add_devices(&pdev->dev, pdev->id, mfd->cells,
+ nb_cells, NULL, 0, NULL);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, mfd);
+
+ return 0;
+}
+
+static struct platform_driver stm32_mfd_timer_driver = {
+ .probe = stm32_mfd_timer_probe,
+ .driver = {
+ .name = "stm32-mfd-timer",
+ .of_match_table = stm32_timer_of_match,
+ },
+};
+module_platform_driver(stm32_mfd_timer_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics STM32 Timer MFD");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/stm32-mfd-timer.h b/include/linux/mfd/stm32-mfd-timer.h
new file mode 100644
index 0000000..4a79c22
--- /dev/null
+++ b/include/linux/mfd/stm32-mfd-timer.h
@@ -0,0 +1,78 @@
+/*
+ * stm32-mfd-timer.h
+ *
+ * Copyright (C) STMicroelectronics 2016
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LINUX_MFD_STM32_TIMER_H_
+#define _LINUX_MFD_STM32_TIMER_H_
+
+#include <linux/clk.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define TIM_CR1 0x00 /* Control Register 1 */
+#define TIM_CR2 0x04 /* Control Register 2 */
+#define TIM_SMCR 0x08 /* Slave mode control reg */
+#define TIM_DIER 0x0C /* DMA/interrupt register */
+#define TIM_SR 0x10 /* Status register */
+#define TIM_EGR 0x14 /* Event Generation Reg */
+#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
+#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
+#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
+#define TIM_PSC 0x28 /* Prescaler */
+#define TIM_ARR 0x2c /* Auto-Reload Register */
+#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
+#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
+#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
+#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
+#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
+
+#define TIM_CR1_CEN BIT(0) /* Counter Enable */
+#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
+#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
+#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
+#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
+#define TIM_DIER_UIE BIT(0) /* Update interrupt */
+#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
+#define TIM_EGR_UG BIT(0) /* Update Generation */
+#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
+#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
+#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
+#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
+#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
+#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
+#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
+#define TIM_BDTR_BKE BIT(12) /* Break input enable */
+#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
+#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
+#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
+
+#define STM32_TIMER_CELLS 2
+#define MAX_TIM_PSC 0xFFFF
+
+struct stm32_mfd_timer_cfg {
+ const char *pwm_name;
+ const char *pwm_compatible;
+ const char *trigger_name;
+ const char *trigger_compatible;
+};
+
+struct stm32_mfd_timer_dev {
+ /* Device data */
+ struct device *dev;
+ struct clk *clk;
+ int irq;
+
+ /* Registers mapping */
+ struct regmap *regmap;
+
+ /* Private data */
+ struct mfd_cell cells[STM32_TIMER_CELLS];
+ struct stm32_mfd_timer_cfg *cfg;
+};
+
+#endif
--
1.9.1
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