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Re: [PATCH] Support for perf on AMD family17h processors

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  Re: [PATCH] Support for perf on AMD family17h processors Borislav Petkov <bp@alien8.de> - 2016-11-16 19:50 +0100

#1523745 — Re: [PATCH] Support for perf on AMD family17h processors

On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
> This patch enables perf core PMU support for AMD family17h processors.
> In family17h, there is no PMC-event constraint. All events, irrespective
> of the type, can be measured using any of the performance counters.
> 
> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
> ---
>  arch/x86/events/amd/core.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index f5f4b3f..849688d 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -652,7 +652,11 @@ static __initconst const struct x86_pmu amd_pmu = {
>  	.amd_nb_constraints	= 1,
>  };
>  
> -static int __init amd_core_pmu_init(void)
> +/*
> + * This function initializes core PMU to enable support
> + * for AMD Core PMC Extension.
> + */
> +static int __init amd_core_pmc_ext_init(void)
>  {
>  	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
>  		return 0;

This renaming looks pretty useless to me. So does the comment.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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