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[PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

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  [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-11-14 11:30 +0100
    [PATCH v5 2/3] mfd: lpc_ich: Add support for SPI serial flash host controller Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-11-14 11:30 +0100
    Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash  controller Lee Jones <lee.jones@linaro.org> - 2016-11-18 20:10 +0100
      Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash  controller Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-11-19 08:50 +0100
        Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash  controller Boris Brezillon <boris.brezillon@free-electrons.com> - 2016-11-19 09:10 +0100
          Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash  controller Lee Jones <lee.jones@linaro.org> - 2016-11-21 11:50 +0100
            Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash  controller Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-11-22 11:30 +0100

#1521509 — [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

This is fifth version of the series. You can find the previous versions
archived on:

  v4: https://lwn.net/Articles/703773/
  v3: https://lwn.net/Articles/697231/
  v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
  v1: https://lkml.org/lkml/2016/6/14/269

This patch series adds support for the Intel SPI serial flash controller
found on many recent Intel CPUs including Baytrail and Braswell. This
driver makes it possible to access the BIOS and other platform data which
is stored on the SPI serial flash. It is also possible to upgrade the BIOS
using this driver if it has not been protected by special hardware bits.

The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
MAX.

Since poking the SPI serial flash can brick the machine, this driver can
only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
unless instructed othwerwise by module parameter.

Changes from v4:
  * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
  * Don't increment i inside call to FDATA() macro
  * Check nor->read_opcode in intel_spi_read() and return
    -EINVAL if not supported. We may add SFDP support later on.

Changes from v3:
  * Added ACKs from Lee Jones.
  * Use bus instead of dev->bus in PCI accesses

Changes from v2:
  * Rebased on top of v4.8-rc2
  * Updated intel_spi_read/write() according spi-nor core changes which
    drops retlen parameter and returns number of bytes read/written.

Changes from v1:
  * Older hardware does not support 64k erase command so added erase_64k
    flag which is set only for Broxton (BXT).
  * Fix protection range offset for Broxton. Now there is ispi->pregs
    pointing to the start of the protection registers.
  * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
  * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
    lpc_ich_init_spi().
  * Use info->type in switch in lpc_ich_init_spi().
  * Add defines for magic numbers used in lpc_ich_init_spi().
  * Use PLATFORM_DEVID_NONE with mfd_add_devices().

Mika Westerberg (3):
  spi-nor: Add support for Intel SPI serial flash controller
  mfd: lpc_ich: Add support for SPI serial flash host controller
  mfd: lpc_ich: Add support for Intel Apollo Lake SoC

 Documentation/mtd/intel-spi.txt          |  88 ++++
 drivers/mfd/lpc_ich.c                    | 131 +++++
 drivers/mtd/spi-nor/Kconfig              |  20 +
 drivers/mtd/spi-nor/Makefile             |   2 +
 drivers/mtd/spi-nor/intel-spi-platform.c |  57 +++
 drivers/mtd/spi-nor/intel-spi.c          | 791 +++++++++++++++++++++++++++++++
 drivers/mtd/spi-nor/intel-spi.h          |  24 +
 include/linux/mfd/lpc_ich.h              |   3 +
 include/linux/platform_data/intel-spi.h  |  31 ++
 9 files changed, 1147 insertions(+)
 create mode 100644 Documentation/mtd/intel-spi.txt
 create mode 100644 drivers/mtd/spi-nor/intel-spi-platform.c
 create mode 100644 drivers/mtd/spi-nor/intel-spi.c
 create mode 100644 drivers/mtd/spi-nor/intel-spi.h
 create mode 100644 include/linux/platform_data/intel-spi.h

-- 
2.9.3

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#1521510 — [PATCH v5 2/3] mfd: lpc_ich: Add support for SPI serial flash host controller

Many Intel CPUs including Haswell, Broadwell and Baytrail have SPI serial
flash host controller as part of the LPC device. This will populate an MFD
cell suitable for the SPI host controller driver if we know that the LPC
device has one.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/lpc_ich.c       | 92 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/lpc_ich.h |  3 ++
 2 files changed, 95 insertions(+)

diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index c8dee47b45d9..985bda575849 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -83,6 +83,15 @@
 #define ACPIBASE_GCS_OFF	0x3410
 #define ACPIBASE_GCS_END	0x3414
 
+#define SPIBASE_BYT		0x54
+#define SPIBASE_BYT_SZ		512
+#define SPIBASE_BYT_EN		BIT(1)
+
+#define SPIBASE_LPT		0x3800
+#define SPIBASE_LPT_SZ		512
+#define BCR			0xdc
+#define BCR_WPD			BIT(0)
+
 #define GPIOBASE_ICH0		0x58
 #define GPIOCTRL_ICH0		0x5C
 #define GPIOBASE_ICH6		0x48
@@ -133,6 +142,12 @@ static struct resource gpio_ich_res[] = {
 	},
 };
 
+static struct resource intel_spi_res[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	}
+};
+
 static struct mfd_cell lpc_ich_wdt_cell = {
 	.name = "iTCO_wdt",
 	.num_resources = ARRAY_SIZE(wdt_ich_res),
@@ -147,6 +162,14 @@ static struct mfd_cell lpc_ich_gpio_cell = {
 	.ignore_resource_conflicts = true,
 };
 
+
+static struct mfd_cell lpc_ich_spi_cell = {
+	.name = "intel-spi",
+	.num_resources = ARRAY_SIZE(intel_spi_res),
+	.resources = intel_spi_res,
+	.ignore_resource_conflicts = true,
+};
+
 /* chipset related info */
 enum lpc_chipsets {
 	LPC_ICH = 0,	/* ICH */
@@ -493,10 +516,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_LPT] = {
 		.name = "Lynx Point",
 		.iTCO_version = 2,
+		.spi_type = INTEL_SPI_LPT,
 	},
 	[LPC_LPT_LP] = {
 		.name = "Lynx Point_LP",
 		.iTCO_version = 2,
+		.spi_type = INTEL_SPI_LPT,
 	},
 	[LPC_WBG] = {
 		.name = "Wellsburg",
@@ -510,6 +535,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_BAYTRAIL] = {
 		.name = "Bay Trail SoC",
 		.iTCO_version = 3,
+		.spi_type = INTEL_SPI_BYT,
 	},
 	[LPC_COLETO] = {
 		.name = "Coleto Creek",
@@ -518,10 +544,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_WPT_LP] = {
 		.name = "Wildcat Point_LP",
 		.iTCO_version = 2,
+		.spi_type = INTEL_SPI_LPT,
 	},
 	[LPC_BRASWELL] = {
 		.name = "Braswell SoC",
 		.iTCO_version = 3,
+		.spi_type = INTEL_SPI_BYT,
 	},
 	[LPC_LEWISBURG] = {
 		.name = "Lewisburg",
@@ -1054,6 +1082,64 @@ static int lpc_ich_init_wdt(struct pci_dev *dev)
 	return ret;
 }
 
+static int lpc_ich_init_spi(struct pci_dev *dev)
+{
+	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
+	struct resource *res = &intel_spi_res[0];
+	struct intel_spi_boardinfo *info;
+	u32 spi_base, rcba, bcr;
+
+	info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->type = lpc_chipset_info[priv->chipset].spi_type;
+
+	switch (info->type) {
+	case INTEL_SPI_BYT:
+		pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
+		if (spi_base & SPIBASE_BYT_EN) {
+			res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
+			res->end = res->start + SPIBASE_BYT_SZ - 1;
+		}
+		break;
+
+	case INTEL_SPI_LPT:
+		pci_read_config_dword(dev, RCBABASE, &rcba);
+		if (rcba & 1) {
+			spi_base = rcba & ~(SPIBASE_LPT_SZ - 1);
+			res->start = spi_base + SPIBASE_LPT;
+			res->end = res->start + SPIBASE_LPT_SZ - 1;
+
+			/*
+			 * Try to make the flash chip writeable now by
+			 * setting BCR_WPD. It it fails we tell the driver
+			 * that it can only read the chip.
+			 */
+			pci_read_config_dword(dev, BCR, &bcr);
+			if (!(bcr & BCR_WPD)) {
+				bcr |= BCR_WPD;
+				pci_write_config_dword(dev, BCR, bcr);
+				pci_read_config_dword(dev, BCR, &bcr);
+			}
+			info->writeable = !!(bcr & BCR_WPD);
+		}
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (!res->start)
+		return -ENODEV;
+
+	lpc_ich_spi_cell.platform_data = info;
+	lpc_ich_spi_cell.pdata_size = sizeof(*info);
+
+	return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
+			       &lpc_ich_spi_cell, 1, NULL, 0, NULL);
+}
+
 static int lpc_ich_probe(struct pci_dev *dev,
 				const struct pci_device_id *id)
 {
@@ -1097,6 +1183,12 @@ static int lpc_ich_probe(struct pci_dev *dev,
 			cell_added = true;
 	}
 
+	if (lpc_chipset_info[priv->chipset].spi_type) {
+		ret = lpc_ich_init_spi(dev);
+		if (!ret)
+			cell_added = true;
+	}
+
 	/*
 	 * We only care if at least one or none of the cells registered
 	 * successfully.
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b44f994..fba8fcb54f8c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -20,6 +20,8 @@
 #ifndef LPC_ICH_H
 #define LPC_ICH_H
 
+#include <linux/platform_data/intel-spi.h>
+
 /* GPIO resources */
 #define ICH_RES_GPIO	0
 #define ICH_RES_GPE0	1
@@ -40,6 +42,7 @@ struct lpc_ich_info {
 	char name[32];
 	unsigned int iTCO_version;
 	unsigned int gpio_version;
+	enum intel_spi_type spi_type;
 	u8 use_gpio;
 };
 
-- 
2.9.3

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#1525660 — Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

On Mon, 14 Nov 2016, Mika Westerberg wrote:

> This is fifth version of the series. You can find the previous versions
> archived on:
> 
>   v4: https://lwn.net/Articles/703773/
>   v3: https://lwn.net/Articles/697231/
>   v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
>   v1: https://lkml.org/lkml/2016/6/14/269
> 
> This patch series adds support for the Intel SPI serial flash controller
> found on many recent Intel CPUs including Baytrail and Braswell. This
> driver makes it possible to access the BIOS and other platform data which
> is stored on the SPI serial flash. It is also possible to upgrade the BIOS
> using this driver if it has not been protected by special hardware bits.
> 
> The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
> MAX.
> 
> Since poking the SPI serial flash can brick the machine, this driver can
> only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
> unless instructed othwerwise by module parameter.
> 
> Changes from v4:
>   * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
>   * Don't increment i inside call to FDATA() macro
>   * Check nor->read_opcode in intel_spi_read() and return
>     -EINVAL if not supported. We may add SFDP support later on.
> 
> Changes from v3:
>   * Added ACKs from Lee Jones.
>   * Use bus instead of dev->bus in PCI accesses
> 
> Changes from v2:
>   * Rebased on top of v4.8-rc2
>   * Updated intel_spi_read/write() according spi-nor core changes which
>     drops retlen parameter and returns number of bytes read/written.
> 
> Changes from v1:
>   * Older hardware does not support 64k erase command so added erase_64k
>     flag which is set only for Broxton (BXT).
>   * Fix protection range offset for Broxton. Now there is ispi->pregs
>     pointing to the start of the protection registers.
>   * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
>   * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
>     lpc_ich_init_spi().
>   * Use info->type in switch in lpc_ich_init_spi().
>   * Add defines for magic numbers used in lpc_ich_init_spi().
>   * Use PLATFORM_DEVID_NONE with mfd_add_devices().
> 
> Mika Westerberg (3):
>   spi-nor: Add support for Intel SPI serial flash controller
>   mfd: lpc_ich: Add support for SPI serial flash host controller
>   mfd: lpc_ich: Add support for Intel Apollo Lake SoC

What's the plan for this set?

>  Documentation/mtd/intel-spi.txt          |  88 ++++
>  drivers/mfd/lpc_ich.c                    | 131 +++++
>  drivers/mtd/spi-nor/Kconfig              |  20 +
>  drivers/mtd/spi-nor/Makefile             |   2 +
>  drivers/mtd/spi-nor/intel-spi-platform.c |  57 +++
>  drivers/mtd/spi-nor/intel-spi.c          | 791 +++++++++++++++++++++++++++++++
>  drivers/mtd/spi-nor/intel-spi.h          |  24 +
>  include/linux/mfd/lpc_ich.h              |   3 +
>  include/linux/platform_data/intel-spi.h  |  31 ++
>  9 files changed, 1147 insertions(+)
>  create mode 100644 Documentation/mtd/intel-spi.txt
>  create mode 100644 drivers/mtd/spi-nor/intel-spi-platform.c
>  create mode 100644 drivers/mtd/spi-nor/intel-spi.c
>  create mode 100644 drivers/mtd/spi-nor/intel-spi.h
>  create mode 100644 include/linux/platform_data/intel-spi.h
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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#1525867 — Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

On Fri, Nov 18, 2016 at 07:04:26PM +0000, Lee Jones wrote:
> On Mon, 14 Nov 2016, Mika Westerberg wrote:
> 
> > This is fifth version of the series. You can find the previous versions
> > archived on:
> > 
> >   v4: https://lwn.net/Articles/703773/
> >   v3: https://lwn.net/Articles/697231/
> >   v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
> >   v1: https://lkml.org/lkml/2016/6/14/269
> > 
> > This patch series adds support for the Intel SPI serial flash controller
> > found on many recent Intel CPUs including Baytrail and Braswell. This
> > driver makes it possible to access the BIOS and other platform data which
> > is stored on the SPI serial flash. It is also possible to upgrade the BIOS
> > using this driver if it has not been protected by special hardware bits.
> > 
> > The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
> > MAX.
> > 
> > Since poking the SPI serial flash can brick the machine, this driver can
> > only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
> > unless instructed othwerwise by module parameter.
> > 
> > Changes from v4:
> >   * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
> >   * Don't increment i inside call to FDATA() macro
> >   * Check nor->read_opcode in intel_spi_read() and return
> >     -EINVAL if not supported. We may add SFDP support later on.
> > 
> > Changes from v3:
> >   * Added ACKs from Lee Jones.
> >   * Use bus instead of dev->bus in PCI accesses
> > 
> > Changes from v2:
> >   * Rebased on top of v4.8-rc2
> >   * Updated intel_spi_read/write() according spi-nor core changes which
> >     drops retlen parameter and returns number of bytes read/written.
> > 
> > Changes from v1:
> >   * Older hardware does not support 64k erase command so added erase_64k
> >     flag which is set only for Broxton (BXT).
> >   * Fix protection range offset for Broxton. Now there is ispi->pregs
> >     pointing to the start of the protection registers.
> >   * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
> >   * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
> >     lpc_ich_init_spi().
> >   * Use info->type in switch in lpc_ich_init_spi().
> >   * Add defines for magic numbers used in lpc_ich_init_spi().
> >   * Use PLATFORM_DEVID_NONE with mfd_add_devices().
> > 
> > Mika Westerberg (3):
> >   spi-nor: Add support for Intel SPI serial flash controller
> >   mfd: lpc_ich: Add support for SPI serial flash host controller
> >   mfd: lpc_ich: Add support for Intel Apollo Lake SoC
> 
> What's the plan for this set?

I was hoping to get this merged via MTD tree but I haven't got much
comments from the maintainers. No idea if anyone is going to take this :-(

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#1525869 — Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

On Sat, 19 Nov 2016 09:35:46 +0200
Mika Westerberg <mika.westerberg@linux.intel.com> wrote:

> On Fri, Nov 18, 2016 at 07:04:26PM +0000, Lee Jones wrote:
> > On Mon, 14 Nov 2016, Mika Westerberg wrote:
> >   
> > > This is fifth version of the series. You can find the previous versions
> > > archived on:
> > > 
> > >   v4: https://lwn.net/Articles/703773/
> > >   v3: https://lwn.net/Articles/697231/
> > >   v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
> > >   v1: https://lkml.org/lkml/2016/6/14/269
> > > 
> > > This patch series adds support for the Intel SPI serial flash controller
> > > found on many recent Intel CPUs including Baytrail and Braswell. This
> > > driver makes it possible to access the BIOS and other platform data which
> > > is stored on the SPI serial flash. It is also possible to upgrade the BIOS
> > > using this driver if it has not been protected by special hardware bits.
> > > 
> > > The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
> > > MAX.
> > > 
> > > Since poking the SPI serial flash can brick the machine, this driver can
> > > only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
> > > unless instructed othwerwise by module parameter.
> > > 
> > > Changes from v4:
> > >   * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
> > >   * Don't increment i inside call to FDATA() macro
> > >   * Check nor->read_opcode in intel_spi_read() and return
> > >     -EINVAL if not supported. We may add SFDP support later on.
> > > 
> > > Changes from v3:
> > >   * Added ACKs from Lee Jones.
> > >   * Use bus instead of dev->bus in PCI accesses
> > > 
> > > Changes from v2:
> > >   * Rebased on top of v4.8-rc2
> > >   * Updated intel_spi_read/write() according spi-nor core changes which
> > >     drops retlen parameter and returns number of bytes read/written.
> > > 
> > > Changes from v1:
> > >   * Older hardware does not support 64k erase command so added erase_64k
> > >     flag which is set only for Broxton (BXT).
> > >   * Fix protection range offset for Broxton. Now there is ispi->pregs
> > >     pointing to the start of the protection registers.
> > >   * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
> > >   * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
> > >     lpc_ich_init_spi().
> > >   * Use info->type in switch in lpc_ich_init_spi().
> > >   * Add defines for magic numbers used in lpc_ich_init_spi().
> > >   * Use PLATFORM_DEVID_NONE with mfd_add_devices().
> > > 
> > > Mika Westerberg (3):
> > >   spi-nor: Add support for Intel SPI serial flash controller
> > >   mfd: lpc_ich: Add support for SPI serial flash host controller
> > >   mfd: lpc_ich: Add support for Intel Apollo Lake SoC  
> > 
> > What's the plan for this set?  
> 
> I was hoping to get this merged via MTD tree but I haven't got much
> comments from the maintainers. No idea if anyone is going to take this :-(

Marek, Cyrille, can you take a look?

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#1526554 — Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

On Sat, 19 Nov 2016, Boris Brezillon wrote:

> On Sat, 19 Nov 2016 09:35:46 +0200
> Mika Westerberg <mika.westerberg@linux.intel.com> wrote:
> 
> > On Fri, Nov 18, 2016 at 07:04:26PM +0000, Lee Jones wrote:
> > > On Mon, 14 Nov 2016, Mika Westerberg wrote:
> > >   
> > > > This is fifth version of the series. You can find the previous versions
> > > > archived on:
> > > > 
> > > >   v4: https://lwn.net/Articles/703773/
> > > >   v3: https://lwn.net/Articles/697231/
> > > >   v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
> > > >   v1: https://lkml.org/lkml/2016/6/14/269
> > > > 
> > > > This patch series adds support for the Intel SPI serial flash controller
> > > > found on many recent Intel CPUs including Baytrail and Braswell. This
> > > > driver makes it possible to access the BIOS and other platform data which
> > > > is stored on the SPI serial flash. It is also possible to upgrade the BIOS
> > > > using this driver if it has not been protected by special hardware bits.
> > > > 
> > > > The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
> > > > MAX.
> > > > 
> > > > Since poking the SPI serial flash can brick the machine, this driver can
> > > > only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
> > > > unless instructed othwerwise by module parameter.
> > > > 
> > > > Changes from v4:
> > > >   * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
> > > >   * Don't increment i inside call to FDATA() macro
> > > >   * Check nor->read_opcode in intel_spi_read() and return
> > > >     -EINVAL if not supported. We may add SFDP support later on.
> > > > 
> > > > Changes from v3:
> > > >   * Added ACKs from Lee Jones.
> > > >   * Use bus instead of dev->bus in PCI accesses
> > > > 
> > > > Changes from v2:
> > > >   * Rebased on top of v4.8-rc2
> > > >   * Updated intel_spi_read/write() according spi-nor core changes which
> > > >     drops retlen parameter and returns number of bytes read/written.
> > > > 
> > > > Changes from v1:
> > > >   * Older hardware does not support 64k erase command so added erase_64k
> > > >     flag which is set only for Broxton (BXT).
> > > >   * Fix protection range offset for Broxton. Now there is ispi->pregs
> > > >     pointing to the start of the protection registers.
> > > >   * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
> > > >   * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
> > > >     lpc_ich_init_spi().
> > > >   * Use info->type in switch in lpc_ich_init_spi().
> > > >   * Add defines for magic numbers used in lpc_ich_init_spi().
> > > >   * Use PLATFORM_DEVID_NONE with mfd_add_devices().
> > > > 
> > > > Mika Westerberg (3):
> > > >   spi-nor: Add support for Intel SPI serial flash controller
> > > >   mfd: lpc_ich: Add support for SPI serial flash host controller
> > > >   mfd: lpc_ich: Add support for Intel Apollo Lake SoC  
> > > 
> > > What's the plan for this set?  
> > 
> > I was hoping to get this merged via MTD tree but I haven't got much
> > comments from the maintainers. No idea if anyone is going to take this :-(
> 
> Marek, Cyrille, can you take a look?

I can push through MFD, no problem.

I just need Acks from all subsystems concerned.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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#1527377 — Re: [PATCH v5 0/3] spi-nor: Add support for Intel SPI serial flash controller

Hi all,

Le 21/11/2016 à 11:51, Lee Jones a écrit :
> On Sat, 19 Nov 2016, Boris Brezillon wrote:
> 
>> On Sat, 19 Nov 2016 09:35:46 +0200
>> Mika Westerberg <mika.westerberg@linux.intel.com> wrote:
>>
>>> On Fri, Nov 18, 2016 at 07:04:26PM +0000, Lee Jones wrote:
>>>> On Mon, 14 Nov 2016, Mika Westerberg wrote:
>>>>   
>>>>> This is fifth version of the series. You can find the previous versions
>>>>> archived on:
>>>>>
>>>>>   v4: https://lwn.net/Articles/703773/
>>>>>   v3: https://lwn.net/Articles/697231/
>>>>>   v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
>>>>>   v1: https://lkml.org/lkml/2016/6/14/269
>>>>>
>>>>> This patch series adds support for the Intel SPI serial flash controller
>>>>> found on many recent Intel CPUs including Baytrail and Braswell. This
>>>>> driver makes it possible to access the BIOS and other platform data which
>>>>> is stored on the SPI serial flash. It is also possible to upgrade the BIOS
>>>>> using this driver if it has not been protected by special hardware bits.
>>>>>
>>>>> The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
>>>>> MAX.
>>>>>
>>>>> Since poking the SPI serial flash can brick the machine, this driver can
>>>>> only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
>>>>> unless instructed othwerwise by module parameter.
>>>>>
>>>>> Changes from v4:
>>>>>   * Use INTEL_SPI_FIFO_SZ instead of hard coded value of 64 bytes
>>>>>   * Don't increment i inside call to FDATA() macro
>>>>>   * Check nor->read_opcode in intel_spi_read() and return
>>>>>     -EINVAL if not supported. We may add SFDP support later on.
>>>>>
>>>>> Changes from v3:
>>>>>   * Added ACKs from Lee Jones.
>>>>>   * Use bus instead of dev->bus in PCI accesses
>>>>>
>>>>> Changes from v2:
>>>>>   * Rebased on top of v4.8-rc2
>>>>>   * Updated intel_spi_read/write() according spi-nor core changes which
>>>>>     drops retlen parameter and returns number of bytes read/written.
>>>>>
>>>>> Changes from v1:
>>>>>   * Older hardware does not support 64k erase command so added erase_64k
>>>>>     flag which is set only for Broxton (BXT).
>>>>>   * Fix protection range offset for Broxton. Now there is ispi->pregs
>>>>>     pointing to the start of the protection registers.
>>>>>   * Change naming of constants from BCR_BYT -> BYT_BCR and so on.
>>>>>   * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
>>>>>     lpc_ich_init_spi().
>>>>>   * Use info->type in switch in lpc_ich_init_spi().
>>>>>   * Add defines for magic numbers used in lpc_ich_init_spi().
>>>>>   * Use PLATFORM_DEVID_NONE with mfd_add_devices().
>>>>>
>>>>> Mika Westerberg (3):
>>>>>   spi-nor: Add support for Intel SPI serial flash controller
>>>>>   mfd: lpc_ich: Add support for SPI serial flash host controller
>>>>>   mfd: lpc_ich: Add support for Intel Apollo Lake SoC  
>>>>
>>>> What's the plan for this set?  
>>>
>>> I was hoping to get this merged via MTD tree but I haven't got much
>>> comments from the maintainers. No idea if anyone is going to take this :-(
>>
>> Marek, Cyrille, can you take a look?
> 
> I can push through MFD, no problem.
> 
> I just need Acks from all subsystems concerned.
> 
Marek told me he wants some more time to review on his side, so please wait
before push through MFD! :)

Best regards,

Cyrille

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