Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1518762 > unrolled thread

[PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

Started byTan Jui Nee <jui.nee.tan@intel.com>
First post2016-11-10 10:10 +0100
Last post2016-11-10 17:20 +0100
Articles 7 — 3 participants

Back to article view | Back to linux.kernel

Contents

  [PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration Tan Jui Nee <jui.nee.tan@intel.com> - 2016-11-10 10:10 +0100
    [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's Tan Jui Nee <jui.nee.tan@intel.com> - 2016-11-10 10:10 +0100
      Re: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to  Sideband bridge support driver for Intel SOC's Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-11-10 17:10 +0100
    [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system Tan Jui Nee <jui.nee.tan@intel.com> - 2016-11-10 10:10 +0100
      Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake  GPIO pinctrl in non-ACPI system kbuild test robot <lkp@intel.com> - 2016-11-10 11:50 +0100
        Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake  GPIO pinctrl in non-ACPI system Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-11-10 12:50 +0100
      Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake  GPIO pinctrl in non-ACPI system Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-11-10 17:20 +0100

#1518762 — [PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

FromTan Jui Nee <jui.nee.tan@intel.com>
Date2016-11-10 10:10 +0100
Subject[PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration
Message-ID<sBTwR-3Ar-3@gated-at.bofh.it>
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Changes in V10:
	- Since P2SB is platform enablement driver and therefore should go into
	  drivers/platform/x86 (suggested by tglx).

Changes in V9:
	- Remove the filename from the header of lpc_ich_core.c (suggested by Lee).

Changes in V8:
	- Update new file name with lpc_ich_core.c at description of source file.
	- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).
	- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
	- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
	  p2sb.c.
	- Split Kconfig option CONFIG_X86_INTEL_IVI to separate patch (suggested by
	  Lee).
	- Split new platform enabling into a separate patch.
	- Move lpc_chipsets enum's definition into a standalone header file which
	  can be used wherever its definition is needed.
	- Add author information and rewrite description of source file 
	  lpc_ich-apl.c and lpc_ich_apl.h.
	- Sort the header files by alphabetical order in lpc_ich-apl.c.
	- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
	- Remove unneeded pdata_size and platform_data from mfd_cell.
	  Also, remove unneeded apl_pinctrl_pdata.
	- Since variable apl_p2sb is only used once, hence switch it out for the
	  PCI_DEVFN macro (suggested by Lee).
	- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
	  supported.
	- Set resources in mfd_cell for each GPIO community.
	- Call p2sb_bar() function once instead of four times inside the for loop.
	  And make p2sb_bar() function just to fill in the base address into a
	  scratch "struct resource" and have the loop do the additions to base/end.
	- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
	  longer needed.
	- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
	- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
	  relates to the actual product, as suggested by Mika.
	- Rework Makefile according Andy's comments.
	- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should not
	  be so generic, as suggested by Andy.
	- Call lpc_ich_add_gpio() via priv->chipset.
	- lpc_ich_add_gpio() function will be moved from 
	  .../include/linux/mfd/lpc_ich.h to
	  .../drivers/mfd/lpc_ich-apl.h
	  as this is a part of internal driver interface as suggested by Andy.
	- Move enum lpc_chipsets from 
	  .../drivers/mfd/lpc_ich-core.c to
	  .../include/linux/mfd/lpc_ich.h
	  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
	- Check if kasprintf return value for all 4 gpio controllers before
	  proceed to add platform device by using mfd_add_devices().

Changes in V5:
	- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
	  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
	- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to CONFIG_X86_INTEL_APL
	  so that it reflects actual product as suggested by Mika.
	- The patch: 
	  [PATCH] pinctrl/broxton: enable platform device in the absent of ACPI enumeration
	  is removed in V5 patch-set as the patch is already applied in Linus' pinctrl tree.

Changes in V4:
	- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
	  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
	  to
	  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
	  since the config is used in latter patch.
	- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
	- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
	  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
	  as suggested by Lee Jones.
	- Use single dimensional array instead of 2D array for apl_gpio_io_res
	  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
	- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
	  defines for apl_gpio_io_res structure
	- Define magic number for P2SB PCI ID
	- Replace switch-case with if-else since currently we have only one
	  use case
	- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
	- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
	  to fix kbuildbot error

Andy Shevchenko (1):
  drivers/platform/x86/p2sb: New Primary to Sideband bridge support
    driver for Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
    cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
    non-ACPI system

 arch/x86/Kconfig                          |   8 ++
 arch/x86/include/asm/p2sb.h               |  27 +++++++
 drivers/mfd/Kconfig                       |   2 +
 drivers/mfd/Makefile                      |   5 ++
 drivers/mfd/lpc_ich_apl.c                 | 120 ++++++++++++++++++++++++++++++
 drivers/mfd/lpc_ich_apl.h                 |  29 ++++++++
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++------------------
 drivers/platform/x86/Kconfig              |   4 +
 drivers/platform/x86/Makefile             |   1 +
 drivers/platform/x86/p2sb.c               |  98 ++++++++++++++++++++++++
 include/linux/mfd/lpc_ich.h               |  72 ++++++++++++++++++
 11 files changed, 377 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)
 create mode 100644 drivers/platform/x86/p2sb.c

-- 
1.9.1

[toc] | [next] | [standalone]

#1518766 — [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

FromTan Jui Nee <jui.nee.tan@intel.com>
Date2016-11-10 10:10 +0100
Subject[PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
Message-ID<sBTwT-3Ar-63@gated-at.bofh.it>
In reply to#1518762
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan <jonathan.yong@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
Changes in V10:
	- Since P2SB is platform enablement driver and therefore should go into
	  drivers/platform/x86 (suggested by tglx).

Changes in V9:
	- No change

Changes in V8:
	- No change

Changes in V7:
	- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
	  p2sb.c.

Changes in V6:
	- No change

Changes in V5:
	- No change

Changes in V4:
	- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
	  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
	  to
	  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
	  since the config is used in latter patch.

Changes in V3:
	- No change

Changes in V2:
	- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
	  to fix kbuildbot error

 arch/x86/include/asm/p2sb.h   | 27 ++++++++++++
 drivers/platform/x86/Kconfig  |  4 ++
 drivers/platform/x86/Makefile |  1 +
 drivers/platform/x86/p2sb.c   | 98 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/platform/x86/p2sb.c

diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 0000000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include <linux/ioport.h>
+#include <linux/pci.h>
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+	struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+	struct resource *res)
+{
+	return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b8a21d7..65ef6a0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1027,4 +1027,8 @@ config INTEL_TELEMETRY
 	  used to get various SoC events and parameters
 	  directly via debugfs files. Various tools may use
 	  this interface for SoC state monitoring.
+
+config P2SB
+	tristate
+	depends on PCI
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 2efa86d..c39a13d 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_INTEL_TELEMETRY)	+= intel_telemetry_core.o \
 				   intel_telemetry_pltdrv.o \
 				   intel_telemetry_debugfs.o
 obj-$(CONFIG_INTEL_PMC_CORE)    += intel_pmc_core.o
+obj-$(CONFIG_P2SB)			+= p2sb.o
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
new file mode 100644
index 0000000..b1d784c
--- /dev/null
+++ b/drivers/platform/x86/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *			Jonathan Yong <jonathan.yong@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+
+#include <asm/p2sb.h>
+
+#define SBREG_BAR	0x10
+#define SBREG_HIDE	0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:	PCI device to get PCI bus to communicate with
+ * @devfn:	PCI device and function to communicate with
+ * @res:	resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+	struct resource *res)
+{
+	u32 base_addr;
+	u64 base64_addr;
+	unsigned long flags;
+
+	if (!res)
+		return -EINVAL;
+
+	spin_lock(&p2sb_spinlock);
+
+	/* Unhide the P2SB device */
+	pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+	/* Check if device present */
+	pci_bus_read_config_dword(pdev->bus, devfn, 0, &base_addr);
+	if (base_addr == 0xffffffff || base_addr == 0x00000000) {
+		spin_unlock(&p2sb_spinlock);
+		dev_warn(&pdev->dev, "P2SB device access disabled by BIOS?\n");
+		return -ENODEV;
+	}
+
+	/* Get IO or MMIO BAR */
+	pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR, &base_addr);
+	if ((base_addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+		flags = IORESOURCE_IO;
+		base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK;
+	} else {
+		flags = IORESOURCE_MEM;
+		base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK;
+		if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+			flags |= IORESOURCE_MEM_64;
+			pci_bus_read_config_dword(pdev->bus, devfn,
+				SBREG_BAR + 4, &base_addr);
+			base64_addr |= (u64)base_addr << 32;
+		}
+	}
+
+	/* Hide the P2SB device */
+	pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x01);
+
+	spin_unlock(&p2sb_spinlock);
+
+	/* User provides prefilled resources */
+	res->start = (resource_size_t)base64_addr;
+	res->flags = flags;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(p2sb_bar);
+
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1519097 — Re: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

FromAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Date2016-11-10 17:10 +0100
SubjectRe: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
Message-ID<sC05k-8tv-33@gated-at.bofh.it>
In reply to#1518766
On Thu, 2016-11-10 at 17:00 +0800, Tan Jui Nee wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> There is already one and at least one more user coming which
> require an access to Primary to Sideband bridge (P2SB) in order
> to get IO or MMIO bar hidden by BIOS.
> Create a driver to access P2SB for x86 devices.
> 
> Signed-off-by: Yong, Jonathan <jonathan.yong@intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>


> +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> +	struct resource *res)
> +{
> +	u32 base_addr;
> +	u64 base64_addr;
> +	unsigned long flags;
> +
> 

> +	if (!res)
> +		return -EINVAL;

I don't remember the details, one version was quite changed, so, I think
these lines are not needed anymore.

> +	/* Get IO or MMIO BAR */
> +	pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR,
> &base_addr);
> +	if ((base_addr & PCI_BASE_ADDRESS_SPACE) ==
> PCI_BASE_ADDRESS_SPACE_IO) {
> +		flags = IORESOURCE_IO;
> +		base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK;
> +	} else {
> +		flags = IORESOURCE_MEM;
> +		base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK;
> +		if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> +			flags |= IORESOURCE_MEM_64;
> 

> +			pci_bus_read_config_dword(pdev->bus, devfn,
> +				SBREG_BAR + 4, &base_addr);

Fix indentation.

> +			base64_addr |= (u64)base_addr << 32;
> +		}
> +	}
> +
> +	/* Hide the P2SB device */
> +	pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE,
> 0x01);
> +
> +	spin_unlock(&p2sb_spinlock);
> +

> +	/* User provides prefilled resources */

Not anymore as far I as I can see. You just return here the result.

> +	res->start = (resource_size_t)base64_addr;
> +	res->flags = flags;

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[toc] | [prev] | [next] | [standalone]

#1518767 — [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

FromTan Jui Nee <jui.nee.tan@intel.com>
Date2016-11-10 10:10 +0100
Subject[PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
Message-ID<sBTwS-3Ar-49@gated-at.bofh.it>
In reply to#1518762
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
Changes in V10:
	- No change

Changes in V9:
	- No change

Changes in V8:
	- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
	- Add author information and rewrite description of source file 
	  lpc_ich-apl.c and lpc_ich_apl.h.
	- Sort the header files by alphabetical order in lpc_ich-apl.c.
	- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
	- Remove unneeded pdata_size and platform_data from mfd_cell.
	  Also, remove unneeded apl_pinctrl_pdata.
	- Since variable apl_p2sb is only used once, hence switch it out for the
	  PCI_DEVFN macro (suggested by Lee).
	- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
	  supported.
	- Set resources in mfd_cell for each GPIO community.
	- Call p2sb_bar() function once instead of four times inside the for loop.
	  And make p2sb_bar() function just to fill in the base address into a
	  scratch "struct resource" and have the loop do the additions to base/end.
	- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
	  longer needed.
	- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
	- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
	  relates to the actual product, as suggested by Mika.
	- Rework Makefile according Andy's comments.
	- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should not
	  be so generic, as suggested by Andy.
	- Call lpc_ich_add_gpio() via priv->chipset.
	- lpc_ich_add_gpio() function will be moved from 
	  .../include/linux/mfd/lpc_ich.h to
	  .../drivers/mfd/lpc_ich-apl.h
	  as this is a part of internal driver interface as suggested by Andy.
	- Move enum lpc_chipsets from 
	  .../drivers/mfd/lpc_ich-core.c to
	  .../include/linux/mfd/lpc_ich.h
	  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
	- Check if kasprintf return value for all 4 gpio controllers before
	  proceed to add platform device by using mfd_add_devices().

Changes in V5:
	- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
	  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
	- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to CONFIG_X86_INTEL_APL
	  so that it reflects actual product as suggested by Mika.

Changes in V4:
	- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
	  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
	  to
	  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
	  since the config is used in latter patch.
	- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
	- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
	  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
	  as suggested by Lee Jones.
	- Use single dimensional array instead of 2D array for apl_gpio_io_res
	  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
	- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
	  defines for apl_gpio_io_res structure
	- Define magic number for P2SB PCI ID
	- Replace switch-case with if-else since currently we have only one
	  use case
	- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
	- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
	  to fix kbuildbot error

 drivers/mfd/Kconfig        |   2 +
 drivers/mfd/Makefile       |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/lpc_ich_apl.h  |  29 +++++++++++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
 	tristate "Intel ICH LPC"
 	depends on PCI
+	depends on X86 && PCI
 	select MFD_CORE
+	select P2SB
 	help
 	  The LPC bridge function of the Intel ICH provides support for
 	  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO)	+= intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)		+= lpc_sch.o
 lpc_ich-objs		:= lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)		+= lpc_ich.o
+lpc_ich-objs		:= lpc_ich_core.o
+ifeq ($(CONFIG_X86_INTEL_IVI),y)
+lpc_ich-objs += lpc_ich_apl.o
+endif
 obj-$(CONFIG_MFD_RDC321X)	+= rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)	+= janz-cmodio.o
 obj-$(CONFIG_MFD_JZ4740_ADC)	+= jz4740-adc.o
diff --git a/drivers/mfd/lpc_ich_apl.c b/drivers/mfd/lpc_ich_apl.c
new file mode 100644
index 0000000..7a79052
--- /dev/null
+++ b/drivers/mfd/lpc_ich_apl.c
@@ -0,0 +1,120 @@
+/*
+ * Intel Apollo Lake In-Vehicle Infotainment (IVI) systems used in cars support
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * Author: Tan, Jui Nee <jui.nee.tan@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/p2sb.h>
+#include <linux/pci.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/lpc_ich.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "lpc_ich_apl.h"
+
+/* Offset data for Apollo Lake GPIO communities */
+#define APL_GPIO_SOUTHWEST_OFFSET	0xc00000
+#define APL_GPIO_NORTHWEST_OFFSET	0xc40000
+#define APL_GPIO_NORTH_OFFSET		0xc50000
+#define APL_GPIO_WEST_OFFSET		0xc70000
+
+#define APL_GPIO_SOUTHWEST_NPIN		43
+#define APL_GPIO_NORTHWEST_NPIN		77
+#define APL_GPIO_NORTH_NPIN		78
+#define APL_GPIO_WEST_NPIN		47
+
+#define APL_GPIO_COMMUNITY_MAX		4
+
+#define APL_GPIO_IRQ 14
+
+#define PCI_IDSEL_P2SB	0x0d
+
+static struct resource apl_gpio_io_res[] = {
+	DEFINE_RES_MEM_NAMED(APL_GPIO_NORTH_OFFSET,
+		APL_GPIO_NORTH_NPIN * SZ_8, "apl_pinctrl_n"),
+	DEFINE_RES_MEM_NAMED(APL_GPIO_NORTHWEST_OFFSET,
+		APL_GPIO_NORTHWEST_NPIN * SZ_8, "apl_pinctrl_nw"),
+	DEFINE_RES_MEM_NAMED(APL_GPIO_WEST_OFFSET,
+		APL_GPIO_WEST_NPIN * SZ_8, "apl_pinctrl_w"),
+	DEFINE_RES_MEM_NAMED(APL_GPIO_SOUTHWEST_OFFSET,
+		APL_GPIO_SOUTHWEST_NPIN * SZ_8, "apl_pinctrl_sw"),
+	DEFINE_RES_IRQ(APL_GPIO_IRQ),
+};
+
+static struct mfd_cell apl_gpio_devices[] = {
+	{
+		.name = "apl-pinctrl",
+		.id = 0,
+		.num_resources = ARRAY_SIZE(apl_gpio_io_res),
+		.resources = &apl_gpio_io_res[0],
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.name = "apl-pinctrl",
+		.id = 1,
+		.num_resources = ARRAY_SIZE(apl_gpio_io_res),
+		.resources = &apl_gpio_io_res[1],
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.name = "apl-pinctrl",
+		.id = 2,
+		.num_resources = ARRAY_SIZE(apl_gpio_io_res),
+		.resources = &apl_gpio_io_res[2],
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.name = "apl-pinctrl",
+		.id = 3,
+		.num_resources = ARRAY_SIZE(apl_gpio_io_res),
+		.resources = &apl_gpio_io_res[3],
+		.ignore_resource_conflicts = true,
+	},
+};
+
+int lpc_ich_add_gpio(struct pci_dev *dev, enum lpc_chipsets chipset)
+{
+	unsigned int i;
+	int ret;
+	struct resource base;
+
+	if (chipset != LPC_APL)
+		return -ENODEV;
+	/*
+	 * Apollo lake, has not 1, but 4 gpio controllers,
+	 * handle it a bit differently.
+	 */
+
+	ret = p2sb_bar(dev, PCI_DEVFN(PCI_IDSEL_P2SB, 0), &base);
+	if (ret)
+		goto warn_continue;
+
+	for (i = 0; i < APL_GPIO_COMMUNITY_MAX; i++) {
+		struct resource *res = &apl_gpio_io_res[i];
+
+		/* Fill MEM resource */
+		res->start += base.start;
+		res->end += base.start;
+		res->flags = base.flags;
+
+		res++;
+	}
+
+	ret = mfd_add_devices(&dev->dev, 0,
+		apl_gpio_devices, ARRAY_SIZE(apl_gpio_devices),
+			NULL, 0, NULL);
+
+	if (ret)
+warn_continue:
+		dev_warn(&dev->dev,
+			"Failed to add Apollo Lake GPIO: %d\n",
+				ret);
+
+	return ret;
+}
diff --git a/drivers/mfd/lpc_ich_apl.h b/drivers/mfd/lpc_ich_apl.h
new file mode 100644
index 0000000..43fcc99
--- /dev/null
+++ b/drivers/mfd/lpc_ich_apl.h
@@ -0,0 +1,29 @@
+/*
+ * lpc_ich_apl.h - Intel In-Vehicle Infotainment (IVI) systems used in cars
+ *                 support
+ *
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * Author: Tan, Jui Nee <jui.nee.tan@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LPC_ICH_APL_H__
+#define __LPC_ICH_APL_H__
+
+#include <linux/pci.h>
+
+#if IS_ENABLED(CONFIG_X86_INTEL_IVI)
+int lpc_ich_add_gpio(struct pci_dev *dev, enum lpc_chipsets chipset);
+#else /* CONFIG_X86_INTEL_IVI is not set */
+static inline int lpc_ich_add_gpio(struct pci_dev *dev,
+	enum lpc_chipsets chipset)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif
diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 3bb6334..25c4d99 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -68,6 +68,8 @@
 #include <linux/mfd/lpc_ich.h>
 #include <linux/platform_data/itco_wdt.h>
 
+#include "lpc_ich_apl.h"
+
 #define ACPIBASE		0x40
 #define ACPIBASE_GPE_OFF	0x28
 #define ACPIBASE_GPE_END	0x2f
@@ -1030,6 +1032,9 @@ static int lpc_ich_probe(struct pci_dev *dev,
 			cell_added = true;
 	}
 
+	if (!lpc_ich_add_gpio(dev, priv->chipset))
+		cell_added = true;
+
 	/*
 	 * We only care if at least one or none of the cells registered
 	 * successfully.
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1518849 — Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

Fromkbuild test robot <lkp@intel.com>
Date2016-11-10 11:50 +0100
SubjectRe: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
Message-ID<sBV5D-4yq-3@gated-at.bofh.it>
In reply to#1518767

[Multipart message — attachments visible in raw view] — view raw

Hi Tan,

[auto build test WARNING on v4.9-rc4]
[cannot apply to ljones-mfd/for-mfd-next platform-drivers-x86/for-next tip/x86/core next-20161110]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Tan-Jui-Nee/pinctrl-broxton-enable-platform-device-in-the-absent-of-ACPI-enumeration/20161110-170808
config: x86_64-randconfig-x012-201645 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

warning: (LPC_ICH) selects P2SB which has unmet direct dependencies (X86 && X86_PLATFORM_DEVICES && PCI)

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[toc] | [prev] | [next] | [standalone]

#1518909 — Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

FromAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Date2016-11-10 12:50 +0100
SubjectRe: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
Message-ID<sBW1I-5Bk-17@gated-at.bofh.it>
In reply to#1518849
On Thu, 2016-11-10 at 18:40 +0800, kbuild test robot wrote:
> Hi Tan,
> 
> [auto build test WARNING on v4.9-rc4]
> [cannot apply to ljones-mfd/for-mfd-next platform-drivers-x86/for-next 
> tip/x86/core next-20161110]
> [if your patch is applied to the wrong git tree, please drop us a note
> to help improve the system]
> 
> url:    https://github.com/0day-ci/linux/commits/Tan-Jui-Nee/pinctrl-b
> roxton-enable-platform-device-in-the-absent-of-ACPI-
> enumeration/20161110-170808
> config: x86_64-randconfig-x012-201645 (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
>         # save the attached .config to linux build tree
>         make ARCH=x86_64 
> 
> All warnings (new ones prefixed by >>):
> 
> warning: (LPC_ICH) selects P2SB which has unmet direct dependencies
> (X86 && X86_PLATFORM_DEVICES && PCI)

Since it will need to be fixed and new version is suggested, I dare to
comment couple of patches.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[toc] | [prev] | [next] | [standalone]

#1519103 — Re: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

FromAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Date2016-11-10 17:20 +0100
SubjectRe: [PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
Message-ID<sC0f0-77-7@gated-at.bofh.it>
In reply to#1518767
On Thu, 2016-11-10 at 17:00 +0800, Tan Jui Nee wrote:
> This driver uses the P2SB hide/unhide mechanism cooperatively
> to pass the PCI BAR address to the gpio platform driver.

@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO)	+=
> intel_quark_i2c_gpio.o
>  obj-$(CONFIG_LPC_SCH)
> 		+= lpc_sch.o


>  lpc_ich-objs		:= lpc_ich_core.o
>  obj-$(CONFIG_LPC_ICH)		+= lpc_ich.o
> +lpc_ich-objs		:= lpc_ich_core.o

Once I pointed out on this.

> @@ -0,0 +1,120 @@
> +/*
> + * Intel Apollo Lake In-Vehicle Infotainment (IVI) systems used in
> cars support
> + *
> + * Copyright (C) 2016 Intel Corporation
> + *
> + * Author: Tan, Jui Nee <jui.nee.tan@intel.com>
> + *
> + * This program is free software; you can redistribute it and/or
> modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/p2sb.h>
> +#include <linux/pci.h>
> +#include <linux/mfd/core.h>
> +#include <linux/mfd/lpc_ich.h>
> +#include <linux/pinctrl/pinctrl.h>

Perhaps some order like

#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/pci.h>
#include <linux/pinctrl/pinctrl.h>

#include <asm/p2sb.h>

> +
> +#include "lpc_ich_apl.h"


> +int lpc_ich_add_gpio(struct pci_dev *dev, enum lpc_chipsets chipset)
> +{

> +	unsigned int i;
> +	int ret;
> +	struct resource base;

Reversed tree, please:

	struct resource base;
	unsigned int i;
	int ret;

> +
> +	if (chipset != LPC_APL)
> +		return -ENODEV;
> +	/*
> +	 * Apollo lake, has not 1, but 4 gpio controllers,
> +	 * handle it a bit differently.
> +	 */
> +
> +	ret = p2sb_bar(dev, PCI_DEVFN(PCI_IDSEL_P2SB, 0), &base);
> +	if (ret)
> +		goto warn_continue;
> +
> +	for (i = 0; i < APL_GPIO_COMMUNITY_MAX; i++) {
> +		struct resource *res = &apl_gpio_io_res[i];
> +
> +		/* Fill MEM resource */
> +		res->start += base.start;
> +		res->end += base.start;
> +		res->flags = base.flags;
> +
> +		res++;
> +	}
> +
> +	ret = mfd_add_devices(&dev->dev, 0,
> +		apl_gpio_devices, ARRAY_SIZE(apl_gpio_devices),
> +			NULL, 0, NULL);
> +
> 

> +	if (ret)
> +warn_continue:

Better if you put label before if for sake of readability. I pointed
once to this.

> +		dev_warn(&dev->dev,
> +			"Failed to add Apollo Lake GPIO: %d\n",
> +				ret);
> +
> +	return ret;
> +}

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web