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Groups > linux.kernel > #1516617 > unrolled thread
| Started by | kan.liang@intel.com |
|---|---|
| First post | 2016-11-07 22:50 +0100 |
| Last post | 2016-11-08 18:10 +0100 |
| Articles | 3 — 3 participants |
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[PATCH] perf/x86: add more Intel uncore IMC PCI ID for SkyLake kan.liang@intel.com - 2016-11-07 22:50 +0100
Re: [PATCH] perf/x86: add more Intel uncore IMC PCI ID for SkyLake Ben Widawsky <benjamin.widawsky@intel.com> - 2016-11-08 01:00 +0100
Re: [PATCH] perf/x86: add more Intel uncore IMC PCI ID for SkyLake Thomas Gleixner <tglx@linutronix.de> - 2016-11-08 18:10 +0100
| From | kan.liang@intel.com |
|---|---|
| Date | 2016-11-07 22:50 +0100 |
| Subject | [PATCH] perf/x86: add more Intel uncore IMC PCI ID for SkyLake |
| Message-ID | <sAZXH-lp-11@gated-at.bofh.it> |
From: Kan Liang <kan.liang@intel.com>
There are several PCI IDs are missed for Intel SkyLake IMC.
This patch adds the PCI IDs for SkyLake Y, U, H and S platforms.
This patch also rename 0x191f and 0x190c according to the document.
These PCI IDs are defined in the document as below.
Y & U platforms
http://www.intel.com/content/www/us/en/processors/core/
6th-gen-core-family-mobile-u-y-processor-lines-datasheet-vol-2.html
S platform
http://www.intel.com/content/www/us/en/processors/core/
desktop-6th-gen-core-family-datasheet-vol-2.html
H platform
http://www.intel.com/content/www/us/en/processors/core/
6th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
Tested-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
---
arch/x86/events/intel/uncore_snb.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index 5f845ee..949f5da 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -8,8 +8,12 @@
#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
#define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
#define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
-#define PCI_DEVICE_ID_INTEL_SKL_IMC 0x191f
-#define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x190c
+#define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
+#define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
+#define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
+#define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
+#define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
+#define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
/* SNB event control */
#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
@@ -616,13 +620,29 @@ static const struct pci_device_id bdw_uncore_pci_ids[] = {
static const struct pci_device_id skl_uncore_pci_ids[] = {
{ /* IMC */
- PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_IMC),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
},
{ /* IMC */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
},
+ { /* IMC */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC),
+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
+ },
+ { /* IMC */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC),
+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
+ },
+ { /* IMC */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC),
+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
+ },
+ { /* IMC */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC),
+ .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
+ },
{ /* end: all zeroes */ },
};
@@ -666,8 +686,12 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */
IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core ULT Mobile Processor */
IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver), /* 5th Gen Core U */
- IMC_DEV(SKL_IMC, &skl_uncore_pci_driver), /* 6th Gen Core */
+ IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver), /* 6th Gen Core Y */
IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver), /* 6th Gen Core U */
+ IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Dual Core */
+ IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */
+ IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */
+ IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */
{ /* end marker */ }
};
--
2.5.5
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| From | Ben Widawsky <benjamin.widawsky@intel.com> |
|---|---|
| Date | 2016-11-08 01:00 +0100 |
| Message-ID | <sB1Zw-1Es-3@gated-at.bofh.it> |
| In reply to | #1516617 |
On 16-11-07 16:47:11, kan.liang@intel.com wrote: >From: Kan Liang <kan.liang@intel.com> > >There are several PCI IDs are missed for Intel SkyLake IMC. >This patch adds the PCI IDs for SkyLake Y, U, H and S platforms. >This patch also rename 0x191f and 0x190c according to the document. > >These PCI IDs are defined in the document as below. > >Y & U platforms >http://www.intel.com/content/www/us/en/processors/core/ >6th-gen-core-family-mobile-u-y-processor-lines-datasheet-vol-2.html > >S platform >http://www.intel.com/content/www/us/en/processors/core/ >desktop-6th-gen-core-family-datasheet-vol-2.html > >H platform >http://www.intel.com/content/www/us/en/processors/core/ >6th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html > >Tested-by: Ben Widawsky <benjamin.widawsky@intel.com> >Signed-off-by: Kan Liang <kan.liang@intel.com> Also: Reported-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> [snip] -- Ben Widawsky, Intel Open Source Technology Center
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| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Date | 2016-11-08 18:10 +0100 |
| Message-ID | <sBi4i-3IU-35@gated-at.bofh.it> |
| In reply to | #1516617 |
On Mon, 7 Nov 2016, kan.liang@intel.com wrote: > There are several PCI IDs are missed for Intel SkyLake IMC. There are ... are ??? > This patch adds the PCI IDs for SkyLake Y, U, H and S platforms. "This patch" is just a bad habit. We already know that this is a patch. See Documentation/SubmittingPatches, which has an explanation for this. > This patch also rename 0x191f and 0x190c according to the document. You do not rename the hex constants. You rename the ID macros ... > These PCI IDs are defined in the document as below. > > Y & U platforms > http://www.intel.com/content/www/us/en/processors/core/ > 6th-gen-core-family-mobile-u-y-processor-lines-datasheet-vol-2.html > > S platform > http://www.intel.com/content/www/us/en/processors/core/ > desktop-6th-gen-core-family-datasheet-vol-2.html > > H platform > http://www.intel.com/content/www/us/en/processors/core/ > 6th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html As I said before several times. These links are just horrible. The Intel webpage is restructured every so often, so the links might be stale before thishits Linus tree. We really need persistant links, not just the link of today. One way to achive that is to open a bugzilla entry in the kernel org bugzilla and stick the files there for permanent reference, unless Intel comes up with something which is not affected by their constant web page reshuffling. Thanks, tglx
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