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Groups > linux.kernel > #1516175 > unrolled thread
| Started by | Alexandre Bailon <abailon@baylibre.com> |
|---|---|
| First post | 2016-11-07 14:30 +0100 |
| Last post | 2016-11-07 14:30 +0100 |
| Articles | 2 — 1 participant |
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[PATCH v5 0/4] usb: musb: da8xx: Fix few issues Alexandre Bailon <abailon@baylibre.com> - 2016-11-07 14:30 +0100
[PATCH v5 2/4] phy: da8xx-usb: Configure CFGCHIP2 to support OTG workaround Alexandre Bailon <abailon@baylibre.com> - 2016-11-07 14:30 +0100
| From | Alexandre Bailon <abailon@baylibre.com> |
|---|---|
| Date | 2016-11-07 14:30 +0100 |
| Subject | [PATCH v5 0/4] usb: musb: da8xx: Fix few issues |
| Message-ID | <sAS0a-3Aq-37@gated-at.bofh.it> |
Currently, the USB OTG of the da8xx doesn't work. This series intend to fix them. Change in v2: * Fix the error path da8xx_musb_init() Changes in v3: * Remove the host workaround that was not working on every platform * Add a property to the devicetree node of phy to force the phy in a specific mode (host or device). * Only use dr_mode to configure the controller mode and let the phy in OTG mode. The main goal of this change is to prevent the phy to be set in host or device mode because these modes have some issues. Changes in v4: * Enable VBUS sense and session end comparator during probe of phy. * Add a quirk flag to skip the phy set mode made during the init of musb. In that way, we can still can configure the phy mode by using mode file in sysfs and configure the controller mode by using dr_mode or platform_data. * Init the phy in otg mode in da8xx glue driver. Changes in v5: * Add the init argument to musb_platform_set_mode() and set_mode() callback. * Remove the quirk * Configure the DA8xx phy in OTG mode if da8xx_musb_set_mode() is called from init. Alexandre Bailon (4): usb: musb: da8xx: Call earlier clk_prepare_enable() phy: da8xx-usb: Configure CFGCHIP2 to support OTG workaround usb: musb: Add a new argument to musb_platform_set_mode() usb: musb: da8xx: Set phy in OTG mode by default drivers/phy/phy-da8xx-usb.c | 5 +++++ drivers/usb/musb/am35x.c | 2 +- drivers/usb/musb/blackfin.c | 2 +- drivers/usb/musb/da8xx.c | 26 ++++++++++++++++---------- drivers/usb/musb/davinci.c | 2 +- drivers/usb/musb/musb_core.c | 12 ++++++------ drivers/usb/musb/musb_core.h | 6 +++--- drivers/usb/musb/musb_dsps.c | 2 +- drivers/usb/musb/sunxi.c | 2 +- drivers/usb/musb/tusb6010.c | 2 +- 10 files changed, 36 insertions(+), 25 deletions(-) -- 2.7.3
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| From | Alexandre Bailon <abailon@baylibre.com> |
|---|---|
| Date | 2016-11-07 14:30 +0100 |
| Subject | [PATCH v5 2/4] phy: da8xx-usb: Configure CFGCHIP2 to support OTG workaround |
| Message-ID | <sAS9Q-3GK-31@gated-at.bofh.it> |
| In reply to | #1516175 |
If we configure the da8xx OTG phy in OTG mode, neither device or host
mode will work. That is because the PHY is not able to detect and notify
the driver that value of ID pin changed.
To work despite this hardware limitation, the da8xx glue implement a
workaround.
But to work, the workaround require the VBUS sense and the session end
comparator to enabled.
Enable them if the phy is configured in OTG mode.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
---
drivers/phy/phy-da8xx-usb.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
index 32ae78c..089c13b 100644
--- a/drivers/phy/phy-da8xx-usb.c
+++ b/drivers/phy/phy-da8xx-usb.c
@@ -23,6 +23,8 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#define PHY_INIT_BITS (CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN)
+
struct da8xx_usb_phy {
struct phy_provider *phy_provider;
struct phy *usb11_phy;
@@ -207,6 +209,9 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev)
dev_warn(dev, "Failed to create usb20 phy lookup\n");
}
+ regmap_write_bits(d_phy->regmap, CFGCHIP(2),
+ PHY_INIT_BITS, PHY_INIT_BITS);
+
return 0;
}
--
2.7.3
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