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[PATCH 0/3] ARM: dts: artpec6.dtsi updates

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  [PATCH 0/3] ARM: dts: artpec6.dtsi updates Lars Persson <lars.persson@axis.com> - 2016-08-23 16:10 +0200
    [PATCH 2/3] ARM: dts: artpec: use optimized pl310 settings Lars Persson <lars.persson@axis.com> - 2016-08-23 16:10 +0200

#1468569 — [PATCH 0/3] ARM: dts: artpec6.dtsi updates

This brings the dtsi up to date with with tested and optimized settings from the
Axis tree.

Lars Persson (3):
  ARM: dts: artpec: use clock binding header
  ARM: dts: artpec: use optimized pl310 settings
  ARM: dts: artpec: set irq affinity on pmu interrupts

 arch/arm/boot/dts/artpec6.dtsi | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

-- 
2.1.4

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#1468572 — [PATCH 2/3] ARM: dts: artpec: use optimized pl310 settings

Use the cache settings that were determined to give best performance
on artpec-6 typical workloads.

Signed-off-by: Lars Persson <larper@axis.com>
---
 arch/arm/boot/dts/artpec6.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index db41b52..4e40d55 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -137,6 +137,13 @@
 		arm,data-latency = <1 1 1>;
 		arm,tag-latency = <1 1 1>;
 		arm,filter-ranges = <0x0 0x80000000>;
+		arm,double-linefill = <1>;
+		arm,double-linefill-incr = <0>;
+		arm,double-linefill-wrap = <0>;
+		prefetch-data = <1>;
+		prefetch-instr = <1>;
+		arm,prefetch-offset = <0>;
+		arm,prefetch-drop = <1>;
 	};
 
 	pmu {
-- 
2.1.4

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