Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1460283 > unrolled thread

[PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

Contents

  [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Rajendra Nayak <rnayak@codeaurora.org> - 2016-08-11 10:50 +0200
    Re: [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Stephen Boyd <sboyd@codeaurora.org> - 2016-08-24 08:20 +0200
      Re: [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Rajendra Nayak <rnayak@codeaurora.org> - 2016-08-25 11:30 +0200

#1460283 — [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode

Some PLLs can support an alpha mode, and a single alpha
register (instead of registers to program the M/N values),
the contents of which depend on the alpha mode selected.
(They are either treated as two's complement or M/N value)
Add support for this in the clk PLL driver.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/clk-pll.c | 8 ++++++--
 drivers/clk/qcom/clk-pll.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 5b940d6..08d2fa2 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
 	u32 mask;
 
 	regmap_write(regmap, pll->l_reg, config->l);
-	regmap_write(regmap, pll->m_reg, config->m);
-	regmap_write(regmap, pll->n_reg, config->n);
+	if (pll->alpha_reg) {
+		regmap_write(regmap, pll->alpha_reg, config->alpha);
+	} else {
+		regmap_write(regmap, pll->m_reg, config->m);
+		regmap_write(regmap, pll->n_reg, config->n);
+	}
 
 	val = config->vco_val;
 	val |= config->pre_div_val;
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index ffd0c63..083727e 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -48,6 +48,7 @@ struct clk_pll {
 	u32	l_reg;
 	u32	m_reg;
 	u32	n_reg;
+	u32	alpha_reg;
 	u32	config_reg;
 	u32	mode_reg;
 	u32	status_reg;
@@ -70,6 +71,7 @@ struct pll_config {
 	u16 l;
 	u32 m;
 	u32 n;
+	u32 alpha;
 	u32 vco_val;
 	u32 vco_mask;
 	u32 pre_div_val;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[toc] | [next] | [standalone]

#1469097

On 08/11, Rajendra Nayak wrote:
> Some PLLs can support an alpha mode, and a single alpha
> register (instead of registers to program the M/N values),
> the contents of which depend on the alpha mode selected.
> (They are either treated as two's complement or M/N value)

That's just a sentence, so please drop the parentheses.

> Add support for this in the clk PLL driver.
> 

I'm confused, don't we already have clk-alpha-pll.c to handle
alpha type plls? What are we doing adding support to the "legacy"
pll code?

> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
>  drivers/clk/qcom/clk-pll.c | 8 ++++++--
>  drivers/clk/qcom/clk-pll.h | 2 ++
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
> index 5b940d6..08d2fa2 100644
> --- a/drivers/clk/qcom/clk-pll.c
> +++ b/drivers/clk/qcom/clk-pll.c
> @@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
>  	u32 mask;
>  
>  	regmap_write(regmap, pll->l_reg, config->l);
> -	regmap_write(regmap, pll->m_reg, config->m);
> -	regmap_write(regmap, pll->n_reg, config->n);
> +	if (pll->alpha_reg) {

This assumes that alpha_reg is not 0 offset from base, which
seems like a bad assumption to make.

> +		regmap_write(regmap, pll->alpha_reg, config->alpha);
> +	} else {
> +		regmap_write(regmap, pll->m_reg, config->m);
> +		regmap_write(regmap, pll->n_reg, config->n);
> +	}
>  
>  	val = config->vco_val;
>  	val |= config->pre_div_val;
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[toc] | [prev] | [next] | [standalone]

#1470003

On 08/24/2016 11:45 AM, Stephen Boyd wrote:
> On 08/11, Rajendra Nayak wrote:
>> Some PLLs can support an alpha mode, and a single alpha
>> register (instead of registers to program the M/N values),
>> the contents of which depend on the alpha mode selected.
>> (They are either treated as two's complement or M/N value)
> 
> That's just a sentence, so please drop the parentheses.

OK

> 
>> Add support for this in the clk PLL driver.
>>
> 
> I'm confused, don't we already have clk-alpha-pll.c to handle
> alpha type plls? What are we doing adding support to the "legacy"
> pll code?

Yes, this does look confusing now that I took a relook at it all.
I will redo this whole thing so it fits into the alpha PLL support that
we already have.

> 
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
>>  drivers/clk/qcom/clk-pll.c | 8 ++++++--
>>  drivers/clk/qcom/clk-pll.h | 2 ++
>>  2 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
>> index 5b940d6..08d2fa2 100644
>> --- a/drivers/clk/qcom/clk-pll.c
>> +++ b/drivers/clk/qcom/clk-pll.c
>> @@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
>>  	u32 mask;
>>  
>>  	regmap_write(regmap, pll->l_reg, config->l);
>> -	regmap_write(regmap, pll->m_reg, config->m);
>> -	regmap_write(regmap, pll->n_reg, config->n);
>> +	if (pll->alpha_reg) {
> 
> This assumes that alpha_reg is not 0 offset from base, which
> seems like a bad assumption to make.

sure, I need to handle this in a better way

> 
>> +		regmap_write(regmap, pll->alpha_reg, config->alpha);
>> +	} else {
>> +		regmap_write(regmap, pll->m_reg, config->m);
>> +		regmap_write(regmap, pll->n_reg, config->n);
>> +	}
>>  
>>  	val = config->vco_val;
>>  	val |= config->pre_div_val;
>>
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web