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Groups > linux.kernel > #1463443 > unrolled thread
| Started by | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| First post | 2016-08-16 08:30 +0200 |
| Last post | 2016-08-23 05:00 +0200 |
| Articles | 20 on this page of 34 — 8 participants |
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[PATCH 0/7] arm64: dts: Add the dts file for Exynos5433 and TM/TM2E board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:30 +0200
[PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:30 +0200
Re: [PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-16 09:50 +0200
Re: [PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver Viresh Kumar <viresh.kumar@linaro.org> - 2016-08-16 10:50 +0200
[PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:30 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Tomasz Figa <tomasz.figa@gmail.com> - 2016-08-16 09:00 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-16 10:50 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Rob Herring <robh@kernel.org> - 2016-08-19 03:50 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-19 11:10 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Tomasz Figa <tomasz.figa@gmail.com> - 2016-08-19 13:40 +0200
Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-24 15:00 +0200
[PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:30 +0200
Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-16 09:50 +0200
Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 10:10 +0200
Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-16 10:20 +0200
Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible Rob Herring <robh@kernel.org> - 2016-08-19 04:00 +0200
[PATCH 1/7] clocksource: exynos_mct: Add the support for Exynos 64bit SoC Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:30 +0200
[PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:40 +0200
Re: [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-17 08:50 +0200
Re: [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-17 09:40 +0200
Re: [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board Rob Herring <robh@kernel.org> - 2016-08-19 03:50 +0200
[PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 08:40 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-17 09:00 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-17 09:40 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-19 03:10 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Rob Herring <robh@kernel.org> - 2016-08-19 03:30 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-08-19 19:20 +0200
Re: [PATCH 6/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board Chanwoo Choi <cwchoi00@gmail.com> - 2016-08-21 09:50 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-08-16 13:00 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-16 15:10 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-08-16 20:00 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-17 02:50 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Marek Szyprowski <m.szyprowski@samsung.com> - 2016-08-19 13:00 +0200
Re: [PATCH 5/7] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-23 05:00 +0200
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:30 +0200 |
| Subject | [PATCH 0/7] arm64: dts: Add the dts file for Exynos5433 and TM/TM2E board |
| Message-ID | <s6G2R-7Xd-1@gated-at.bofh.it> |
This patchset adds the Device Tree file for Samsung 64-bit Exynos5433 SoC and TM/TM2E board based on Exynos5433. The Exynos5433 has Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). The TM2 and TM2E are the Samsung board based on Exynos5433 SoC. I sent the Exynos5433 patches[3]. But it was not merged because of sending the only SoC dtsi patch without board patches. So, I again send the Exynos5433 SoC patches with TM2/TM2E board dts files. When making the patches, I get the guide from Krzysztof (Exynos SoC maintainer). The maintainer requires that already developed and verified work should merge them as one patch. So, this patchset include only three patches for Exynos5433 dtsi, TM2 dts and TM2E dts file. I tested the display controller by using the modetest tool. But, Samsung s6e3ha2 panel driver has not yet posted. So, the TM2 dts file don't include the panel Device Tree node. I'll post the s6e3ha2 panel driver on separate patch with a dt patch. Depends on: This patchset are based on v4.8-rc1[1] and TM2 sound patches[2]. [1] v4.8-rc1 [2] https://lkml.org/lkml/2016/7/5/470 : [PATCH v4 0/4] ASoC: samsung: Sound support for Exynos5433 TM2(E) boards [3] http://lkml.org/lkml/2015/3/17/843 : [PATCH v7 0/9] arm64: Add the support for new Exynos5433 SoC Chanwoo Choi (6): clocksource: exynos_mct: Add the support for Exynos 64bit SoC Documentation: bindings: Add Exynos5433 PMU compatible cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board Joonyoung Shim (1): pinctrl: samsung: Add GPFx support of Exynos5433 .../devicetree/bindings/arm/samsung/pmu.txt | 1 + .../bindings/arm/samsung/samsung-boards.txt | 2 + .../bindings/pinctrl/samsung-pinctrl.txt | 1 + arch/arm64/boot/dts/exynos/Makefile | 5 +- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 794 ++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1003 +++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 + .../dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi | 23 + .../dts/exynos/exynos5433-tmu-sensor-conf.dtsi | 22 + arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 306 ++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1580 ++++++++++++++++++++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/exynos_mct.c | 4 + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/pinctrl/samsung/pinctrl-exynos.c | 5 + drivers/pinctrl/samsung/pinctrl-exynos.h | 11 + drivers/pinctrl/samsung/pinctrl-samsung.c | 43 +- drivers/pinctrl/samsung/pinctrl-samsung.h | 5 + 18 files changed, 3839 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi -- 1.9.1
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:30 +0200 |
| Subject | [PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver |
| Message-ID | <s6G2R-7Xd-17@gated-at.bofh.it> |
| In reply to | #1463443 |
This patch adds the exynos5433 compatible string for supporting
the generic cpufreq driver on Exynos5433.
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 0bb44d5b5df4..470db30f745f 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -40,6 +40,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "samsung,exynos5250", },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", },
+ { .compatible = "samsung,exynos5433", },
{ .compatible = "samsung,exynos5800", },
#endif
--
1.9.1
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2016-08-16 09:50 +0200 |
| Subject | Re: [PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver |
| Message-ID | <s6Hii-c3-25@gated-at.bofh.it> |
| In reply to | #1463446 |
On 08/16/2016 08:27 AM, Chanwoo Choi wrote: > This patch adds the exynos5433 compatible string for supporting > the generic cpufreq driver on Exynos5433. > > Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> > Cc: Viresh Kumar <viresh.kumar@linaro.org> > Cc: linux-pm@vger.kernel.org > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > drivers/cpufreq/cpufreq-dt-platdev.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> I guess this does not depend on the rest and can go through PM/cpufreq tree? Viresh, Rafael, If you wish me to take it, let me know. Best regards, Krzysztof
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| From | Viresh Kumar <viresh.kumar@linaro.org> |
|---|---|
| Date | 2016-08-16 10:50 +0200 |
| Subject | Re: [PATCH 3/7] cpufreq: dt: Add exynos5433 compatible to use generic cpufreq driver |
| Message-ID | <s6Iem-Nx-15@gated-at.bofh.it> |
| In reply to | #1463506 |
On 16-08-16, 09:47, Krzysztof Kozlowski wrote: > On 08/16/2016 08:27 AM, Chanwoo Choi wrote: > > This patch adds the exynos5433 compatible string for supporting > > the generic cpufreq driver on Exynos5433. > > > > Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> > > Cc: Viresh Kumar <viresh.kumar@linaro.org> > > Cc: linux-pm@vger.kernel.org > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > > --- > > drivers/cpufreq/cpufreq-dt-platdev.c | 1 + > > 1 file changed, 1 insertion(+) > > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > > I guess this does not depend on the rest and can go through PM/cpufreq tree? > > Viresh, Rafael, > If you wish me to take it, let me know. I will prefer it going through PM tree. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> -- viresh
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:30 +0200 |
| Subject | [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s6G2R-7Xd-21@gated-at.bofh.it> |
| In reply to | #1463443 |
From: Joonyoung Shim <jy0922.shim@samsung.com>
This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has
different memory map of GPFx from previous Exynos SoC. Exynos GPIO has
following register to control gpio funciton. Usually, all registers of GPIO
are included in same domain.
- CON / DAT / PUD / DRV / CONPDN / PUDPDN
- EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
But, GPFx are included in two domain as following. So, this patch supports
the GPFx pin which handle the on separate two domains.
- ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN
- IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++
drivers/pinctrl/samsung/pinctrl-exynos.h | 11 ++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 43 ++++++++++++++++++----
drivers/pinctrl/samsung/pinctrl-samsung.h | 5 +++
5 files changed, 57 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 6db16b90873a..807fba1f829f 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -19,6 +19,7 @@ Required Properties:
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 051b5bf701a8..4f95983e0cdd 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1350,6 +1350,11 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004),
+ EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008),
+ EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010),
+ EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014),
};
/* pin banks of exynos5433 pin-controller - AUD */
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 0f0f7cedb2dc..4b737b6c434d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -79,6 +79,17 @@
.name = id \
}
+#define EXYNOS_PIN_BANK_EINTW_EXT(pins, reg, id, offs) \
+ { \
+ .type = &bank_type_off, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_WKUP, \
+ .eint_offset = offs, \
+ .eint_ext = true, \
+ .name = id \
+ }
+
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 513fe6b23248..57e22085c2db 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -338,6 +338,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
struct samsung_pin_bank **bank)
{
struct samsung_pin_bank *b;
+ void __iomem *virt_base = drvdata->virt_base;
b = drvdata->pin_banks;
@@ -345,7 +346,10 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
((b->pin_base + b->nr_pins - 1) < pin))
b++;
- *reg = drvdata->virt_base + b->pctl_offset;
+ if (b->eint_ext)
+ virt_base = drvdata->ext_base;
+
+ *reg = virt_base + b->pctl_offset;
*offset = pin - b->pin_base;
if (bank)
*bank = b;
@@ -523,10 +527,12 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ void __iomem *virt_base = bank->eint_ext ?
+ bank->drvdata->ext_base : bank->drvdata->virt_base;
void __iomem *reg;
u32 data;
- reg = bank->drvdata->virt_base + bank->pctl_offset;
+ reg = virt_base + bank->pctl_offset;
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data &= ~(1 << offset);
@@ -553,8 +559,10 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
u32 data;
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ void __iomem *virt_base = bank->eint_ext ?
+ bank->drvdata->ext_base : bank->drvdata->virt_base;
- reg = bank->drvdata->virt_base + bank->pctl_offset;
+ reg = virt_base + bank->pctl_offset;
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data >>= offset;
@@ -574,6 +582,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
const struct samsung_pin_bank_type *type;
struct samsung_pin_bank *bank;
struct samsung_pinctrl_drv_data *drvdata;
+ void __iomem *virt_base;
void __iomem *reg;
u32 data, mask, shift;
@@ -581,7 +590,8 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
type = bank->type;
drvdata = bank->drvdata;
- reg = drvdata->virt_base + bank->pctl_offset +
+ virt_base = bank->eint_ext ? drvdata->ext_base : drvdata->virt_base;
+ reg = virt_base + bank->pctl_offset +
type->reg_offset[PINCFG_TYPE_FUNC];
mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
@@ -1007,6 +1017,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
bank->eint_type = bdata->eint_type;
bank->eint_mask = bdata->eint_mask;
bank->eint_offset = bdata->eint_offset;
+ bank->eint_ext = bdata->eint_ext;
bank->name = bdata->name;
spin_lock_init(&bank->slock);
@@ -1065,6 +1076,14 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(drvdata->virt_base))
return PTR_ERR(drvdata->virt_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (res) {
+ drvdata->ext_base =
+ devm_ioremap(dev, res->start, resource_size(res));
+ if (!drvdata->ext_base)
+ return -ENXIO;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (res)
drvdata->irq = res->start;
@@ -1102,16 +1121,20 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
static void samsung_pinctrl_suspend_dev(
struct samsung_pinctrl_drv_data *drvdata)
{
- void __iomem *virt_base = drvdata->virt_base;
+ void __iomem *virt_base;
int i;
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
- void __iomem *reg = virt_base + bank->pctl_offset;
+ void __iomem *reg;
const u8 *offs = bank->type->reg_offset;
const u8 *widths = bank->type->fld_width;
enum pincfg_type type;
+ virt_base = bank->eint_ext ?
+ drvdata->ext_base : drvdata->virt_base;
+ reg = virt_base + bank->pctl_offset;
+
/* Registers without a powerdown config aren't lost */
if (!widths[PINCFG_TYPE_CON_PDN])
continue;
@@ -1148,7 +1171,7 @@ static void samsung_pinctrl_suspend_dev(
*/
static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
{
- void __iomem *virt_base = drvdata->virt_base;
+ void __iomem *virt_base;
int i;
if (drvdata->resume)
@@ -1156,11 +1179,15 @@ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
- void __iomem *reg = virt_base + bank->pctl_offset;
+ void __iomem *reg;
const u8 *offs = bank->type->reg_offset;
const u8 *widths = bank->type->fld_width;
enum pincfg_type type;
+ virt_base = bank->eint_ext ?
+ drvdata->ext_base : drvdata->virt_base;
+ reg = virt_base + bank->pctl_offset;
+
/* Registers without a powerdown config aren't lost */
if (!widths[PINCFG_TYPE_CON_PDN])
continue;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index cd31bfaf62cb..3005135f4565 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -131,6 +131,7 @@ struct samsung_pin_bank_data {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ bool eint_ext;
const char *name;
};
@@ -163,6 +164,7 @@ struct samsung_pin_bank {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ bool eint_ext;
const char *name;
u32 pin_base;
@@ -201,6 +203,8 @@ struct samsung_pin_ctrl {
* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
* @node: global list node
* @virt_base: register base address of the controller.
+ * @ext_base: external register base address of the controller.
+ * @ext_base: external register base address of the controller.
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
* @ctrl: pin controller instance managed by the driver.
@@ -216,6 +220,7 @@ struct samsung_pin_ctrl {
struct samsung_pinctrl_drv_data {
struct list_head node;
void __iomem *virt_base;
+ void __iomem *ext_base;
struct device *dev;
int irq;
--
1.9.1
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| From | Tomasz Figa <tomasz.figa@gmail.com> |
|---|---|
| Date | 2016-08-16 09:00 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s6GvT-86R-5@gated-at.bofh.it> |
| In reply to | #1463447 |
Hi, 2016-08-16 15:27 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>: > From: Joonyoung Shim <jy0922.shim@samsung.com> > > This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has > different memory map of GPFx from previous Exynos SoC. Exynos GPIO has > following register to control gpio funciton. Usually, all registers of GPIO > are included in same domain. > - CON / DAT / PUD / DRV / CONPDN / PUDPDN > - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND > > But, GPFx are included in two domain as following. So, this patch supports > the GPFx pin which handle the on separate two domains. > - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN > - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND I'm afraid I don't get anything from the description above. Could you describe the layout of registers in memory map and IRQ routing of the pins? Best regards, Tomasz
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2016-08-16 10:50 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s6Iel-Nx-3@gated-at.bofh.it> |
| In reply to | #1463447 |
On 08/16/2016 08:27 AM, Chanwoo Choi wrote:
> From: Joonyoung Shim <jy0922.shim@samsung.com>
>
> This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has
> different memory map of GPFx from previous Exynos SoC. Exynos GPIO has
> following register to control gpio funciton. Usually, all registers of GPIO
> are included in same domain.
> - CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
>
> But, GPFx are included in two domain as following. So, this patch supports
> the GPFx pin which handle the on separate two domains.
> - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> .../bindings/pinctrl/samsung-pinctrl.txt | 1 +
> drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++
> drivers/pinctrl/samsung/pinctrl-exynos.h | 11 ++++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 43 ++++++++++++++++++----
> drivers/pinctrl/samsung/pinctrl-samsung.h | 5 +++
> 5 files changed, 57 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> index 6db16b90873a..807fba1f829f 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> @@ -19,6 +19,7 @@ Required Properties:
> - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
> - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
> - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
> + - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
>
> - reg: Base address of the pin controller hardware module and length of
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 051b5bf701a8..4f95983e0cdd 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1350,6 +1350,11 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
> EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
> EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
> EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004),
> + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008),
> + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014),
> };
>
> /* pin banks of exynos5433 pin-controller - AUD */
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 0f0f7cedb2dc..4b737b6c434d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -79,6 +79,17 @@
> .name = id \
> }
>
> +#define EXYNOS_PIN_BANK_EINTW_EXT(pins, reg, id, offs) \
> + { \
> + .type = &bank_type_off, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_WKUP, \
> + .eint_offset = offs, \
> + .eint_ext = true, \
> + .name = id \
> + }
> +
> /**
> * struct exynos_weint_data: irq specific data for all the wakeup interrupts
> * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 513fe6b23248..57e22085c2db 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -338,6 +338,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
> struct samsung_pin_bank **bank)
> {
> struct samsung_pin_bank *b;
> + void __iomem *virt_base = drvdata->virt_base;
>
> b = drvdata->pin_banks;
>
> @@ -345,7 +346,10 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
> ((b->pin_base + b->nr_pins - 1) < pin))
> b++;
>
> - *reg = drvdata->virt_base + b->pctl_offset;
> + if (b->eint_ext)
> + virt_base = drvdata->ext_base;
> +
> + *reg = virt_base + b->pctl_offset;
> *offset = pin - b->pin_base;
> if (bank)
> *bank = b;
> @@ -523,10 +527,12 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
> {
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + void __iomem *virt_base = bank->eint_ext ?
> + bank->drvdata->ext_base : bank->drvdata->virt_base;
I would prefer to avoid '?' operator because it makes the line difficult
to read. However I wonder whether this check here and later is needed at
all. It obfuscates the code so how about:
1. In pinctrl-samsung always access virt_base as it was before.
The virt_base in probe will be in domain of GPF_CON registers.
2. Rename ext_base to eint_base
3. Always assign eint_base in probe():
if (exynos5433)
eint_base = iomap()...
else
eint_base = virt_base;
4. in pinctrl-exynos.c access the eint_base.
No need of scattered if() through various calls and simpler flow.
> void __iomem *reg;
> u32 data;
>
> - reg = bank->drvdata->virt_base + bank->pctl_offset;
> + reg = virt_base + bank->pctl_offset;
>
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data &= ~(1 << offset);
> @@ -553,8 +559,10 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
> u32 data;
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + void __iomem *virt_base = bank->eint_ext ?
> + bank->drvdata->ext_base : bank->drvdata->virt_base;
>
> - reg = bank->drvdata->virt_base + bank->pctl_offset;
> + reg = virt_base + bank->pctl_offset;
>
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data >>= offset;
> @@ -574,6 +582,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> const struct samsung_pin_bank_type *type;
> struct samsung_pin_bank *bank;
> struct samsung_pinctrl_drv_data *drvdata;
> + void __iomem *virt_base;
> void __iomem *reg;
> u32 data, mask, shift;
>
> @@ -581,7 +590,8 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> type = bank->type;
> drvdata = bank->drvdata;
>
> - reg = drvdata->virt_base + bank->pctl_offset +
> + virt_base = bank->eint_ext ? drvdata->ext_base : drvdata->virt_base;
> + reg = virt_base + bank->pctl_offset +
> type->reg_offset[PINCFG_TYPE_FUNC];
>
> mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
> @@ -1007,6 +1017,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
> bank->eint_type = bdata->eint_type;
> bank->eint_mask = bdata->eint_mask;
> bank->eint_offset = bdata->eint_offset;
> + bank->eint_ext = bdata->eint_ext;
> bank->name = bdata->name;
>
> spin_lock_init(&bank->slock);
> @@ -1065,6 +1076,14 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
> if (IS_ERR(drvdata->virt_base))
> return PTR_ERR(drvdata->virt_base);
>
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Additional reg should be documented in bindings documentation.
Best regards,
Krzysztof
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-08-19 03:50 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s7H6x-7vO-1@gated-at.bofh.it> |
| In reply to | #1463447 |
On Tue, Aug 16, 2016 at 03:27:20PM +0900, Chanwoo Choi wrote: > From: Joonyoung Shim <jy0922.shim@samsung.com> > > This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has > different memory map of GPFx from previous Exynos SoC. Exynos GPIO has > following register to control gpio funciton. Usually, all registers of GPIO > are included in same domain. > - CON / DAT / PUD / DRV / CONPDN / PUDPDN > - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND > > But, GPFx are included in two domain as following. So, this patch supports > the GPFx pin which handle the on separate two domains. > - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN > - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND > > Cc: Linus Walleij <linus.walleij@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> > Cc: Kukjin Kim <kgene@kernel.org> > Cc: linux-gpio@vger.kernel.org > Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > .../bindings/pinctrl/samsung-pinctrl.txt | 1 + Acked-by: Rob Herring <robh@kernel.org> > drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++ > drivers/pinctrl/samsung/pinctrl-exynos.h | 11 ++++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 43 ++++++++++++++++++---- > drivers/pinctrl/samsung/pinctrl-samsung.h | 5 +++ > 5 files changed, 57 insertions(+), 8 deletions(-)
[toc] | [prev] | [next] | [standalone]
| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-19 11:10 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s7NYl-3GZ-19@gated-at.bofh.it> |
| In reply to | #1463447 |
Hi Tomasz Figa,
Due to wrong setting of email client,
your reply is deleted on my email client at the company.
I'm so sorry. So, I add your comment on below and then
I reply the detailed description.
On 2016년 08월 16일 15:27, Chanwoo Choi wrote:
> From: Joonyoung Shim <jy0922.shim@samsung.com>
>
> This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has
> different memory map of GPFx from previous Exynos SoC. Exynos GPIO has
> following register to control gpio funciton. Usually, all registers of GPIO
> are included in same domain.
> - CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
>
> But, GPFx are included in two domain as following. So, this patch supports
> the GPFx pin which handle the on separate two domains.
> - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
---------
I'm afraid I don't get anything from the description above. Could you
describe the layout of registers in memory map and IRQ routing of the
pins?
Best regards,
Tomasz
----------
On this patch, I'm sorry that I described the wrong information about GFP1~5.
I explained the memory map of GPF[1-5] the oppositely. Following compositions
are correct.
- ALIVE : WEINT_FLTCONx, WEINT_MASK, WEING_PEND
- IMEM : CON, DAT, PUD, DRV, CONPDN, PUDPDN
And, I add the memory map for GPF[1~5][2] and the wakeup interrupt information[1].
[1] Memory map for GPF1~5
[ALIVE]
WEINT_GPA0_CON : 0x1058_0000 (ALIVE) + (0x0700 = 0x0700 + 0x0)
WEINT_GPA1_CON : 0x1058_0000 (ALIVE) + (0x0704 = 0x0700 + 0x4)
WEINT_GPA2_CON : 0x1058_0000 (ALIVE) + (0x0708 = 0x0700 + 0x8)
WEINT_GPA3_CON : 0x1058_0000 (ALIVE) + (0x070C = 0x0700 + 0xC)
WEINT_GPF1_CON : 0x1058_0000 (ALIVE) + (0x1704 = 0x0700 + 0x1004)
WEINT_GPF2_CON : 0x1058_0000 (ALIVE) + (0x1708 = 0x0700 + 0x1008)
WEINT_GPF3_CON : 0x1058_0000 (ALIVE) + (0x170C = 0x0700 + 0x100C)
WEINT_GPF4_CON : 0x1058_0000 (ALIVE) + (0x1710 = 0x0700 + 0x10010)
WEINT_GPF5_CON : 0x1058_0000 (ALIVE) + (0x1714 = 0x0700 + 0x1014)
WEINT_GPF[x]_MASK : 0x1058_0000 (ALIVE) + (0x1900 + (x * 4))
WEINT_GPF[x]_PEND : 0x1058_0000 (ALIVE) + (0x1A00 + (x * 4))
(x : 1 ~ 5)
[IMEM]
GPF1_CON : 0X1109_0000 (IMEM) + 0x0020
GPF1_DAT : 0X1109_0000 (IMEM) + 0x0024
GPF1_PUD : 0X1109_0000 (IMEM) + 0x0028
GPF1_DRV : 0X1109_0000 (IMEM) + 0x002C
GPF1_CONPDN : 0X1109_0000 (IMEM) + 0x0030
GPF1_PUDPDN : 0X1109_0000 (IMEM) + 0x0034
GPF2_CON : 0X1109_0000 (IMEM) + 0x0040
...
GPF3_CON : 0X1109_0000 (IMEM) + 0x0060
...
GPF4_CON : 0X1109_0000 (IMEM) + 0x0080
...
GPF5_CON : 0X1109_0000 (IMEM) + 0x00A0
[2] Interrput pin information
- the total number of wakeup external IRQ is 64.
----------------------------------------------------------------------------------
domain| gpio : nr | wakeup interrput name | SPI number |
-----------------------------------------------------------------------------------
ALIVE | GPA0 : 8 | INTREQ__EINT[0~7] | SPI[0] ~ SPI[7] |
ALIVE | GPA1 : 8 | INTREQ__EINT[8~15] | SPI[8] ~ SPI[15] |
ALIVE | GPA2 : 8 | INTREQ__EINT_16_63 | SPI[16] |
ALIVE | GPA3 : 8 | INTREQ__EINT_16_63 | SPI[16] |
-----------------------------------------------------------------------------------
ALIVE | GPF1 : 8 | INTREQ__EINT_16_63 | SPI[16] |
ALIVE | GPF2 : 4 | INTREQ__EINT_16_63 | SPI[16] |
ALIVE | GPF3 : 4 | INTREQ__EINT_16_63 | SPI[16] |
ALIVE | GPF4 : 8 | INTREQ__EINT_16_63 | SPI[16] |
ALIVE | GPF5 : 8 | INTREQ__EINT_16_63 | SPI[16] |
-----------------------------------------------------------------------------------
In summary,
If gpf[1-5] handle the CON/DAT/PUD/DRV register,
the driver will use the drvdata->ext_base (IMEM base address)
instead of drvdata->virt_base(ALIVE base address)
because the CON/DAT/PUD/DRV register of gpf[1-5] are included
in the IMEM domain.
If gpf[1-5] handle the WEINT_* register,
the driver will use the drvdata->virt_base(ALIVE base address)
because the WEINT_* registers of gpf[1-5] are included in the ALIVE domain.
Best Regards,
Chanwoo Choi
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> .../bindings/pinctrl/samsung-pinctrl.txt | 1 +
> drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++
> drivers/pinctrl/samsung/pinctrl-exynos.h | 11 ++++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 43 ++++++++++++++++++----
> drivers/pinctrl/samsung/pinctrl-samsung.h | 5 +++
> 5 files changed, 57 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> index 6db16b90873a..807fba1f829f 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> @@ -19,6 +19,7 @@ Required Properties:
> - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
> - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
> - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
> + - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
>
> - reg: Base address of the pin controller hardware module and length of
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 051b5bf701a8..4f95983e0cdd 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1350,6 +1350,11 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
> EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
> EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
> EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004),
> + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008),
> + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010),
> + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014),
> };
>
> /* pin banks of exynos5433 pin-controller - AUD */
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 0f0f7cedb2dc..4b737b6c434d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -79,6 +79,17 @@
> .name = id \
> }
>
> +#define EXYNOS_PIN_BANK_EINTW_EXT(pins, reg, id, offs) \
> + { \
> + .type = &bank_type_off, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_WKUP, \
> + .eint_offset = offs, \
> + .eint_ext = true, \
> + .name = id \
> + }
> +
> /**
> * struct exynos_weint_data: irq specific data for all the wakeup interrupts
> * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 513fe6b23248..57e22085c2db 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -338,6 +338,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
> struct samsung_pin_bank **bank)
> {
> struct samsung_pin_bank *b;
> + void __iomem *virt_base = drvdata->virt_base;
>
> b = drvdata->pin_banks;
>
> @@ -345,7 +346,10 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
> ((b->pin_base + b->nr_pins - 1) < pin))
> b++;
>
> - *reg = drvdata->virt_base + b->pctl_offset;
> + if (b->eint_ext)
> + virt_base = drvdata->ext_base;
> +
> + *reg = virt_base + b->pctl_offset;
> *offset = pin - b->pin_base;
> if (bank)
> *bank = b;
> @@ -523,10 +527,12 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
> {
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + void __iomem *virt_base = bank->eint_ext ?
> + bank->drvdata->ext_base : bank->drvdata->virt_base;
> void __iomem *reg;
> u32 data;
>
> - reg = bank->drvdata->virt_base + bank->pctl_offset;
> + reg = virt_base + bank->pctl_offset;
>
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data &= ~(1 << offset);
> @@ -553,8 +559,10 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
> u32 data;
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + void __iomem *virt_base = bank->eint_ext ?
> + bank->drvdata->ext_base : bank->drvdata->virt_base;
>
> - reg = bank->drvdata->virt_base + bank->pctl_offset;
> + reg = virt_base + bank->pctl_offset;
>
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data >>= offset;
> @@ -574,6 +582,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> const struct samsung_pin_bank_type *type;
> struct samsung_pin_bank *bank;
> struct samsung_pinctrl_drv_data *drvdata;
> + void __iomem *virt_base;
> void __iomem *reg;
> u32 data, mask, shift;
>
> @@ -581,7 +590,8 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> type = bank->type;
> drvdata = bank->drvdata;
>
> - reg = drvdata->virt_base + bank->pctl_offset +
> + virt_base = bank->eint_ext ? drvdata->ext_base : drvdata->virt_base;
> + reg = virt_base + bank->pctl_offset +
> type->reg_offset[PINCFG_TYPE_FUNC];
>
> mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
> @@ -1007,6 +1017,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
> bank->eint_type = bdata->eint_type;
> bank->eint_mask = bdata->eint_mask;
> bank->eint_offset = bdata->eint_offset;
> + bank->eint_ext = bdata->eint_ext;
> bank->name = bdata->name;
>
> spin_lock_init(&bank->slock);
> @@ -1065,6 +1076,14 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
> if (IS_ERR(drvdata->virt_base))
> return PTR_ERR(drvdata->virt_base);
>
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (res) {
> + drvdata->ext_base =
> + devm_ioremap(dev, res->start, resource_size(res));
> + if (!drvdata->ext_base)
> + return -ENXIO;
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> if (res)
> drvdata->irq = res->start;
> @@ -1102,16 +1121,20 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
> static void samsung_pinctrl_suspend_dev(
> struct samsung_pinctrl_drv_data *drvdata)
> {
> - void __iomem *virt_base = drvdata->virt_base;
> + void __iomem *virt_base;
> int i;
>
> for (i = 0; i < drvdata->nr_banks; i++) {
> struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
> - void __iomem *reg = virt_base + bank->pctl_offset;
> + void __iomem *reg;
> const u8 *offs = bank->type->reg_offset;
> const u8 *widths = bank->type->fld_width;
> enum pincfg_type type;
>
> + virt_base = bank->eint_ext ?
> + drvdata->ext_base : drvdata->virt_base;
> + reg = virt_base + bank->pctl_offset;
> +
> /* Registers without a powerdown config aren't lost */
> if (!widths[PINCFG_TYPE_CON_PDN])
> continue;
> @@ -1148,7 +1171,7 @@ static void samsung_pinctrl_suspend_dev(
> */
> static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
> {
> - void __iomem *virt_base = drvdata->virt_base;
> + void __iomem *virt_base;
> int i;
>
> if (drvdata->resume)
> @@ -1156,11 +1179,15 @@ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
>
> for (i = 0; i < drvdata->nr_banks; i++) {
> struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
> - void __iomem *reg = virt_base + bank->pctl_offset;
> + void __iomem *reg;
> const u8 *offs = bank->type->reg_offset;
> const u8 *widths = bank->type->fld_width;
> enum pincfg_type type;
>
> + virt_base = bank->eint_ext ?
> + drvdata->ext_base : drvdata->virt_base;
> + reg = virt_base + bank->pctl_offset;
> +
> /* Registers without a powerdown config aren't lost */
> if (!widths[PINCFG_TYPE_CON_PDN])
> continue;
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index cd31bfaf62cb..3005135f4565 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -131,6 +131,7 @@ struct samsung_pin_bank_data {
> enum eint_type eint_type;
> u32 eint_mask;
> u32 eint_offset;
> + bool eint_ext;
> const char *name;
> };
>
> @@ -163,6 +164,7 @@ struct samsung_pin_bank {
> enum eint_type eint_type;
> u32 eint_mask;
> u32 eint_offset;
> + bool eint_ext;
> const char *name;
>
> u32 pin_base;
> @@ -201,6 +203,8 @@ struct samsung_pin_ctrl {
> * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
> * @node: global list node
> * @virt_base: register base address of the controller.
> + * @ext_base: external register base address of the controller.
> + * @ext_base: external register base address of the controller.
> * @dev: device instance representing the controller.
> * @irq: interrpt number used by the controller to notify gpio interrupts.
> * @ctrl: pin controller instance managed by the driver.
> @@ -216,6 +220,7 @@ struct samsung_pin_ctrl {
> struct samsung_pinctrl_drv_data {
> struct list_head node;
> void __iomem *virt_base;
> + void __iomem *ext_base;
> struct device *dev;
> int irq;
>
>
[toc] | [prev] | [next] | [standalone]
| From | Tomasz Figa <tomasz.figa@gmail.com> |
|---|---|
| Date | 2016-08-19 13:40 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s7Qjv-52h-9@gated-at.bofh.it> |
| In reply to | #1466244 |
Hi Chanwoo, 2016-08-19 18:07 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>: > Hi Tomasz Figa, > > Due to wrong setting of email client, > your reply is deleted on my email client at the company. I used Gmail (in plain text mode) to reply, was that related? > I'm so sorry. So, I add your comment on below and then > I reply the detailed description. No problem. Thanks for description. > > On 2016년 08월 16일 15:27, Chanwoo Choi wrote: >> From: Joonyoung Shim <jy0922.shim@samsung.com> >> >> This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has >> different memory map of GPFx from previous Exynos SoC. Exynos GPIO has >> following register to control gpio funciton. Usually, all registers of GPIO >> are included in same domain. >> - CON / DAT / PUD / DRV / CONPDN / PUDPDN >> - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND >> >> But, GPFx are included in two domain as following. So, this patch supports >> the GPFx pin which handle the on separate two domains. >> - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN >> - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND > > --------- > I'm afraid I don't get anything from the description above. Could you > describe the layout of registers in memory map and IRQ routing of the > pins? > > Best regards, > Tomasz > ---------- > > On this patch, I'm sorry that I described the wrong information about GFP1~5. > I explained the memory map of GPF[1-5] the oppositely. Following compositions > are correct. > - ALIVE : WEINT_FLTCONx, WEINT_MASK, WEING_PEND > - IMEM : CON, DAT, PUD, DRV, CONPDN, PUDPDN > And, I add the memory map for GPF[1~5][2] and the wakeup interrupt information[1]. > > [1] Memory map for GPF1~5 > [ALIVE] > WEINT_GPA0_CON : 0x1058_0000 (ALIVE) + (0x0700 = 0x0700 + 0x0) > WEINT_GPA1_CON : 0x1058_0000 (ALIVE) + (0x0704 = 0x0700 + 0x4) > WEINT_GPA2_CON : 0x1058_0000 (ALIVE) + (0x0708 = 0x0700 + 0x8) > WEINT_GPA3_CON : 0x1058_0000 (ALIVE) + (0x070C = 0x0700 + 0xC) > > WEINT_GPF1_CON : 0x1058_0000 (ALIVE) + (0x1704 = 0x0700 + 0x1004) > WEINT_GPF2_CON : 0x1058_0000 (ALIVE) + (0x1708 = 0x0700 + 0x1008) > WEINT_GPF3_CON : 0x1058_0000 (ALIVE) + (0x170C = 0x0700 + 0x100C) > WEINT_GPF4_CON : 0x1058_0000 (ALIVE) + (0x1710 = 0x0700 + 0x10010) > WEINT_GPF5_CON : 0x1058_0000 (ALIVE) + (0x1714 = 0x0700 + 0x1014) > > WEINT_GPF[x]_MASK : 0x1058_0000 (ALIVE) + (0x1900 + (x * 4)) > WEINT_GPF[x]_PEND : 0x1058_0000 (ALIVE) + (0x1A00 + (x * 4)) > (x : 1 ~ 5) > > [IMEM] > GPF1_CON : 0X1109_0000 (IMEM) + 0x0020 > GPF1_DAT : 0X1109_0000 (IMEM) + 0x0024 > GPF1_PUD : 0X1109_0000 (IMEM) + 0x0028 > GPF1_DRV : 0X1109_0000 (IMEM) + 0x002C > GPF1_CONPDN : 0X1109_0000 (IMEM) + 0x0030 > GPF1_PUDPDN : 0X1109_0000 (IMEM) + 0x0034 > > GPF2_CON : 0X1109_0000 (IMEM) + 0x0040 > ... > GPF3_CON : 0X1109_0000 (IMEM) + 0x0060 > ... > GPF4_CON : 0X1109_0000 (IMEM) + 0x0080 > ... > GPF5_CON : 0X1109_0000 (IMEM) + 0x00A0 > > [2] Interrput pin information > - the total number of wakeup external IRQ is 64. > ---------------------------------------------------------------------------------- > domain| gpio : nr | wakeup interrput name | SPI number | > ----------------------------------------------------------------------------------- > ALIVE | GPA0 : 8 | INTREQ__EINT[0~7] | SPI[0] ~ SPI[7] | > ALIVE | GPA1 : 8 | INTREQ__EINT[8~15] | SPI[8] ~ SPI[15] | > ALIVE | GPA2 : 8 | INTREQ__EINT_16_63 | SPI[16] | > ALIVE | GPA3 : 8 | INTREQ__EINT_16_63 | SPI[16] | > ----------------------------------------------------------------------------------- > ALIVE | GPF1 : 8 | INTREQ__EINT_16_63 | SPI[16] | > ALIVE | GPF2 : 4 | INTREQ__EINT_16_63 | SPI[16] | > ALIVE | GPF3 : 4 | INTREQ__EINT_16_63 | SPI[16] | > ALIVE | GPF4 : 8 | INTREQ__EINT_16_63 | SPI[16] | > ALIVE | GPF5 : 8 | INTREQ__EINT_16_63 | SPI[16] | > ----------------------------------------------------------------------------------- > > In summary, > If gpf[1-5] handle the CON/DAT/PUD/DRV register, > the driver will use the drvdata->ext_base (IMEM base address) > instead of drvdata->virt_base(ALIVE base address) > because the CON/DAT/PUD/DRV register of gpf[1-5] are included > in the IMEM domain. > > If gpf[1-5] handle the WEINT_* register, > the driver will use the drvdata->virt_base(ALIVE base address) > because the WEINT_* registers of gpf[1-5] are included in the ALIVE domain. Okay, so Krzysztof's suggestion doesn't apply because it's not the eint base which is displaced, but the pinctrl base. I'd suggest the following solution then: - make samsung_pinctrl_drv_data::virt_base an array and save there all mapped iomem resources, - add unsigned pctl_base_res_idx to samsung_pin_bank_data that would be the index of iomem resource into which the samsung_pin_bank_data::pctl_offset is an offfset, Existing EXYNOS_PIN_BANK* macros don't need to be changed, because the field would be 0 by default. Then only the new bank type macro would have another argument that would be the resource index, - replace samsung_pin_bank::pctl_offset with void __iomem *pctl_base and precalculate the addresses at probe time for each bank (pctl_base = virt_base[pctl_base_res_idx] + samsung_pin_bank_data::pctl_offset). Since currently there is only a problem with pctl_base and eint_base seems to be only one, EINT code can simply use virt_base[0] all the time for now. Also you should document the second regs entry in the DT binding. What do you think? Best regards, Tomasz
[toc] | [prev] | [next] | [standalone]
| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-24 15:00 +0200 |
| Subject | Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433 |
| Message-ID | <s9FWF-2mk-7@gated-at.bofh.it> |
| In reply to | #1466303 |
Hi Tomasz, I'm sorry for delay reply. On 2016년 08월 19일 20:31, Tomasz Figa wrote: > Hi Chanwoo, > > 2016-08-19 18:07 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>: >> Hi Tomasz Figa, >> >> Due to wrong setting of email client, >> your reply is deleted on my email client at the company. > > I used Gmail (in plain text mode) to reply, was that related? The mistake depend on my filer setting of mail client. > >> I'm so sorry. So, I add your comment on below and then >> I reply the detailed description. > > No problem. Thanks for description. > >> >> On 2016년 08월 16일 15:27, Chanwoo Choi wrote: >>> From: Joonyoung Shim <jy0922.shim@samsung.com> >>> >>> This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has >>> different memory map of GPFx from previous Exynos SoC. Exynos GPIO has >>> following register to control gpio funciton. Usually, all registers of GPIO >>> are included in same domain. >>> - CON / DAT / PUD / DRV / CONPDN / PUDPDN >>> - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND >>> >>> But, GPFx are included in two domain as following. So, this patch supports >>> the GPFx pin which handle the on separate two domains. >>> - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN >>> - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND >> >> --------- >> I'm afraid I don't get anything from the description above. Could you >> describe the layout of registers in memory map and IRQ routing of the >> pins? >> >> Best regards, >> Tomasz >> ---------- >> >> On this patch, I'm sorry that I described the wrong information about GFP1~5. >> I explained the memory map of GPF[1-5] the oppositely. Following compositions >> are correct. >> - ALIVE : WEINT_FLTCONx, WEINT_MASK, WEING_PEND >> - IMEM : CON, DAT, PUD, DRV, CONPDN, PUDPDN >> And, I add the memory map for GPF[1~5][2] and the wakeup interrupt information[1]. >> >> [1] Memory map for GPF1~5 >> [ALIVE] >> WEINT_GPA0_CON : 0x1058_0000 (ALIVE) + (0x0700 = 0x0700 + 0x0) >> WEINT_GPA1_CON : 0x1058_0000 (ALIVE) + (0x0704 = 0x0700 + 0x4) >> WEINT_GPA2_CON : 0x1058_0000 (ALIVE) + (0x0708 = 0x0700 + 0x8) >> WEINT_GPA3_CON : 0x1058_0000 (ALIVE) + (0x070C = 0x0700 + 0xC) >> >> WEINT_GPF1_CON : 0x1058_0000 (ALIVE) + (0x1704 = 0x0700 + 0x1004) >> WEINT_GPF2_CON : 0x1058_0000 (ALIVE) + (0x1708 = 0x0700 + 0x1008) >> WEINT_GPF3_CON : 0x1058_0000 (ALIVE) + (0x170C = 0x0700 + 0x100C) >> WEINT_GPF4_CON : 0x1058_0000 (ALIVE) + (0x1710 = 0x0700 + 0x10010) >> WEINT_GPF5_CON : 0x1058_0000 (ALIVE) + (0x1714 = 0x0700 + 0x1014) >> >> WEINT_GPF[x]_MASK : 0x1058_0000 (ALIVE) + (0x1900 + (x * 4)) >> WEINT_GPF[x]_PEND : 0x1058_0000 (ALIVE) + (0x1A00 + (x * 4)) >> (x : 1 ~ 5) >> >> [IMEM] >> GPF1_CON : 0X1109_0000 (IMEM) + 0x0020 >> GPF1_DAT : 0X1109_0000 (IMEM) + 0x0024 >> GPF1_PUD : 0X1109_0000 (IMEM) + 0x0028 >> GPF1_DRV : 0X1109_0000 (IMEM) + 0x002C >> GPF1_CONPDN : 0X1109_0000 (IMEM) + 0x0030 >> GPF1_PUDPDN : 0X1109_0000 (IMEM) + 0x0034 >> >> GPF2_CON : 0X1109_0000 (IMEM) + 0x0040 >> ... >> GPF3_CON : 0X1109_0000 (IMEM) + 0x0060 >> ... >> GPF4_CON : 0X1109_0000 (IMEM) + 0x0080 >> ... >> GPF5_CON : 0X1109_0000 (IMEM) + 0x00A0 >> >> [2] Interrput pin information >> - the total number of wakeup external IRQ is 64. >> ---------------------------------------------------------------------------------- >> domain| gpio : nr | wakeup interrput name | SPI number | >> ----------------------------------------------------------------------------------- >> ALIVE | GPA0 : 8 | INTREQ__EINT[0~7] | SPI[0] ~ SPI[7] | >> ALIVE | GPA1 : 8 | INTREQ__EINT[8~15] | SPI[8] ~ SPI[15] | >> ALIVE | GPA2 : 8 | INTREQ__EINT_16_63 | SPI[16] | >> ALIVE | GPA3 : 8 | INTREQ__EINT_16_63 | SPI[16] | >> ----------------------------------------------------------------------------------- >> ALIVE | GPF1 : 8 | INTREQ__EINT_16_63 | SPI[16] | >> ALIVE | GPF2 : 4 | INTREQ__EINT_16_63 | SPI[16] | >> ALIVE | GPF3 : 4 | INTREQ__EINT_16_63 | SPI[16] | >> ALIVE | GPF4 : 8 | INTREQ__EINT_16_63 | SPI[16] | >> ALIVE | GPF5 : 8 | INTREQ__EINT_16_63 | SPI[16] | >> ----------------------------------------------------------------------------------- >> >> In summary, >> If gpf[1-5] handle the CON/DAT/PUD/DRV register, >> the driver will use the drvdata->ext_base (IMEM base address) >> instead of drvdata->virt_base(ALIVE base address) >> because the CON/DAT/PUD/DRV register of gpf[1-5] are included >> in the IMEM domain. >> >> If gpf[1-5] handle the WEINT_* register, >> the driver will use the drvdata->virt_base(ALIVE base address) >> because the WEINT_* registers of gpf[1-5] are included in the ALIVE domain. > > Okay, so Krzysztof's suggestion doesn't apply because it's not the > eint base which is displaced, but the pinctrl base. I'd suggest the > following solution then: > > - make samsung_pinctrl_drv_data::virt_base an array and save there all > mapped iomem resources, > > - add unsigned pctl_base_res_idx to samsung_pin_bank_data that would > be the index of iomem resource into which the > samsung_pin_bank_data::pctl_offset is an offfset, Existing > EXYNOS_PIN_BANK* macros don't need to be changed, because the field > would be 0 by default. Then only the new bank type macro would have > another argument that would be the resource index, > > - replace samsung_pin_bank::pctl_offset with void __iomem *pctl_base > and precalculate the addresses at probe time for each bank (pctl_base > = virt_base[pctl_base_res_idx] + samsung_pin_bank_data::pctl_offset). > Since currently there is only a problem with pctl_base and eint_base > seems to be only one, EINT code can simply use virt_base[0] all the > time for now. > > Also you should document the second regs entry in the DT binding. > > What do you think? I understand. I suggest the one thing. I think that we need to add the 'eint_base_idx' for WEINT registers which is handled on pinctrl-exynos.c because the composition of gpio registers might be exchanged against the Exynos5433's GPFx. "drvdata->virt_base[pctl_res_idx]" will be used on pinctrl-samsung.c. "drvdata->virt_base[eint_res_idx]" will be used on pinctrl-exynos.c. As your suggestion, I make a patch and this patch is well working. I'll send the new patch for samsung pinctrl driver on v2 patchset. -- Best Regards, Chanwoo Choi
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:30 +0200 |
| Subject | [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible |
| Message-ID | <s6G2S-7Xd-23@gated-at.bofh.it> |
| In reply to | #1463443 |
This patch adds the exynos5433 PMU compatible to support the access of PMU (Power Management Unit) block. Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index 2d6356d8daf4..bf5fc59a6938 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -10,6 +10,7 @@ Properties: - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - "samsung,exynos5420-pmu" - for Exynos5420 SoC. + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - "samsung,exynos7-pmu" - for Exynos7 SoC. second value must be always "syscon". -- 1.9.1
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2016-08-16 09:50 +0200 |
| Subject | Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible |
| Message-ID | <s6Hii-c3-13@gated-at.bofh.it> |
| In reply to | #1463448 |
On 08/16/2016 08:27 AM, Chanwoo Choi wrote: > This patch adds the exynos5433 PMU compatible to support the access > of PMU (Power Management Unit) block. > > Cc: Kukjin Kim <kgene@kernel.org> > Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt > index 2d6356d8daf4..bf5fc59a6938 100644 > --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt > +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt > @@ -10,6 +10,7 @@ Properties: > - "samsung,exynos5260-pmu" - for Exynos5260 SoC. > - "samsung,exynos5410-pmu" - for Exynos5410 SoC, > - "samsung,exynos5420-pmu" - for Exynos5420 SoC. > + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. > - "samsung,exynos7-pmu" - for Exynos7 SoC. > second value must be always "syscon". Is there any plan to add Exynos5433 support to drivers/soc/samsung/exynos-pmu.c? If no... then exynos7-pmu might be reused. If yes, then this makes sense. Best regards, Krzysztof
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 10:10 +0200 |
| Subject | Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible |
| Message-ID | <s6HBD-ym-1@gated-at.bofh.it> |
| In reply to | #1463505 |
Hi Krzysztof, On 2016년 08월 16일 16:40, Krzysztof Kozlowski wrote: > On 08/16/2016 08:27 AM, Chanwoo Choi wrote: >> This patch adds the exynos5433 PMU compatible to support the access >> of PMU (Power Management Unit) block. >> >> Cc: Kukjin Kim <kgene@kernel.org> >> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> >> Cc: Rob Herring <robh+dt@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> --- >> Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt >> index 2d6356d8daf4..bf5fc59a6938 100644 >> --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt >> +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt >> @@ -10,6 +10,7 @@ Properties: >> - "samsung,exynos5260-pmu" - for Exynos5260 SoC. >> - "samsung,exynos5410-pmu" - for Exynos5410 SoC, >> - "samsung,exynos5420-pmu" - for Exynos5420 SoC. >> + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. >> - "samsung,exynos7-pmu" - for Exynos7 SoC. >> second value must be always "syscon". > > Is there any plan to add Exynos5433 support to > drivers/soc/samsung/exynos-pmu.c? If no... then exynos7-pmu might be > reused. If yes, then this makes sense. Yes. I'll support the suspend-to-ram for Exynos5433. But it is not right now. because the current kernel support the suspend-to-ram for only 32-bit Exynos. and the pm/suspend code are included in in arch/arm/mach-exynos/. To support the suspend-to-ram for 64bit Exynos, I need a lot of time to support the 64-bit suspend. Regards, Chanwoo Choi
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2016-08-16 10:20 +0200 |
| Subject | Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible |
| Message-ID | <s6HLk-BJ-23@gated-at.bofh.it> |
| In reply to | #1463517 |
On 08/16/2016 10:08 AM, Chanwoo Choi wrote: > Hi Krzysztof, > > On 2016년 08월 16일 16:40, Krzysztof Kozlowski wrote: >> On 08/16/2016 08:27 AM, Chanwoo Choi wrote: >>> This patch adds the exynos5433 PMU compatible to support the access >>> of PMU (Power Management Unit) block. >>> >>> Cc: Kukjin Kim <kgene@kernel.org> >>> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> >>> Cc: Rob Herring <robh+dt@kernel.org> >>> Cc: Mark Rutland <mark.rutland@arm.com> >>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >>> --- >>> Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt >>> index 2d6356d8daf4..bf5fc59a6938 100644 >>> --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt >>> +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt >>> @@ -10,6 +10,7 @@ Properties: >>> - "samsung,exynos5260-pmu" - for Exynos5260 SoC. >>> - "samsung,exynos5410-pmu" - for Exynos5410 SoC, >>> - "samsung,exynos5420-pmu" - for Exynos5420 SoC. >>> + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. >>> - "samsung,exynos7-pmu" - for Exynos7 SoC. >>> second value must be always "syscon". >> >> Is there any plan to add Exynos5433 support to >> drivers/soc/samsung/exynos-pmu.c? If no... then exynos7-pmu might be >> reused. If yes, then this makes sense. > > Yes. > I'll support the suspend-to-ram for Exynos5433. But it is not right now. > because the current kernel support the suspend-to-ram for only 32-bit Exynos. > and the pm/suspend code are included in in arch/arm/mach-exynos/. > > To support the suspend-to-ram for 64bit Exynos, I need a lot of time > to support the 64-bit suspend. OK, make sense. Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-08-19 04:00 +0200 |
| Subject | Re: [PATCH 2/7] Documentation: bindings: Add Exynos5433 PMU compatible |
| Message-ID | <s7Hge-7z4-33@gated-at.bofh.it> |
| In reply to | #1463448 |
On Tue, Aug 16, 2016 at 03:27:18PM +0900, Chanwoo Choi wrote: > This patch adds the exynos5433 PMU compatible to support the access > of PMU (Power Management Unit) block. > > Cc: Kukjin Kim <kgene@kernel.org> > Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org>
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:30 +0200 |
| Subject | [PATCH 1/7] clocksource: exynos_mct: Add the support for Exynos 64bit SoC |
| Message-ID | <s6G2S-7Xd-25@gated-at.bofh.it> |
| In reply to | #1463443 |
This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for 32bit SoC.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/exynos_mct.c | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 567788664723..ec443c318c77 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -351,7 +351,7 @@ config CLKSRC_METAG_GENERIC
config CLKSRC_EXYNOS_MCT
bool "Exynos multi core timer driver" if COMPILE_TEST
- depends on ARM
+ depends on ARM || ARM64
help
Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 41840d02c331..8f3488b80896 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
}
+#if defined(CONFIG_ARM)
static struct delay_timer exynos4_delay_timer;
static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
"cycles_t needs to move to 32-bit for ARM64 usage");
return exynos4_read_count_32();
}
+#endif
static int __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(&exynos4_delay_timer);
+#endif
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);
--
1.9.1
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-16 08:40 +0200 |
| Subject | [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board |
| Message-ID | <s6Gcx-80i-1@gated-at.bofh.it> |
| In reply to | #1463443 |
This patcha adds the Device Tree source for Exynos5433-based Samsung TM2E
board. TM2E board is the most similiar with TM2 board. The exynos5433-tm2e.dts
include the difference between TM2 and TM2E.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
.../bindings/arm/samsung/samsung-boards.txt | 1 +
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 ++++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index c704b4bf6137..c1bda8d3674c 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -16,6 +16,7 @@ Required root node properties:
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- "samsung,tm2" - for Exynos5333-based Samsung TM2 board.
+ - "samsung,tm2e" - for Exynos5333-based Samsung TM2E board.
- "samsung,sd5v1" - for Exynos5440-based Samsung board.
- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
new file mode 100644
index 000000000000..283b4fd19d5a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -0,0 +1,41 @@
+/*
+ * SAMSUNG Exynos5433 TM2E board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
+ * Samsung Exynos5433 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5433-tm2.dts"
+
+/ {
+ model = "Samsung TM2E board";
+ compatible = "samsung,exynos5433-tm2e", "samsung,exynos5433";
+};
+
+&ldo23_reg {
+ regulator-name = "CAM_SEN_CORE_1.025V_AP";
+ regulator-max-microvolt = <1050000>;
+};
+
+&ldo25_reg {
+ regulator-name = "UNUSED_LDO25";
+ regulator-always-off;
+};
+
+&ldo31_reg {
+ regulator-name = "TSP_VDD_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+};
+
+&ldo38_reg {
+ regulator-name = "VCC_3.3V_MOTOR_AP";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
--
1.9.1
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2016-08-17 08:50 +0200 |
| Subject | Re: [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board |
| Message-ID | <s72PL-5MN-1@gated-at.bofh.it> |
| In reply to | #1463450 |
On 08/16/2016 08:35 AM, Chanwoo Choi wrote: > This patcha adds the Device Tree source for Exynos5433-based Samsung TM2E s/patcha/patch/ > board. TM2E board is the most similiar with TM2 board. The exynos5433-tm2e.dts s/similiar/similar/ > include the difference between TM2 and TM2E. > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> > Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> > Signed-off-by: Inki Dae <inki.dae@samsung.com> > Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> > Signed-off-by: Beomho Seo <beomho.seo@samsung.com> > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > Signed-off-by: Inha Song <ideal.song@samsung.com> > Signed-off-by: Ingi kim <ingi2.kim@samsung.com> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- > .../bindings/arm/samsung/samsung-boards.txt | 1 + > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 ++++++++++++++++++++++ > 2 files changed, 42 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts > > diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt > index c704b4bf6137..c1bda8d3674c 100644 > --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt > +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt > @@ -16,6 +16,7 @@ Required root node properties: > - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. > - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. > - "samsung,tm2" - for Exynos5333-based Samsung TM2 board. > + - "samsung,tm2e" - for Exynos5333-based Samsung TM2E board. > - "samsung,sd5v1" - for Exynos5440-based Samsung board. > - "samsung,ssdk5440" - for Exynos5440-based Samsung board. > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts > new file mode 100644 > index 000000000000..283b4fd19d5a > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts > @@ -0,0 +1,41 @@ > +/* > + * SAMSUNG Exynos5433 TM2E board device tree source > + * > + * Copyright (c) 2016 Samsung Electronics Co., Ltd. > + * > + * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on > + * Samsung Exynos5433 SoC. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include "exynos5433-tm2.dts" > + Cool! Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2016-08-17 09:40 +0200 |
| Subject | Re: [PATCH 7/7] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board |
| Message-ID | <s73C9-6mv-11@gated-at.bofh.it> |
| In reply to | #1464346 |
Hi Krzysztof, On 2016년 08월 17일 15:43, Krzysztof Kozlowski wrote: > On 08/16/2016 08:35 AM, Chanwoo Choi wrote: >> This patcha adds the Device Tree source for Exynos5433-based Samsung TM2E > > s/patcha/patch/ OK. > >> board. TM2E board is the most similiar with TM2 board. The exynos5433-tm2e.dts > > s/similiar/similar/ OK. > >> include the difference between TM2 and TM2E. >> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> >> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> >> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> >> Signed-off-by: Inki Dae <inki.dae@samsung.com> >> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> >> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> >> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> >> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> >> Signed-off-by: Inha Song <ideal.song@samsung.com> >> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> >> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> >> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> >> --- >> .../bindings/arm/samsung/samsung-boards.txt | 1 + >> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 ++++++++++++++++++++++ >> 2 files changed, 42 insertions(+) >> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts >> >> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt >> index c704b4bf6137..c1bda8d3674c 100644 >> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt >> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt >> @@ -16,6 +16,7 @@ Required root node properties: >> - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. >> - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. >> - "samsung,tm2" - for Exynos5333-based Samsung TM2 board. >> + - "samsung,tm2e" - for Exynos5333-based Samsung TM2E board. >> - "samsung,sd5v1" - for Exynos5440-based Samsung board. >> - "samsung,ssdk5440" - for Exynos5440-based Samsung board. >> >> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts >> new file mode 100644 >> index 000000000000..283b4fd19d5a >> --- /dev/null >> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts >> @@ -0,0 +1,41 @@ >> +/* >> + * SAMSUNG Exynos5433 TM2E board device tree source >> + * >> + * Copyright (c) 2016 Samsung Electronics Co., Ltd. >> + * >> + * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on >> + * Samsung Exynos5433 SoC. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#include "exynos5433-tm2.dts" >> + > > Cool! > > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Thanks for the review. Best regards, Chanwoo Choi
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