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| Started by | Shawn Lin <shawn.lin@rock-chips.com> |
|---|---|
| First post | 2016-08-19 03:50 +0200 |
| Last post | 2016-08-20 04:40 +0200 |
| Articles | 3 — 2 participants |
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[PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller Shawn Lin <shawn.lin@rock-chips.com> - 2016-08-19 03:50 +0200
Re: [PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller Bjorn Helgaas <helgaas@kernel.org> - 2016-08-19 21:40 +0200
Re: [PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller Shawn Lin <shawn.lin@rock-chips.com> - 2016-08-20 04:40 +0200
| From | Shawn Lin <shawn.lin@rock-chips.com> |
|---|---|
| Date | 2016-08-19 03:50 +0200 |
| Subject | [PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller |
| Message-ID | <s7H6x-7vO-7@gated-at.bofh.it> |
This patch adds a binding that describes the Rockchip PCIe controller
found on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
---
Changes in v10:
- fix broken description of msi-map
- s/pcie/PCIe for description
Changes in v9: None
Changes in v8:
- add Brian's review-tag
Changes in v7:
- move optional properties ahead of interrupt subnode
- use 0-base index for INTx
Changes in v6:
- add ack tag from Rob
Changes in v5:
- fix wrong example reported by Marc
- add seperate section to describe the interrupt controller child
node
Changes in v4:
- fix example of adding intermediate interrupt controller for pcie
legacy interrrupt
Changes in v3:
- fix example dts code suggested by Rob and Marc
- remove driver's behaviour of regulator
Changes in v2:
- fix lots clk/reset stuff suggested by Heiko
- remove msi-parent and add msi-map suggested by Marc
- drop phy related stuff
- some others minor fixes
.../devicetree/bindings/pci/rockchip-pcie.txt | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
new file mode 100644
index 0000000..ba67b39
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -0,0 +1,106 @@
+* Rockchip AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "rockchip,rk3399-pcie"
+- reg: Two register ranges as listed in the reg-names property
+- reg-names: Must include the following names
+ - "axi-base"
+ - "apb-base"
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - "aclk"
+ - "aclk-perf"
+ - "hclk"
+ - "pm"
+- msi-map: Maps a Requester ID to an MSI controller and associated
+ msi-specifier data. See ./pci-msi.txt
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names: MUST be "pcie-phy".
+- interrupts: Three interrupt entries must be specified.
+- interrupt-names: Must include the following names
+ - "sys"
+ - "legacy"
+ - "client"
+- resets: Must contain five entries for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following names
+ - "core"
+ - "mgmt"
+ - "mgmt-sticky"
+ - "pipe"
+- pinctrl-names : The pin control state names
+- pinctrl-0: The "default" pinctrl state
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- interrupt-map-mask and interrupt-map: standard PCI properties
+
+Optional Property:
+- ep-gpios: contain the entry for pre-reset gpio
+- num-lanes: number of lanes to use
+- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
+- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
+- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
+
+*Interrupt controller child node*
+The core controller provides a single interrupt for legacy INTx. The PCIe node
+should contain an interrupt controller node as a target for the PCI
+'interrupt-map' property. This node represents the domain at which the four
+INTx interrupts are decoded and routed.
+
+
+Required properties for Interrupt controller child node:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+Example:
+
+pcie0: pcie@f8000000 {
+ compatible = "rockchip,rk3399-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+ <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+ clock-names = "aclk", "aclk-perf",
+ "hclk", "pm";
+ bus-range = <0x0 0x1>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "legacy", "client";
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
+ 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+ num-lanes = <4>;
+ msi-map = <0x0 &its 0x0 0x1000>;
+ reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
+ reg-names = "axi-base", "apb-base";
+ resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreq>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+};
--
2.3.7
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| From | Bjorn Helgaas <helgaas@kernel.org> |
|---|---|
| Date | 2016-08-19 21:40 +0200 |
| Subject | Re: [PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller |
| Message-ID | <s7XO1-1lr-13@gated-at.bofh.it> |
| In reply to | #1465834 |
On Fri, Aug 19, 2016 at 09:34:31AM +0800, Shawn Lin wrote:
> This patch adds a binding that describes the Rockchip PCIe controller
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Brian Norris <briannorris@chromium.org>
I applied both of these to pci/host-rockchip for v4.9, thanks, Shawn!
I made a few whitespace and typo fixes in pcie-rockchip.c, so take a
look and make sure I didn't break anything.
> ---
>
> Changes in v10:
> - fix broken description of msi-map
> - s/pcie/PCIe for description
>
> Changes in v9: None
> Changes in v8:
> - add Brian's review-tag
>
> Changes in v7:
> - move optional properties ahead of interrupt subnode
> - use 0-base index for INTx
>
> Changes in v6:
> - add ack tag from Rob
>
> Changes in v5:
> - fix wrong example reported by Marc
> - add seperate section to describe the interrupt controller child
> node
>
> Changes in v4:
> - fix example of adding intermediate interrupt controller for pcie
> legacy interrrupt
>
> Changes in v3:
> - fix example dts code suggested by Rob and Marc
> - remove driver's behaviour of regulator
>
> Changes in v2:
> - fix lots clk/reset stuff suggested by Heiko
> - remove msi-parent and add msi-map suggested by Marc
> - drop phy related stuff
> - some others minor fixes
>
> .../devicetree/bindings/pci/rockchip-pcie.txt | 106 +++++++++++++++++++++
> 1 file changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
> new file mode 100644
> index 0000000..ba67b39
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
> @@ -0,0 +1,106 @@
> +* Rockchip AXI PCIe Root Port Bridge DT description
> +
> +Required properties:
> +- #address-cells: Address representation for root ports, set to <3>
> +- #size-cells: Size representation for root ports, set to <2>
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +- compatible: Should contain "rockchip,rk3399-pcie"
> +- reg: Two register ranges as listed in the reg-names property
> +- reg-names: Must include the following names
> + - "axi-base"
> + - "apb-base"
> +- clocks: Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> +- clock-names: Must include the following entries:
> + - "aclk"
> + - "aclk-perf"
> + - "hclk"
> + - "pm"
> +- msi-map: Maps a Requester ID to an MSI controller and associated
> + msi-specifier data. See ./pci-msi.txt
> +- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
> +- phy-names: MUST be "pcie-phy".
> +- interrupts: Three interrupt entries must be specified.
> +- interrupt-names: Must include the following names
> + - "sys"
> + - "legacy"
> + - "client"
> +- resets: Must contain five entries for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +- reset-names: Must include the following names
> + - "core"
> + - "mgmt"
> + - "mgmt-sticky"
> + - "pipe"
> +- pinctrl-names : The pin control state names
> +- pinctrl-0: The "default" pinctrl state
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +- interrupt-map-mask and interrupt-map: standard PCI properties
> +
> +Optional Property:
> +- ep-gpios: contain the entry for pre-reset gpio
> +- num-lanes: number of lanes to use
> +- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
> +- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
> +- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
> +
> +*Interrupt controller child node*
> +The core controller provides a single interrupt for legacy INTx. The PCIe node
> +should contain an interrupt controller node as a target for the PCI
> +'interrupt-map' property. This node represents the domain at which the four
> +INTx interrupts are decoded and routed.
> +
> +
> +Required properties for Interrupt controller child node:
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #address-cells: specifies the number of cells needed to encode an
> + address. The value must be 0.
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +
> +Example:
> +
> +pcie0: pcie@f8000000 {
> + compatible = "rockchip,rk3399-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
> + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
> + clock-names = "aclk", "aclk-perf",
> + "hclk", "pm";
> + bus-range = <0x0 0x1>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "sys", "legacy", "client";
> + assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
> + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
> + assigned-clock-rates = <100000000>;
> + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
> + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
> + num-lanes = <4>;
> + msi-map = <0x0 &its 0x0 0x1000>;
> + reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
> + reg-names = "axi-base", "apb-base";
> + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
> + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
> + reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreq>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie0_intc 0>,
> + <0 0 0 2 &pcie0_intc 1>,
> + <0 0 0 3 &pcie0_intc 2>,
> + <0 0 0 4 &pcie0_intc 3>;
> + pcie0_intc: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +};
> --
> 2.3.7
>
>
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| From | Shawn Lin <shawn.lin@rock-chips.com> |
|---|---|
| Date | 2016-08-20 04:40 +0200 |
| Subject | Re: [PATCH v10 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller |
| Message-ID | <s84mu-5vA-3@gated-at.bofh.it> |
| In reply to | #1466628 |
在 2016/8/20 3:33, Bjorn Helgaas 写道:
> On Fri, Aug 19, 2016 at 09:34:31AM +0800, Shawn Lin wrote:
>> This patch adds a binding that describes the Rockchip PCIe controller
>> found on Rockchip SoCs PCIe interface.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Reviewed-by: Brian Norris <briannorris@chromium.org>
>
> I applied both of these to pci/host-rockchip for v4.9, thanks, Shawn!
>
> I made a few whitespace and typo fixes in pcie-rockchip.c, so take a
> look and make sure I didn't break anything.
I checked your branch, host-rockchip, and it's okay.
Thanks, Bjorn!
>
>> ---
>>
>> Changes in v10:
>> - fix broken description of msi-map
>> - s/pcie/PCIe for description
>>
>> Changes in v9: None
>> Changes in v8:
>> - add Brian's review-tag
>>
>> Changes in v7:
>> - move optional properties ahead of interrupt subnode
>> - use 0-base index for INTx
>>
>> Changes in v6:
>> - add ack tag from Rob
>>
>> Changes in v5:
>> - fix wrong example reported by Marc
>> - add seperate section to describe the interrupt controller child
>> node
>>
>> Changes in v4:
>> - fix example of adding intermediate interrupt controller for pcie
>> legacy interrrupt
>>
>> Changes in v3:
>> - fix example dts code suggested by Rob and Marc
>> - remove driver's behaviour of regulator
>>
>> Changes in v2:
>> - fix lots clk/reset stuff suggested by Heiko
>> - remove msi-parent and add msi-map suggested by Marc
>> - drop phy related stuff
>> - some others minor fixes
>>
>> .../devicetree/bindings/pci/rockchip-pcie.txt | 106 +++++++++++++++++++++
>> 1 file changed, 106 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
>> new file mode 100644
>> index 0000000..ba67b39
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
>> @@ -0,0 +1,106 @@
>> +* Rockchip AXI PCIe Root Port Bridge DT description
>> +
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to <2>
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +- compatible: Should contain "rockchip,rk3399-pcie"
>> +- reg: Two register ranges as listed in the reg-names property
>> +- reg-names: Must include the following names
>> + - "axi-base"
>> + - "apb-base"
>> +- clocks: Must contain an entry for each entry in clock-names.
>> + See ../clocks/clock-bindings.txt for details.
>> +- clock-names: Must include the following entries:
>> + - "aclk"
>> + - "aclk-perf"
>> + - "hclk"
>> + - "pm"
>> +- msi-map: Maps a Requester ID to an MSI controller and associated
>> + msi-specifier data. See ./pci-msi.txt
>> +- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
>> +- phy-names: MUST be "pcie-phy".
>> +- interrupts: Three interrupt entries must be specified.
>> +- interrupt-names: Must include the following names
>> + - "sys"
>> + - "legacy"
>> + - "client"
>> +- resets: Must contain five entries for each entry in reset-names.
>> + See ../reset/reset.txt for details.
>> +- reset-names: Must include the following names
>> + - "core"
>> + - "mgmt"
>> + - "mgmt-sticky"
>> + - "pipe"
>> +- pinctrl-names : The pin control state names
>> +- pinctrl-0: The "default" pinctrl state
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +- interrupt-map-mask and interrupt-map: standard PCI properties
>> +
>> +Optional Property:
>> +- ep-gpios: contain the entry for pre-reset gpio
>> +- num-lanes: number of lanes to use
>> +- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
>> +- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
>> +- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
>> +
>> +*Interrupt controller child node*
>> +The core controller provides a single interrupt for legacy INTx. The PCIe node
>> +should contain an interrupt controller node as a target for the PCI
>> +'interrupt-map' property. This node represents the domain at which the four
>> +INTx interrupts are decoded and routed.
>> +
>> +
>> +Required properties for Interrupt controller child node:
>> +- interrupt-controller: identifies the node as an interrupt controller
>> +- #address-cells: specifies the number of cells needed to encode an
>> + address. The value must be 0.
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +
>> +Example:
>> +
>> +pcie0: pcie@f8000000 {
>> + compatible = "rockchip,rk3399-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
>> + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
>> + clock-names = "aclk", "aclk-perf",
>> + "hclk", "pm";
>> + bus-range = <0x0 0x1>;
>> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
>> + interrupt-names = "sys", "legacy", "client";
>> + assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
>> + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
>> + assigned-clock-rates = <100000000>;
>> + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
>> + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
>> + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
>> + num-lanes = <4>;
>> + msi-map = <0x0 &its 0x0 0x1000>;
>> + reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
>> + reg-names = "axi-base", "apb-base";
>> + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
>> + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
>> + reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
>> + phys = <&pcie_phy>;
>> + phy-names = "pcie-phy";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pcie_clkreq>;
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie0_intc 0>,
>> + <0 0 0 2 &pcie0_intc 1>,
>> + <0 0 0 3 &pcie0_intc 2>,
>> + <0 0 0 4 &pcie0_intc 3>;
>> + pcie0_intc: interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + };
>> +};
>> --
>> 2.3.7
>>
>>
>
>
>
--
Best Regards
Shawn Lin
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