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[PATCH v3 0/3] spi-nor: Add support for Intel SPI serial flash controller

Started byMika Westerberg <mika.westerberg@linux.intel.com>
First post2016-08-15 09:20 +0200
Last post2016-08-15 09:20 +0200
Articles 2 — 1 participant

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  [PATCH v3 0/3] spi-nor: Add support for Intel SPI serial flash controller Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-08-15 09:20 +0200
    [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-08-15 09:20 +0200

#1462597 — [PATCH v3 0/3] spi-nor: Add support for Intel SPI serial flash controller

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2016-08-15 09:20 +0200
Subject[PATCH v3 0/3] spi-nor: Add support for Intel SPI serial flash controller
Message-ID<s6klI-2uR-9@gated-at.bofh.it>
Hi,

This is third version of the series. Previous versions can be found:

  v2: http://lists.infradead.org/pipermail/linux-mtd/2016-June/068277.html
  v1: https://lkml.org/lkml/2016/6/14/269

This series adds support for the Intel SPI serial flash controller found on
many recent Intel CPUs including Baytrail and Braswell. This driver makes
it possible to access the BIOS and other platform data which is stored on
the SPI serial flash. It is also possible to upgrade the BIOS using this
driver if it has not been protected by special hardware bits.

The patch [1/3] includes documentation how to upgrade BIOS on MinnowBoard
MAX.

Since poking the SPI serial flash can brick the machine, this driver can
only be enabled when CONFIG_EXPERT=y and even then it will remain read-only
unless instructed othwerwise by module parameter.

Lee can you ACK/NACK the MFD parts so that we can merge the whole series
through the MTD tree?

Changes from v2:

  * Rebased on top of v4.8-rc2

  * Updated intel_spi_read/write() according spi-nor core changes which
    drops retlen parameter and returns number of bytes read/written.

Changes from v1:

[1/3] spi-nor: Add support for Intel SPI serial flash controller

  * Older hardware does not support 64k erase command so added erase_64k
    flag which is set only for Broxton (BXT).

  * Fix protection range offset for Broxton. Now there is ispi->pregs
    pointing to the start of the protection registers.

  * Change naming of constants from BCR_BYT -> BYT_BCR and so on.

[2/3] mfd: lpc_ich: Add support for SPI serial flash host controller

  * Drop lpc_ich_finalize_spi_cell() and initialize cell directly in
    lpc_ich_init_spi().

  * Use info->type in switch in lpc_ich_init_spi().

  * Add defines for magic numbers used in lpc_ich_init_spi().

  * Use PLATFORM_DEVID_NONE with mfd_add_devices().

[3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC

  * No changes

Mika Westerberg (3):
  spi-nor: Add support for Intel SPI serial flash controller
  mfd: lpc_ich: Add support for SPI serial flash host controller
  mfd: lpc_ich: Add support for Intel Apollo Lake SoC

 Documentation/mtd/intel-spi.txt          |  88 ++++
 drivers/mfd/lpc_ich.c                    | 131 ++++++
 drivers/mtd/spi-nor/Kconfig              |  20 +
 drivers/mtd/spi-nor/Makefile             |   2 +
 drivers/mtd/spi-nor/intel-spi-platform.c |  57 +++
 drivers/mtd/spi-nor/intel-spi.c          | 780 +++++++++++++++++++++++++++++++
 drivers/mtd/spi-nor/intel-spi.h          |  24 +
 include/linux/mfd/lpc_ich.h              |   3 +
 include/linux/platform_data/intel-spi.h  |  31 ++
 9 files changed, 1136 insertions(+)
 create mode 100644 Documentation/mtd/intel-spi.txt
 create mode 100644 drivers/mtd/spi-nor/intel-spi-platform.c
 create mode 100644 drivers/mtd/spi-nor/intel-spi.c
 create mode 100644 drivers/mtd/spi-nor/intel-spi.h
 create mode 100644 include/linux/platform_data/intel-spi.h

-- 
2.8.1

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#1462601 — [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2016-08-15 09:20 +0200
Subject[PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC
Message-ID<s6klI-2uR-37@gated-at.bofh.it>
In reply to#1462597
Intel Apollo Lake SoC exposes serial SPI flash through the LPC device. The
SPI flash host controller is not discoverable through PCI config cycles
because P2SB (function 0 of the device 13) is hidden by the BIOS. We unhide
the device briefly in order to read BAR 0 of the SPI host controller.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/mfd/lpc_ich.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index 56a0e98a5f89..b1013b3f4dee 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -56,6 +56,7 @@
  *	document number TBD : Wildcat Point-LP
  *	document number TBD : 9 Series
  *	document number TBD : Lewisburg
+ *	document number TBD : Apollo Lake SoC
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -92,6 +93,8 @@
 #define BCR			0xdc
 #define BCR_WPD			BIT(0)
 
+#define SPIBASE_APL_SZ		4096
+
 #define GPIOBASE_ICH0		0x58
 #define GPIOCTRL_ICH0		0x5C
 #define GPIOBASE_ICH6		0x48
@@ -239,6 +242,7 @@ enum lpc_chipsets {
 	LPC_BRASWELL,	/* Braswell SoC */
 	LPC_LEWISBURG,	/* Lewisburg */
 	LPC_9S,		/* 9 Series */
+	LPC_APL,	/* Apollo Lake SoC */
 };
 
 static struct lpc_ich_info lpc_chipset_info[] = {
@@ -559,6 +563,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 		.name = "9 Series",
 		.iTCO_version = 2,
 	},
+	[LPC_APL] = {
+		.name = "Apollo Lake SoC",
+		.spi_type = INTEL_SPI_BXT,
+	},
 };
 
 /*
@@ -707,6 +715,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
 	{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 	{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 	{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+	{ PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
 	{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 	{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 	{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
@@ -1122,6 +1131,36 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
 		}
 		break;
 
+	case INTEL_SPI_BXT: {
+		unsigned int p2sb = PCI_DEVFN(13, 0);
+		unsigned int spi = PCI_DEVFN(13, 2);
+		struct pci_bus *bus = dev->bus;
+
+		/*
+		 * The P2SB is hidden by BIOS and we need to unhide it in
+		 * order to read BAR of the SPI flash device. Once that is
+		 * done we hide it again.
+		 */
+		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
+		pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
+					  &spi_base);
+		if (spi_base != ~0) {
+			res->start = spi_base & 0xfffffff0;
+			res->end = res->start + SPIBASE_APL_SZ - 1;
+
+			pci_bus_read_config_dword(bus, spi, BCR, &bcr);
+			if (!(bcr & BCR_WPD)) {
+				bcr |= BCR_WPD;
+				pci_bus_write_config_dword(bus, spi, BCR, bcr);
+				pci_bus_read_config_dword(bus, spi, BCR, &bcr);
+			}
+			info->writeable = !!(bcr & BCR_WPD);
+		}
+
+		pci_bus_write_config_byte(dev->bus, p2sb, 0xe1, 0x1);
+		break;
+	}
+
 	default:
 		return -EINVAL;
 	}
-- 
2.8.1

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