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| Started by | Ben Hutchings <ben@decadent.org.uk> |
|---|---|
| First post | 2016-08-14 13:10 +0200 |
| Last post | 2016-08-14 13:10 +0200 |
| Articles | 1 — 1 participant |
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[PATCH 3.16 185/305] spi: sun4i: fix FIFO limit Ben Hutchings <ben@decadent.org.uk> - 2016-08-14 13:10 +0200
| From | Ben Hutchings <ben@decadent.org.uk> |
|---|---|
| Date | 2016-08-14 13:10 +0200 |
| Subject | [PATCH 3.16 185/305] spi: sun4i: fix FIFO limit |
| Message-ID | <s61sK-7d0-31@gated-at.bofh.it> |
3.16.37-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Michal Suchanek <hramrach@gmail.com> commit 6d9fe44bd73d567d04d3a68a2d2fa521ab9532f2 upstream. When testing SPI without DMA I noticed that filling the FIFO on the spi controller causes timeout. Always leave room for one byte in the FIFO. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Ben Hutchings <ben@decadent.org.uk> --- drivers/spi/spi-sun4i.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -176,7 +176,10 @@ static int sun4i_spi_transfer_one(struct /* We don't support transfer larger than the FIFO */ if (tfr->len > SUN4I_FIFO_DEPTH) - return -EINVAL; + return -EMSGSIZE; + + if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH) + return -EMSGSIZE; reinit_completion(&sspi->done); sspi->tx_buf = tfr->tx_buf; @@ -269,8 +272,12 @@ static int sun4i_spi_transfer_one(struct sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); - /* Fill the TX FIFO */ - sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH); + /* + * Fill the TX FIFO + * Filling the FIFO fully causes timeout for some reason + * at least on spi2 on A10s + */ + sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); /* Enable the interrupts */ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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