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| Started by | Randy Dunlap <rdunlap@infradead.org> |
|---|---|
| First post | 2016-08-08 06:10 +0200 |
| Last post | 2016-08-08 06:10 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCH] treewide: fix a bunch of typos (Documentation/) Randy Dunlap <rdunlap@infradead.org> - 2016-08-08 06:10 +0200
| From | Randy Dunlap <rdunlap@infradead.org> |
|---|---|
| Date | 2016-08-08 06:10 +0200 |
| Subject | Re: [PATCH] treewide: fix a bunch of typos (Documentation/) |
| Message-ID | <s3K30-4Ps-1@gated-at.bofh.it> |
On 08/07/16 06:56, Masahiro Yamada wrote: > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> for the Documentation/* files: All of the changes look correct, but a couple of them could use some more attention: --- a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt @@ -45,7 +45,7 @@ Required Properties: Optional Properties: - reg-names: In addition to the required properties, the following are optional - "efuse-address" - Contains efuse base address used to pick up ABB info. - - "ldo-address" - Contains address of ABB LDO overide register address. + - "ldo-address" - Contains address of ABB LDO override register address. Probably drop the last "address". --- a/Documentation/xtensa/atomctl.txt +++ b/Documentation/xtensa/atomctl.txt @@ -19,7 +19,7 @@ doing a Cached (WB) transaction and use the Memory RCW for un-cached operations. For systems without an coherent cache controller, non-MX, we always -use the memory controllers RCW, thought non-MX controlers likely +use the memory controllers RCW, thought non-MX controllers likely support the Internal Operation. I think s/thought/though/. -- ~Randy
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