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Groups > linux.kernel > #1452293 > unrolled thread

[PATCH v4 0/7] rk3399 support ddr frequency scaling

Started byLin Huang <hl@rock-chips.com>
First post2016-07-29 10:00 +0200
Last post2016-08-05 15:50 +0200
Articles 15 — 7 participants

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Contents

  [PATCH v4 0/7] rk3399 support ddr frequency scaling  Lin Huang <hl@rock-chips.com> - 2016-07-29 10:00 +0200
    [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Lin Huang <hl@rock-chips.com> - 2016-07-29 10:00 +0200
      Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-01 10:00 +0200
        Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-01 10:10 +0200
          Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi  controller hl <hl@rock-chips.com> - 2016-08-01 10:30 +0200
            Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-01 12:40 +0200
    [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll Lin Huang <hl@rock-chips.com> - 2016-07-29 10:00 +0200
      Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll Heiko Stuebner <heiko@sntech.de> - 2016-08-05 00:40 +0200
        Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when  register pll hl <huanglin821201@gmail.com> - 2016-08-05 11:00 +0200
          Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll Heiko Stübner <heiko@sntech.de> - 2016-08-05 11:00 +0200
    [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support Lin Huang <hl@rock-chips.com> - 2016-07-29 10:00 +0200
    Re: [PATCH v4 0/7] rk3399 support ddr frequency scaling hl <hl@rock-chips.com> - 2016-08-01 09:50 +0200
      Re: [PATCH v4 0/7] rk3399 support ddr frequency scaling Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-01 10:00 +0200
    Re: [PATCH v4 0/7] rk3399 support ddr frequency scaling Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-01 09:50 +0200
    Re: [PATCH v4 0/7] rk3399 support ddr frequency scaling Tomeu Vizoso <tomeu@tomeuvizoso.net> - 2016-08-05 15:50 +0200

#1452293 — [PATCH v4 0/7] rk3399 support ddr frequency scaling

FromLin Huang <hl@rock-chips.com>
Date2016-07-29 10:00 +0200
Subject[PATCH v4 0/7] rk3399 support ddr frequency scaling
Message-ID<s0aS5-1HF-3@gated-at.bofh.it>
rk3399 platform have dfi controller can monitor ddr load,
and dcf controller to handle ddr register so we can get the
right ddr frequency and make ddr controller happy work(which
will implement in bl31). So we do ddr frequency scaling with
following flow:

	     kernel                                bl31

	monitor ddr load
		|
		|
	get_target_rate
		|
		|           pass rate to bl31
	clk_set_rate(ddr) --------------------->run dcf flow
		|                                   |
		|                                   |
	wait dcf interrupt<-------------------trigger dcf interrupt  
		|
		|
	      return

Lin Huang (6):
  clk: rockchip: add new clock-type for the ddrclk
  clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
  clk: rockchip: rk3399: add ddrc clock support
  PM / devfreq: event: support rockchip dfi controller
  PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
  drm/rockchip: Add dmc notifier in vop driver


Heiko Stübner (1):
  clk: rockchip: add clock flag parameter when register pll

Lin Huang (6):
  clk: rockchip: add new clock-type for the ddrclk
  clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
  clk: rockchip: rk3399: add ddrc clock support
  PM / devfreq: event: support rockchip dfi controller
  PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
  drm/rockchip: Add dmc notifier in vop driver

 drivers/clk/rockchip/Makefile               |   1 +
 drivers/clk/rockchip/clk-ddr.c              | 146 +++++++++
 drivers/clk/rockchip/clk-pll.c              |   4 +-
 drivers/clk/rockchip/clk-rk3399.c           |  19 ++
 drivers/clk/rockchip/clk.c                  |  11 +-
 drivers/clk/rockchip/clk.h                  |  29 +-
 drivers/devfreq/Kconfig                     |   1 +
 drivers/devfreq/Makefile                    |   1 +
 drivers/devfreq/event/Kconfig               |   7 +
 drivers/devfreq/event/Makefile              |   1 +
 drivers/devfreq/event/rockchip-dfi.c        | 253 +++++++++++++++
 drivers/devfreq/rockchip/Kconfig            |   8 +
 drivers/devfreq/rockchip/Makefile           |   1 +
 drivers/devfreq/rockchip/rk3399_dmc.c       | 473 ++++++++++++++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 124 +++++++-
 include/dt-bindings/clock/rk3399-cru.h      |   1 +
 include/soc/rockchip/rockchip_sip.h         |  27 ++
 17 files changed, 1098 insertions(+), 9 deletions(-)
 create mode 100644 drivers/clk/rockchip/clk-ddr.c
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c
 create mode 100644 drivers/devfreq/rockchip/Kconfig
 create mode 100644 drivers/devfreq/rockchip/Makefile
 create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c
 create mode 100644 include/soc/rockchip/rockchip_sip.h

-- 
1.9.1

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#1452294 — [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller

FromLin Huang <hl@rock-chips.com>
Date2016-07-29 10:00 +0200
Subject[PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller
Message-ID<s0aS5-1HF-23@gated-at.bofh.it>
In reply to#1452293
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- use clk_disable_unprepare and clk_enable_prepare
- remove clk_enable_prepare in probe
- remove rockchip_dfi_remove function

Changes in v1:
- None

 drivers/devfreq/event/Kconfig        |   7 +
 drivers/devfreq/event/Makefile       |   1 +
 drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++
 3 files changed, 261 insertions(+)
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c

diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
index a11720a..ff9279f 100644
--- a/drivers/devfreq/event/Kconfig
+++ b/drivers/devfreq/event/Kconfig
@@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
 	  (Platform Performance Monitoring Unit) counters to estimate the
 	  utilization of each module.
 
+config DEVFREQ_EVENT_ROCKCHIP_DFI
+	tristate "ROCKCHIP DFI DEVFREQ event Driver"
+	depends on ARCH_ROCKCHIP
+	help
+	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
+	  (DDR Monitor Module) driver to count ddr load.
+
 endif # PM_DEVFREQ_EVENT
diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
index be146ea..e3f88fc 100644
--- a/drivers/devfreq/event/Makefile
+++ b/drivers/devfreq/event/Makefile
@@ -1,2 +1,3 @@
 # Exynos DEVFREQ Event Drivers
 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
+obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
new file mode 100644
index 0000000..96a0307
--- /dev/null
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Lin Huang <hl@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq-event.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/of.h>
+
+#define RK3399_DMC_NUM_CH	2
+
+/* DDRMON_CTRL */
+#define DDRMON_CTRL	0x04
+#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
+#define LPDDR4_EN	(0x10001 << 4)
+#define HARDWARE_EN	(0x10001 << 3)
+#define LPDDR3_EN	(0x10001 << 2)
+#define SOFTWARE_EN	(0x10001 << 1)
+#define TIME_CNT_EN	(0x10001 << 0)
+
+#define DDRMON_CH0_COUNT_NUM		0x28
+#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
+#define DDRMON_CH1_COUNT_NUM		0x3c
+#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+
+/* pmu grf */
+#define PMUGRF_OS_REG2	0x308
+#define DDRTYPE_SHIFT	13
+#define DDRTYPE_MASK	7
+
+enum {
+	DDR3 = 3,
+	LPDDR3 = 6,
+	LPDDR4 = 7,
+	UNUSED = 0xFF
+};
+
+struct dmc_usage {
+	u32 access;
+	u32 total;
+};
+
+struct rockchip_dfi {
+	struct devfreq_event_dev *edev;
+	struct devfreq_event_desc *desc;
+	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+	struct device *dev;
+	void __iomem *regs;
+	struct regmap *regmap_pmu;
+	struct clk *clk;
+};
+
+static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+	u32 val;
+	u32 ddr_type;
+
+	/* get ddr type */
+	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
+	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
+
+	/* clear DDRMON_CTRL setting */
+	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+
+	/* set ddr type to dfi */
+	if (ddr_type == LPDDR3)
+		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+	else if (ddr_type == LPDDR4)
+		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+
+	/* enable count, use software mode */
+	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+}
+
+static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+	u32 val;
+
+	val = readl_relaxed(dfi_regs + DDRMON_CTRL);
+	val &= ~SOFTWARE_EN;
+	writel_relaxed(val, dfi_regs + DDRMON_CTRL);
+}
+
+static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	u32 tmp, max = 0;
+	u32 i, busier_ch = 0;
+	void __iomem *dfi_regs = info->regs;
+
+	rockchip_dfi_stop_hardware_counter(edev);
+
+	/* Find out which channel is busier */
+	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+		info->ch_usage[i].access = readl_relaxed(dfi_regs +
+				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+		info->ch_usage[i].total = readl_relaxed(dfi_regs +
+				DDRMON_CH0_COUNT_NUM + i * 20);
+		tmp = info->ch_usage[i].access;
+		if (tmp > max) {
+			busier_ch = i;
+			max = tmp;
+		}
+	}
+	rockchip_dfi_start_hardware_counter(edev);
+
+	return busier_ch;
+}
+
+static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+	rockchip_dfi_stop_hardware_counter(edev);
+	clk_disable_unprepare(info->clk);
+
+	return 0;
+}
+
+static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int ret;
+
+	ret = clk_prepare_enable(info->clk);
+	if (ret) {
+		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+		return ret;
+	}
+
+	rockchip_dfi_start_hardware_counter(edev);
+	return 0;
+}
+
+static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
+{
+	return 0;
+}
+
+static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
+				  struct devfreq_event_data *edata)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int busier_ch;
+
+	busier_ch = rockchip_dfi_get_busier_ch(edev);
+
+	edata->load_count = info->ch_usage[busier_ch].access;
+	edata->total_count = info->ch_usage[busier_ch].total;
+
+	return 0;
+}
+
+static const struct devfreq_event_ops rockchip_dfi_ops = {
+	.disable = rockchip_dfi_disable,
+	.enable = rockchip_dfi_enable,
+	.get_event = rockchip_dfi_get_event,
+	.set_event = rockchip_dfi_set_event,
+};
+
+static const struct of_device_id rockchip_dfi_id_match[] = {
+	{ .compatible = "rockchip,rk3399-dfi" },
+	{ },
+};
+
+static int rockchip_dfi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rockchip_dfi *data;
+	struct resource *res;
+	struct devfreq_event_desc *desc;
+	struct device_node *np = pdev->dev.of_node, *node;
+
+	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(data->regs))
+		return PTR_ERR(data->regs);
+
+	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
+	if (IS_ERR(data->clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->clk);
+	};
+
+	/* try to find the optional reference to the pmu syscon */
+	node = of_parse_phandle(np, "rockchip,pmu", 0);
+	if (node) {
+		data->regmap_pmu = syscon_node_to_regmap(node);
+		if (IS_ERR(data->regmap_pmu))
+			return PTR_ERR(data->regmap_pmu);
+	}
+	data->dev = dev;
+
+	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+
+	desc->ops = &rockchip_dfi_ops;
+	desc->driver_data = data;
+	desc->name = np->name;
+	data->desc = desc;
+
+	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+	if (IS_ERR(data->edev)) {
+		dev_err(&pdev->dev,
+			"failed to add devfreq-event device\n");
+		return PTR_ERR(data->edev);
+	}
+
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static struct platform_driver rockchip_dfi_driver = {
+	.probe	= rockchip_dfi_probe,
+	.driver = {
+		.name	= "rockchip-dfi",
+		.of_match_table = rockchip_dfi_id_match,
+	},
+};
+module_platform_driver(rockchip_dfi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip dfi driver");
-- 
1.9.1

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#1453030 — Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller

FromChanwoo Choi <cw00.choi@samsung.com>
Date2016-08-01 10:00 +0200
SubjectRe: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller
Message-ID<s1giK-3pK-9@gated-at.bofh.it>
In reply to#1452294
Hi Lin,

Because you remove the 'RFC' prefix on patch title,
I think that you better to make the documentation as following: 
- Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt

Regards,
Chanwoo Choi

On 2016년 07월 29일 16:56, Lin Huang wrote:
> on rk3399 platform, there is dfi conroller can monitor
> ddr load, base on this result, we can do ddr freqency
> scaling.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> Changes in v4:
> - None
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - use clk_disable_unprepare and clk_enable_prepare
> - remove clk_enable_prepare in probe
> - remove rockchip_dfi_remove function
> 
> Changes in v1:
> - None
> 
>  drivers/devfreq/event/Kconfig        |   7 +
>  drivers/devfreq/event/Makefile       |   1 +
>  drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++
>  3 files changed, 261 insertions(+)
>  create mode 100644 drivers/devfreq/event/rockchip-dfi.c
> 
> diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
> index a11720a..ff9279f 100644
> --- a/drivers/devfreq/event/Kconfig
> +++ b/drivers/devfreq/event/Kconfig
> @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
>  	  (Platform Performance Monitoring Unit) counters to estimate the
>  	  utilization of each module.
>  
> +config DEVFREQ_EVENT_ROCKCHIP_DFI
> +	tristate "ROCKCHIP DFI DEVFREQ event Driver"
> +	depends on ARCH_ROCKCHIP
> +	help
> +	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
> +	  (DDR Monitor Module) driver to count ddr load.
> +
>  endif # PM_DEVFREQ_EVENT
> diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
> index be146ea..e3f88fc 100644
> --- a/drivers/devfreq/event/Makefile
> +++ b/drivers/devfreq/event/Makefile
> @@ -1,2 +1,3 @@
>  # Exynos DEVFREQ Event Drivers
>  obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
> +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> new file mode 100644
> index 0000000..96a0307
> --- /dev/null
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -0,0 +1,253 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
> + * Author: Lin Huang <hl@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/list.h>
> +#include <linux/of.h>
> +
> +#define RK3399_DMC_NUM_CH	2
> +
> +/* DDRMON_CTRL */
> +#define DDRMON_CTRL	0x04
> +#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
> +#define LPDDR4_EN	(0x10001 << 4)
> +#define HARDWARE_EN	(0x10001 << 3)
> +#define LPDDR3_EN	(0x10001 << 2)
> +#define SOFTWARE_EN	(0x10001 << 1)
> +#define TIME_CNT_EN	(0x10001 << 0)
> +
> +#define DDRMON_CH0_COUNT_NUM		0x28
> +#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
> +#define DDRMON_CH1_COUNT_NUM		0x3c
> +#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
> +
> +/* pmu grf */
> +#define PMUGRF_OS_REG2	0x308
> +#define DDRTYPE_SHIFT	13
> +#define DDRTYPE_MASK	7
> +
> +enum {
> +	DDR3 = 3,
> +	LPDDR3 = 6,
> +	LPDDR4 = 7,
> +	UNUSED = 0xFF
> +};
> +
> +struct dmc_usage {
> +	u32 access;
> +	u32 total;
> +};
> +
> +struct rockchip_dfi {
> +	struct devfreq_event_dev *edev;
> +	struct devfreq_event_desc *desc;
> +	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
> +	struct device *dev;
> +	void __iomem *regs;
> +	struct regmap *regmap_pmu;
> +	struct clk *clk;
> +};
> +
> +static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +	void __iomem *dfi_regs = info->regs;
> +	u32 val;
> +	u32 ddr_type;
> +
> +	/* get ddr type */
> +	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
> +	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
> +
> +	/* clear DDRMON_CTRL setting */
> +	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
> +
> +	/* set ddr type to dfi */
> +	if (ddr_type == LPDDR3)
> +		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> +	else if (ddr_type == LPDDR4)
> +		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
> +
> +	/* enable count, use software mode */
> +	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
> +}
> +
> +static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +	void __iomem *dfi_regs = info->regs;
> +	u32 val;
> +
> +	val = readl_relaxed(dfi_regs + DDRMON_CTRL);
> +	val &= ~SOFTWARE_EN;
> +	writel_relaxed(val, dfi_regs + DDRMON_CTRL);
> +}
> +
> +static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +	u32 tmp, max = 0;
> +	u32 i, busier_ch = 0;
> +	void __iomem *dfi_regs = info->regs;
> +
> +	rockchip_dfi_stop_hardware_counter(edev);
> +
> +	/* Find out which channel is busier */
> +	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> +		info->ch_usage[i].access = readl_relaxed(dfi_regs +
> +				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> +		info->ch_usage[i].total = readl_relaxed(dfi_regs +
> +				DDRMON_CH0_COUNT_NUM + i * 20);
> +		tmp = info->ch_usage[i].access;
> +		if (tmp > max) {
> +			busier_ch = i;
> +			max = tmp;
> +		}
> +	}
> +	rockchip_dfi_start_hardware_counter(edev);
> +
> +	return busier_ch;
> +}
> +
> +static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +
> +	rockchip_dfi_stop_hardware_counter(edev);
> +	clk_disable_unprepare(info->clk);
> +
> +	return 0;
> +}
> +
> +static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +	int ret;
> +
> +	ret = clk_prepare_enable(info->clk);
> +	if (ret) {
> +		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	rockchip_dfi_start_hardware_counter(edev);
> +	return 0;
> +}
> +
> +static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
> +{
> +	return 0;
> +}
> +
> +static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
> +				  struct devfreq_event_data *edata)
> +{
> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> +	int busier_ch;
> +
> +	busier_ch = rockchip_dfi_get_busier_ch(edev);
> +
> +	edata->load_count = info->ch_usage[busier_ch].access;
> +	edata->total_count = info->ch_usage[busier_ch].total;
> +
> +	return 0;
> +}
> +
> +static const struct devfreq_event_ops rockchip_dfi_ops = {
> +	.disable = rockchip_dfi_disable,
> +	.enable = rockchip_dfi_enable,
> +	.get_event = rockchip_dfi_get_event,
> +	.set_event = rockchip_dfi_set_event,
> +};
> +
> +static const struct of_device_id rockchip_dfi_id_match[] = {
> +	{ .compatible = "rockchip,rk3399-dfi" },
> +	{ },
> +};
> +
> +static int rockchip_dfi_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct rockchip_dfi *data;
> +	struct resource *res;
> +	struct devfreq_event_desc *desc;
> +	struct device_node *np = pdev->dev.of_node, *node;
> +
> +	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	data->regs = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(data->regs))
> +		return PTR_ERR(data->regs);
> +
> +	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
> +	if (IS_ERR(data->clk)) {
> +		dev_err(dev, "Cannot get the clk dmc_clk\n");
> +		return PTR_ERR(data->clk);
> +	};
> +
> +	/* try to find the optional reference to the pmu syscon */
> +	node = of_parse_phandle(np, "rockchip,pmu", 0);
> +	if (node) {
> +		data->regmap_pmu = syscon_node_to_regmap(node);
> +		if (IS_ERR(data->regmap_pmu))
> +			return PTR_ERR(data->regmap_pmu);
> +	}
> +	data->dev = dev;
> +
> +	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
> +	if (!desc)
> +		return -ENOMEM;
> +
> +	desc->ops = &rockchip_dfi_ops;
> +	desc->driver_data = data;
> +	desc->name = np->name;
> +	data->desc = desc;
> +
> +	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
> +	if (IS_ERR(data->edev)) {
> +		dev_err(&pdev->dev,
> +			"failed to add devfreq-event device\n");
> +		return PTR_ERR(data->edev);
> +	}
> +
> +	platform_set_drvdata(pdev, data);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver rockchip_dfi_driver = {
> +	.probe	= rockchip_dfi_probe,
> +	.driver = {
> +		.name	= "rockchip-dfi",
> +		.of_match_table = rockchip_dfi_id_match,
> +	},
> +};
> +module_platform_driver(rockchip_dfi_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip dfi driver");
>

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#1453033 — Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller

FromChanwoo Choi <cw00.choi@samsung.com>
Date2016-08-01 10:10 +0200
SubjectRe: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller
Message-ID<s1gsq-3Iu-19@gated-at.bofh.it>
In reply to#1453030
Hi Lin,

I add the one minor comment for full name of 'DRI'.

On 2016년 08월 01일 16:41, Chanwoo Choi wrote:
> Hi Lin,
> 
> Because you remove the 'RFC' prefix on patch title,
> I think that you better to make the documentation as following: 
> - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> 
> Regards,
> Chanwoo Choi
> 
> On 2016년 07월 29일 16:56, Lin Huang wrote:
>> on rk3399 platform, there is dfi conroller can monitor
>> ddr load, base on this result, we can do ddr freqency
>> scaling.
>>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>> Changes in v4:
>> - None
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - use clk_disable_unprepare and clk_enable_prepare
>> - remove clk_enable_prepare in probe
>> - remove rockchip_dfi_remove function
>>
>> Changes in v1:
>> - None
>>
>>  drivers/devfreq/event/Kconfig        |   7 +
>>  drivers/devfreq/event/Makefile       |   1 +
>>  drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++
>>  3 files changed, 261 insertions(+)
>>  create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>>
>> diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
>> index a11720a..ff9279f 100644
>> --- a/drivers/devfreq/event/Kconfig
>> +++ b/drivers/devfreq/event/Kconfig
>> @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
>>  	  (Platform Performance Monitoring Unit) counters to estimate the
>>  	  utilization of each module.
>>  
>> +config DEVFREQ_EVENT_ROCKCHIP_DFI
>> +	tristate "ROCKCHIP DFI DEVFREQ event Driver"
>> +	depends on ARCH_ROCKCHIP
>> +	help
>> +	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
>> +	  (DDR Monitor Module) driver to count ddr load.

The DFI is "DDR Monitor Module" full name? I need the correct abbreviation 
and full name.

>> +
>>  endif # PM_DEVFREQ_EVENT
>> diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
>> index be146ea..e3f88fc 100644
>> --- a/drivers/devfreq/event/Makefile
>> +++ b/drivers/devfreq/event/Makefile
>> @@ -1,2 +1,3 @@
>>  # Exynos DEVFREQ Event Drivers
>>  obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
>> +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
>> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
>> new file mode 100644
>> index 0000000..96a0307
>> --- /dev/null
>> +++ b/drivers/devfreq/event/rockchip-dfi.c
>> @@ -0,0 +1,253 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>> + * Author: Lin Huang <hl@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/devfreq-event.h>
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/slab.h>
>> +#include <linux/list.h>
>> +#include <linux/of.h>
>> +
>> +#define RK3399_DMC_NUM_CH	2
>> +
>> +/* DDRMON_CTRL */
>> +#define DDRMON_CTRL	0x04
>> +#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
>> +#define LPDDR4_EN	(0x10001 << 4)
>> +#define HARDWARE_EN	(0x10001 << 3)
>> +#define LPDDR3_EN	(0x10001 << 2)
>> +#define SOFTWARE_EN	(0x10001 << 1)
>> +#define TIME_CNT_EN	(0x10001 << 0)
>> +
>> +#define DDRMON_CH0_COUNT_NUM		0x28
>> +#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
>> +#define DDRMON_CH1_COUNT_NUM		0x3c
>> +#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
>> +
>> +/* pmu grf */
>> +#define PMUGRF_OS_REG2	0x308
>> +#define DDRTYPE_SHIFT	13
>> +#define DDRTYPE_MASK	7
>> +
>> +enum {
>> +	DDR3 = 3,
>> +	LPDDR3 = 6,
>> +	LPDDR4 = 7,
>> +	UNUSED = 0xFF
>> +};
>> +
>> +struct dmc_usage {
>> +	u32 access;
>> +	u32 total;
>> +};
>> +
>> +struct rockchip_dfi {
>> +	struct devfreq_event_dev *edev;
>> +	struct devfreq_event_desc *desc;
>> +	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
>> +	struct device *dev;
>> +	void __iomem *regs;
>> +	struct regmap *regmap_pmu;
>> +	struct clk *clk;
>> +};
>> +
>> +static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +	void __iomem *dfi_regs = info->regs;
>> +	u32 val;
>> +	u32 ddr_type;
>> +
>> +	/* get ddr type */
>> +	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
>> +	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
>> +
>> +	/* clear DDRMON_CTRL setting */
>> +	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>> +
>> +	/* set ddr type to dfi */
>> +	if (ddr_type == LPDDR3)
>> +		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
>> +	else if (ddr_type == LPDDR4)
>> +		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>> +
>> +	/* enable count, use software mode */
>> +	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
>> +}
>> +
>> +static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +	void __iomem *dfi_regs = info->regs;
>> +	u32 val;
>> +
>> +	val = readl_relaxed(dfi_regs + DDRMON_CTRL);
>> +	val &= ~SOFTWARE_EN;
>> +	writel_relaxed(val, dfi_regs + DDRMON_CTRL);
>> +}
>> +
>> +static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +	u32 tmp, max = 0;
>> +	u32 i, busier_ch = 0;
>> +	void __iomem *dfi_regs = info->regs;
>> +
>> +	rockchip_dfi_stop_hardware_counter(edev);
>> +
>> +	/* Find out which channel is busier */
>> +	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
>> +		info->ch_usage[i].access = readl_relaxed(dfi_regs +
>> +				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
>> +		info->ch_usage[i].total = readl_relaxed(dfi_regs +
>> +				DDRMON_CH0_COUNT_NUM + i * 20);
>> +		tmp = info->ch_usage[i].access;
>> +		if (tmp > max) {
>> +			busier_ch = i;
>> +			max = tmp;
>> +		}
>> +	}
>> +	rockchip_dfi_start_hardware_counter(edev);
>> +
>> +	return busier_ch;
>> +}
>> +
>> +static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +
>> +	rockchip_dfi_stop_hardware_counter(edev);
>> +	clk_disable_unprepare(info->clk);
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +	int ret;
>> +
>> +	ret = clk_prepare_enable(info->clk);
>> +	if (ret) {
>> +		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	rockchip_dfi_start_hardware_counter(edev);
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
>> +				  struct devfreq_event_data *edata)
>> +{
>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>> +	int busier_ch;
>> +
>> +	busier_ch = rockchip_dfi_get_busier_ch(edev);
>> +
>> +	edata->load_count = info->ch_usage[busier_ch].access;
>> +	edata->total_count = info->ch_usage[busier_ch].total;
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct devfreq_event_ops rockchip_dfi_ops = {
>> +	.disable = rockchip_dfi_disable,
>> +	.enable = rockchip_dfi_enable,
>> +	.get_event = rockchip_dfi_get_event,
>> +	.set_event = rockchip_dfi_set_event,
>> +};
>> +
>> +static const struct of_device_id rockchip_dfi_id_match[] = {
>> +	{ .compatible = "rockchip,rk3399-dfi" },
>> +	{ },
>> +};
>> +
>> +static int rockchip_dfi_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct rockchip_dfi *data;
>> +	struct resource *res;
>> +	struct devfreq_event_desc *desc;
>> +	struct device_node *np = pdev->dev.of_node, *node;
>> +
>> +	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
>> +	if (!data)
>> +		return -ENOMEM;
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	data->regs = devm_ioremap_resource(&pdev->dev, res);
>> +	if (IS_ERR(data->regs))
>> +		return PTR_ERR(data->regs);
>> +
>> +	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
>> +	if (IS_ERR(data->clk)) {
>> +		dev_err(dev, "Cannot get the clk dmc_clk\n");
>> +		return PTR_ERR(data->clk);
>> +	};
>> +
>> +	/* try to find the optional reference to the pmu syscon */
>> +	node = of_parse_phandle(np, "rockchip,pmu", 0);
>> +	if (node) {
>> +		data->regmap_pmu = syscon_node_to_regmap(node);
>> +		if (IS_ERR(data->regmap_pmu))
>> +			return PTR_ERR(data->regmap_pmu);
>> +	}
>> +	data->dev = dev;
>> +
>> +	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
>> +	if (!desc)
>> +		return -ENOMEM;
>> +
>> +	desc->ops = &rockchip_dfi_ops;
>> +	desc->driver_data = data;
>> +	desc->name = np->name;
>> +	data->desc = desc;
>> +
>> +	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
>> +	if (IS_ERR(data->edev)) {
>> +		dev_err(&pdev->dev,
>> +			"failed to add devfreq-event device\n");
>> +		return PTR_ERR(data->edev);
>> +	}
>> +
>> +	platform_set_drvdata(pdev, data);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver rockchip_dfi_driver = {
>> +	.probe	= rockchip_dfi_probe,
>> +	.driver = {
>> +		.name	= "rockchip-dfi",
>> +		.of_match_table = rockchip_dfi_id_match,
>> +	},
>> +};
>> +module_platform_driver(rockchip_dfi_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip dfi driver");

s/dfi -> DFI

Regards,
Chanwoo Choi

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#1453035 — Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller

Fromhl <hl@rock-chips.com>
Date2016-08-01 10:30 +0200
SubjectRe: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller
Message-ID<s1gLL-3Qt-5@gated-at.bofh.it>
In reply to#1453033
Hi Chanwoo Choi,

On 2016年08月01日 16:08, Chanwoo Choi wrote:
> Hi Lin,
>
> I add the one minor comment for full name of 'DRI'.
>
> On 2016년 08월 01일 16:41, Chanwoo Choi wrote:
>> Hi Lin,
>>
>> Because you remove the 'RFC' prefix on patch title,
>> I think that you better to make the documentation as following:
>> - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
>>
>> Regards,
>> Chanwoo Choi
>>
>> On 2016년 07월 29일 16:56, Lin Huang wrote:
>>> on rk3399 platform, there is dfi conroller can monitor
>>> ddr load, base on this result, we can do ddr freqency
>>> scaling.
>>>
>>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>>> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> ---
>>> Changes in v4:
>>> - None
>>>
>>> Changes in v3:
>>> - None
>>>
>>> Changes in v2:
>>> - use clk_disable_unprepare and clk_enable_prepare
>>> - remove clk_enable_prepare in probe
>>> - remove rockchip_dfi_remove function
>>>
>>> Changes in v1:
>>> - None
>>>
>>>   drivers/devfreq/event/Kconfig        |   7 +
>>>   drivers/devfreq/event/Makefile       |   1 +
>>>   drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++
>>>   3 files changed, 261 insertions(+)
>>>   create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>>>
>>> diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
>>> index a11720a..ff9279f 100644
>>> --- a/drivers/devfreq/event/Kconfig
>>> +++ b/drivers/devfreq/event/Kconfig
>>> @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
>>>   	  (Platform Performance Monitoring Unit) counters to estimate the
>>>   	  utilization of each module.
>>>   
>>> +config DEVFREQ_EVENT_ROCKCHIP_DFI
>>> +	tristate "ROCKCHIP DFI DEVFREQ event Driver"
>>> +	depends on ARCH_ROCKCHIP
>>> +	help
>>> +	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
>>> +	  (DDR Monitor Module) driver to count ddr load.
> The DFI is "DDR Monitor Module" full name? I need the correct abbreviation
> and full name.
We just call this module DFI in datasheet, and this module function is 
ddr monitor module,
yes, it is do not fit the full name, but i think it is better follow the 
datasheet name.
>
>>> +
>>>   endif # PM_DEVFREQ_EVENT
>>> diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
>>> index be146ea..e3f88fc 100644
>>> --- a/drivers/devfreq/event/Makefile
>>> +++ b/drivers/devfreq/event/Makefile
>>> @@ -1,2 +1,3 @@
>>>   # Exynos DEVFREQ Event Drivers
>>>   obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
>>> +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
>>> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
>>> new file mode 100644
>>> index 0000000..96a0307
>>> --- /dev/null
>>> +++ b/drivers/devfreq/event/rockchip-dfi.c
>>> @@ -0,0 +1,253 @@
>>> +/*
>>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>>> + * Author: Lin Huang <hl@rock-chips.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify it
>>> + * under the terms and conditions of the GNU General Public License,
>>> + * version 2, as published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope it will be useful, but WITHOUT
>>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>>> + * more details.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/devfreq-event.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/err.h>
>>> +#include <linux/init.h>
>>> +#include <linux/io.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/list.h>
>>> +#include <linux/of.h>
>>> +
>>> +#define RK3399_DMC_NUM_CH	2
>>> +
>>> +/* DDRMON_CTRL */
>>> +#define DDRMON_CTRL	0x04
>>> +#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
>>> +#define LPDDR4_EN	(0x10001 << 4)
>>> +#define HARDWARE_EN	(0x10001 << 3)
>>> +#define LPDDR3_EN	(0x10001 << 2)
>>> +#define SOFTWARE_EN	(0x10001 << 1)
>>> +#define TIME_CNT_EN	(0x10001 << 0)
>>> +
>>> +#define DDRMON_CH0_COUNT_NUM		0x28
>>> +#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
>>> +#define DDRMON_CH1_COUNT_NUM		0x3c
>>> +#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
>>> +
>>> +/* pmu grf */
>>> +#define PMUGRF_OS_REG2	0x308
>>> +#define DDRTYPE_SHIFT	13
>>> +#define DDRTYPE_MASK	7
>>> +
>>> +enum {
>>> +	DDR3 = 3,
>>> +	LPDDR3 = 6,
>>> +	LPDDR4 = 7,
>>> +	UNUSED = 0xFF
>>> +};
>>> +
>>> +struct dmc_usage {
>>> +	u32 access;
>>> +	u32 total;
>>> +};
>>> +
>>> +struct rockchip_dfi {
>>> +	struct devfreq_event_dev *edev;
>>> +	struct devfreq_event_desc *desc;
>>> +	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
>>> +	struct device *dev;
>>> +	void __iomem *regs;
>>> +	struct regmap *regmap_pmu;
>>> +	struct clk *clk;
>>> +};
>>> +
>>> +static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +	void __iomem *dfi_regs = info->regs;
>>> +	u32 val;
>>> +	u32 ddr_type;
>>> +
>>> +	/* get ddr type */
>>> +	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
>>> +	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
>>> +
>>> +	/* clear DDRMON_CTRL setting */
>>> +	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>>> +
>>> +	/* set ddr type to dfi */
>>> +	if (ddr_type == LPDDR3)
>>> +		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
>>> +	else if (ddr_type == LPDDR4)
>>> +		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>>> +
>>> +	/* enable count, use software mode */
>>> +	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
>>> +}
>>> +
>>> +static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +	void __iomem *dfi_regs = info->regs;
>>> +	u32 val;
>>> +
>>> +	val = readl_relaxed(dfi_regs + DDRMON_CTRL);
>>> +	val &= ~SOFTWARE_EN;
>>> +	writel_relaxed(val, dfi_regs + DDRMON_CTRL);
>>> +}
>>> +
>>> +static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +	u32 tmp, max = 0;
>>> +	u32 i, busier_ch = 0;
>>> +	void __iomem *dfi_regs = info->regs;
>>> +
>>> +	rockchip_dfi_stop_hardware_counter(edev);
>>> +
>>> +	/* Find out which channel is busier */
>>> +	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
>>> +		info->ch_usage[i].access = readl_relaxed(dfi_regs +
>>> +				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
>>> +		info->ch_usage[i].total = readl_relaxed(dfi_regs +
>>> +				DDRMON_CH0_COUNT_NUM + i * 20);
>>> +		tmp = info->ch_usage[i].access;
>>> +		if (tmp > max) {
>>> +			busier_ch = i;
>>> +			max = tmp;
>>> +		}
>>> +	}
>>> +	rockchip_dfi_start_hardware_counter(edev);
>>> +
>>> +	return busier_ch;
>>> +}
>>> +
>>> +static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +
>>> +	rockchip_dfi_stop_hardware_counter(edev);
>>> +	clk_disable_unprepare(info->clk);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +	int ret;
>>> +
>>> +	ret = clk_prepare_enable(info->clk);
>>> +	if (ret) {
>>> +		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
>>> +		return ret;
>>> +	}
>>> +
>>> +	rockchip_dfi_start_hardware_counter(edev);
>>> +	return 0;
>>> +}
>>> +
>>> +static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
>>> +{
>>> +	return 0;
>>> +}
>>> +
>>> +static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
>>> +				  struct devfreq_event_data *edata)
>>> +{
>>> +	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
>>> +	int busier_ch;
>>> +
>>> +	busier_ch = rockchip_dfi_get_busier_ch(edev);
>>> +
>>> +	edata->load_count = info->ch_usage[busier_ch].access;
>>> +	edata->total_count = info->ch_usage[busier_ch].total;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static const struct devfreq_event_ops rockchip_dfi_ops = {
>>> +	.disable = rockchip_dfi_disable,
>>> +	.enable = rockchip_dfi_enable,
>>> +	.get_event = rockchip_dfi_get_event,
>>> +	.set_event = rockchip_dfi_set_event,
>>> +};
>>> +
>>> +static const struct of_device_id rockchip_dfi_id_match[] = {
>>> +	{ .compatible = "rockchip,rk3399-dfi" },
>>> +	{ },
>>> +};
>>> +
>>> +static int rockchip_dfi_probe(struct platform_device *pdev)
>>> +{
>>> +	struct device *dev = &pdev->dev;
>>> +	struct rockchip_dfi *data;
>>> +	struct resource *res;
>>> +	struct devfreq_event_desc *desc;
>>> +	struct device_node *np = pdev->dev.of_node, *node;
>>> +
>>> +	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
>>> +	if (!data)
>>> +		return -ENOMEM;
>>> +
>>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +	data->regs = devm_ioremap_resource(&pdev->dev, res);
>>> +	if (IS_ERR(data->regs))
>>> +		return PTR_ERR(data->regs);
>>> +
>>> +	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
>>> +	if (IS_ERR(data->clk)) {
>>> +		dev_err(dev, "Cannot get the clk dmc_clk\n");
>>> +		return PTR_ERR(data->clk);
>>> +	};
>>> +
>>> +	/* try to find the optional reference to the pmu syscon */
>>> +	node = of_parse_phandle(np, "rockchip,pmu", 0);
>>> +	if (node) {
>>> +		data->regmap_pmu = syscon_node_to_regmap(node);
>>> +		if (IS_ERR(data->regmap_pmu))
>>> +			return PTR_ERR(data->regmap_pmu);
>>> +	}
>>> +	data->dev = dev;
>>> +
>>> +	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
>>> +	if (!desc)
>>> +		return -ENOMEM;
>>> +
>>> +	desc->ops = &rockchip_dfi_ops;
>>> +	desc->driver_data = data;
>>> +	desc->name = np->name;
>>> +	data->desc = desc;
>>> +
>>> +	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
>>> +	if (IS_ERR(data->edev)) {
>>> +		dev_err(&pdev->dev,
>>> +			"failed to add devfreq-event device\n");
>>> +		return PTR_ERR(data->edev);
>>> +	}
>>> +
>>> +	platform_set_drvdata(pdev, data);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static struct platform_driver rockchip_dfi_driver = {
>>> +	.probe	= rockchip_dfi_probe,
>>> +	.driver = {
>>> +		.name	= "rockchip-dfi",
>>> +		.of_match_table = rockchip_dfi_id_match,
>>> +	},
>>> +};
>>> +module_platform_driver(rockchip_dfi_driver);
>>> +
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
>>> +MODULE_DESCRIPTION("Rockchip dfi driver");
> s/dfi -> DFI
>
> Regards,
> Chanwoo Choi
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
Lin Huang

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#1453123 — Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller

FromChanwoo Choi <cw00.choi@samsung.com>
Date2016-08-01 12:40 +0200
SubjectRe: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller
Message-ID<s1iNA-56O-13@gated-at.bofh.it>
In reply to#1453035
Hi Lin,

On 2016년 08월 01일 17:27, hl wrote:
> Hi Chanwoo Choi,
> 
> On 2016年08月01日 16:08, Chanwoo Choi wrote:
>> Hi Lin,
>>
>> I add the one minor comment for full name of 'DRI'.
>>
>> On 2016년 08월 01일 16:41, Chanwoo Choi wrote:
>>> Hi Lin,
>>>
>>> Because you remove the 'RFC' prefix on patch title,
>>> I think that you better to make the documentation as following:
>>> - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
>>>
>>> Regards,
>>> Chanwoo Choi
>>>
>>> On 2016년 07월 29일 16:56, Lin Huang wrote:
>>>> on rk3399 platform, there is dfi conroller can monitor
>>>> ddr load, base on this result, we can do ddr freqency
>>>> scaling.
>>>>
>>>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>>>> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>> Changes in v4:
>>>> - None
>>>>
>>>> Changes in v3:
>>>> - None
>>>>
>>>> Changes in v2:
>>>> - use clk_disable_unprepare and clk_enable_prepare
>>>> - remove clk_enable_prepare in probe
>>>> - remove rockchip_dfi_remove function
>>>>
>>>> Changes in v1:
>>>> - None
>>>>
>>>>   drivers/devfreq/event/Kconfig        |   7 +
>>>>   drivers/devfreq/event/Makefile       |   1 +
>>>>   drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++
>>>>   3 files changed, 261 insertions(+)
>>>>   create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>>>>
>>>> diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
>>>> index a11720a..ff9279f 100644
>>>> --- a/drivers/devfreq/event/Kconfig
>>>> +++ b/drivers/devfreq/event/Kconfig
>>>> @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
>>>>         (Platform Performance Monitoring Unit) counters to estimate the
>>>>         utilization of each module.
>>>>   +config DEVFREQ_EVENT_ROCKCHIP_DFI
>>>> +    tristate "ROCKCHIP DFI DEVFREQ event Driver"
>>>> +    depends on ARCH_ROCKCHIP
>>>> +    help
>>>> +      This add the devfreq-event driver for Rockchip SoC. It provides DFI
>>>> +      (DDR Monitor Module) driver to count ddr load.
>> The DFI is "DDR Monitor Module" full name? I need the correct abbreviation
>> and full name.
> We just call this module DFI in datasheet, and this module function is ddr monitor module,
> yes, it is do not fit the full name, but i think it is better follow the datasheet name.

Are there any full name of DFI? If the people who don't know the detailed history about
this workd (DFI), it causes the confusion and they don't understand it.

I think that if you want to use the DFI work, you need to add the more detailed description
why DFI word is used.

>>
>>>> +
>>>>   endif # PM_DEVFREQ_EVENT
>>>> diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
>>>> index be146ea..e3f88fc 100644
>>>> --- a/drivers/devfreq/event/Makefile
>>>> +++ b/drivers/devfreq/event/Makefile
>>>> @@ -1,2 +1,3 @@
>>>>   # Exynos DEVFREQ Event Drivers
>>>>   obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
>>>> +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
>>>> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
>>>> new file mode 100644
>>>> index 0000000..96a0307
>>>> --- /dev/null
>>>> +++ b/drivers/devfreq/event/rockchip-dfi.c
>>>> @@ -0,0 +1,253 @@
>>>> +/*
>>>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>>>> + * Author: Lin Huang <hl@rock-chips.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify it
>>>> + * under the terms and conditions of the GNU General Public License,
>>>> + * version 2, as published by the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope it will be useful, but WITHOUT
>>>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>>>> + * more details.
>>>> + */
>>>> +
>>>> +#include <linux/clk.h>
>>>> +#include <linux/devfreq-event.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/mfd/syscon.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/regmap.h>
>>>> +#include <linux/slab.h>
>>>> +#include <linux/list.h>
>>>> +#include <linux/of.h>
>>>> +
>>>> +#define RK3399_DMC_NUM_CH    2
>>>> +
>>>> +/* DDRMON_CTRL */
>>>> +#define DDRMON_CTRL    0x04
>>>> +#define CLR_DDRMON_CTRL    (0x1f0000 << 0)
>>>> +#define LPDDR4_EN    (0x10001 << 4)
>>>> +#define HARDWARE_EN    (0x10001 << 3)
>>>> +#define LPDDR3_EN    (0x10001 << 2)
>>>> +#define SOFTWARE_EN    (0x10001 << 1)
>>>> +#define TIME_CNT_EN    (0x10001 << 0)

[snip]

>>>> +};
>>>> +module_platform_driver(rockchip_dfi_driver);
>>>> +
>>>> +MODULE_LICENSE("GPL v2");
>>>> +MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
>>>> +MODULE_DESCRIPTION("Rockchip dfi driver");
>> s/dfi -> DFI

You should use the capital letter.

Regards,
Chanwoo Choi

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#1452297 — [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll

FromLin Huang <hl@rock-chips.com>
Date2016-07-29 10:00 +0200
Subject[PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll
Message-ID<s0aS6-1HF-35@gated-at.bofh.it>
In reply to#1452293
From: Heiko Stübner <heiko@sntech.de>

add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- None

Changes in v1:
- None

 drivers/clk/rockchip/clk-pll.c | 4 ++--
 drivers/clk/rockchip/clk.c     | 2 +-
 drivers/clk/rockchip/clk.h     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 8ac73bc..d824c36 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -864,7 +864,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 		u8 num_parents, int con_offset, int grf_lock_offset,
 		int lock_shift, int mode_offset, int mode_shift,
 		struct rockchip_pll_rate_table *rate_table,
-		u8 clk_pll_flags)
+		unsigned long flags, u8 clk_pll_flags)
 {
 	const char *pll_parents[3];
 	struct clk_init_data init;
@@ -919,7 +919,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	init.name = pll_name;
 
 	/* keep all plls untouched for now */
-	init.flags = CLK_IGNORE_UNUSED;
+	init.flags = flags | CLK_IGNORE_UNUSED;
 
 	init.parent_names = &parent_names[0];
 	init.num_parents = 1;
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index f0a8be1..9a046f1 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -390,7 +390,7 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 				list->con_offset, grf_lock_offset,
 				list->lock_shift, list->mode_offset,
 				list->mode_shift, list->rate_table,
-				list->pll_flags);
+				list->flags, list->pll_flags);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 				list->name);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 1abb7d0..bac775d 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -238,7 +238,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 		u8 num_parents, int con_offset, int grf_lock_offset,
 		int lock_shift, int mode_offset, int mode_shift,
 		struct rockchip_pll_rate_table *rate_table,
-		u8 clk_pll_flags);
+		unsigned long flags, u8 clk_pll_flags);
 
 struct rockchip_cpuclk_clksel {
 	int reg;
-- 
1.9.1

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#1456789 — Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll

FromHeiko Stuebner <heiko@sntech.de>
Date2016-08-05 00:40 +0200
SubjectRe: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll
Message-ID<s2zsZ-7Bf-13@gated-at.bofh.it>
In reply to#1452297
Am Freitag, 29. Juli 2016, 15:56:55 schrieb Lin Huang:
> From: Heiko Stübner <heiko@sntech.de>
> 
> add clock flag parameter so we can pass specific clock flag
> (like CLK_GET_RATE_NOCACHE etc..)to pll driver.
> 
> Signed-off-by: Heiko Stübner <heiko@sntech.de>
> Signed-off-by: Lin Huang <hl@rock-chips.com>

applied to my clock branch for 4.9 after some minor edits on the commit 
message.


Thanks
Heiko

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#1456954 — Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll

Fromhl <huanglin821201@gmail.com>
Date2016-08-05 11:00 +0200
SubjectRe: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll
Message-ID<s2J8Z-5cv-1@gated-at.bofh.it>
In reply to#1456789
Hi Heiko,

On 2016年08月05日 06:37, Heiko Stuebner wrote:
> Am Freitag, 29. Juli 2016, 15:56:55 schrieb Lin Huang:
>> From: Heiko Stübner <heiko@sntech.de>
>>
>> add clock flag parameter so we can pass specific clock flag
>> (like CLK_GET_RATE_NOCACHE etc..)to pll driver.
>>
>> Signed-off-by: Heiko Stübner <heiko@sntech.de>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
> applied to my clock branch for 4.9 after some minor edits on the commit
> message.
  I can not found your clock branch for 4.9, can you share me the patch 
ID, i want
cherry-pick it to my downstream branch.
>
> Thanks
> Heiko
>
>

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#1456956 — Re: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll

FromHeiko Stübner <heiko@sntech.de>
Date2016-08-05 11:00 +0200
SubjectRe: [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll
Message-ID<s2J90-5cv-9@gated-at.bofh.it>
In reply to#1456954
Hi Lin,

Am Freitag, 5. August 2016, 16:50:49 schrieb hl:
> On 2016年08月05日 06:37, Heiko Stuebner wrote:
> > Am Freitag, 29. Juli 2016, 15:56:55 schrieb Lin Huang:
> >> From: Heiko Stübner <heiko@sntech.de>
> >> 
> >> add clock flag parameter so we can pass specific clock flag
> >> (like CLK_GET_RATE_NOCACHE etc..)to pll driver.
> >> 
> >> Signed-off-by: Heiko Stübner <heiko@sntech.de>
> >> Signed-off-by: Lin Huang <hl@rock-chips.com>
> > 
> > applied to my clock branch for 4.9 after some minor edits on the commit
> > message.
> 
>   I can not found your clock branch for 4.9, can you share me the patch
> ID, i want
> cherry-pick it to my downstream branch.

sorry forgot to push yesterday evening. The patch is at [0].

Please keep in mind, that I'll rebase that branch onto 4.8-rc1 once it 
gets released on sunday. So the commit id is volatile till then.
[Same is true for all my 4.9 branch of course, I just pick patches already
to reduce the number of patches in my inbox :-) ]


Heiko

[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.9-clk/next&id=24bdd1a5a2cc706b8c4820a1976dd4eed56716e4

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#1452300 — [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support

FromLin Huang <hl@rock-chips.com>
Date2016-07-29 10:00 +0200
Subject[PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support
Message-ID<s0aS6-1HF-41@gated-at.bofh.it>
In reply to#1452293
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.

Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list

Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
- move clk_ddrc and clk_ddrc_dpll_src to critical

 drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index d4a1cf0..b7b42d9 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -118,6 +118,10 @@ PNAME(mux_armclkb_p)				= { "clk_core_b_lpll_src",
 						    "clk_core_b_bpll_src",
 						    "clk_core_b_dpll_src",
 						    "clk_core_b_gpll_src" };
+PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
+						    "clk_ddrc_bpll_src",
+						    "clk_ddrc_dpll_src",
+						    "clk_ddrc_gpll_src" };
 PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
 						    "gpll_aclk_cci_src",
 						    "npll_aclk_cci_src",
@@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
 			RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
 			RK3368_CLKGATE_CON(13), 11, GFLAGS),
+
+	/* ddrc */
+	GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
+	     0, GFLAGS),
+	GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
+	     1, GFLAGS),
+	GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
+	     2, GFLAGS),
+	GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
+	     3, GFLAGS),
+	COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, 0,
+		       RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS),
 };
 
 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
@@ -1487,6 +1503,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = {
 	"gpll_hclk_perilp1_src",
 	"gpll_aclk_perilp0_src",
 	"gpll_aclk_perihp_src",
+
+	/* ddrc */
+	"clk_ddrc"
 };
 
 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
-- 
1.9.1

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#1453021

Fromhl <hl@rock-chips.com>
Date2016-08-01 09:50 +0200
Message-ID<s1g94-3mB-17@gated-at.bofh.it>
In reply to#1452293
Hi Chanwoo Choi,

     Ah, i am base on 
https://chromium.googlesource.com/chromiumos/third_party/kernel/v4.4,
and forget to rebase on 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git, i 
will fix it in next version.
I am sorry about that. And can you help to review the devfreq patch 
first, if something need to update,
i will do it together. Thanks.

On 2016年08月01日 15:39, Chanwoo Choi wrote:
> Hi Lin,
>
> On 2016년 07월 29일 16:56, Lin Huang wrote:
>> rk3399 platform have dfi controller can monitor ddr load,
>> and dcf controller to handle ddr register so we can get the
>> right ddr frequency and make ddr controller happy work(which
>> will implement in bl31). So we do ddr frequency scaling with
>> following flow:
>>
>> 	     kernel                                bl31
>>
>> 	monitor ddr load
>> 		|
>> 		|
>> 	get_target_rate
>> 		|
>> 		|           pass rate to bl31
>> 	clk_set_rate(ddr) --------------------->run dcf flow
>> 		|                                   |
>> 		|                                   |
>> 	wait dcf interrupt<-------------------trigger dcf interrupt
>> 		|
>> 		|
>> 	      return
>>
>> Lin Huang (6):
>>    clk: rockchip: add new clock-type for the ddrclk
>>    clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>>    clk: rockchip: rk3399: add ddrc clock support
>>    PM / devfreq: event: support rockchip dfi controller
>>    PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>>    drm/rockchip: Add dmc notifier in vop driver
>>
>>
>> Heiko Stübner (1):
>>    clk: rockchip: add clock flag parameter when register pll
>>
>> Lin Huang (6):
>>    clk: rockchip: add new clock-type for the ddrclk
>>    clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>>    clk: rockchip: rk3399: add ddrc clock support
>>    PM / devfreq: event: support rockchip dfi controller
>>    PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>>    drm/rockchip: Add dmc notifier in vop driver
> The cover-letter includes the duplicate list of patches.
>
> Also, I want to test the build test. but, When I apply these patches,
> merge conflict happen. Could you give the information about base git repository?
>
> Regards,
> Chanwoo Choi
>
>
>>   drivers/clk/rockchip/Makefile               |   1 +
>>   drivers/clk/rockchip/clk-ddr.c              | 146 +++++++++
>>   drivers/clk/rockchip/clk-pll.c              |   4 +-
>>   drivers/clk/rockchip/clk-rk3399.c           |  19 ++
>>   drivers/clk/rockchip/clk.c                  |  11 +-
>>   drivers/clk/rockchip/clk.h                  |  29 +-
>>   drivers/devfreq/Kconfig                     |   1 +
>>   drivers/devfreq/Makefile                    |   1 +
>>   drivers/devfreq/event/Kconfig               |   7 +
>>   drivers/devfreq/event/Makefile              |   1 +
>>   drivers/devfreq/event/rockchip-dfi.c        | 253 +++++++++++++++
>>   drivers/devfreq/rockchip/Kconfig            |   8 +
>>   drivers/devfreq/rockchip/Makefile           |   1 +
>>   drivers/devfreq/rockchip/rk3399_dmc.c       | 473 ++++++++++++++++++++++++++++
>>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 124 +++++++-
>>   include/dt-bindings/clock/rk3399-cru.h      |   1 +
>>   include/soc/rockchip/rockchip_sip.h         |  27 ++
>>   17 files changed, 1098 insertions(+), 9 deletions(-)
>>   create mode 100644 drivers/clk/rockchip/clk-ddr.c
>>   create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>>   create mode 100644 drivers/devfreq/rockchip/Kconfig
>>   create mode 100644 drivers/devfreq/rockchip/Makefile
>>   create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c
>>   create mode 100644 include/soc/rockchip/rockchip_sip.h
>>
>
>
>

-- 
Lin Huang

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#1453027

FromChanwoo Choi <cw00.choi@samsung.com>
Date2016-08-01 10:00 +0200
Message-ID<s1giJ-3pK-1@gated-at.bofh.it>
In reply to#1453021
Hi Lin,

On 2016년 08월 01일 16:46, hl wrote:
> Hi Chanwoo Choi,
> 
>     Ah, i am base on https://chromium.googlesource.com/chromiumos/third_party/kernel/v4.4,
> and forget to rebase on https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git, i will fix it in next version.
> I am sorry about that. And can you help to review the devfreq patch first, if something need to update,
> i will do it together. Thanks.

Sure. I'm now reviewing the devfreq patches.

Regards,
Chanwoo Choi

> 
> On 2016年08月01日 15:39, Chanwoo Choi wrote:
>> Hi Lin,
>>
>> On 2016년 07월 29일 16:56, Lin Huang wrote:
>>> rk3399 platform have dfi controller can monitor ddr load,
>>> and dcf controller to handle ddr register so we can get the
>>> right ddr frequency and make ddr controller happy work(which
>>> will implement in bl31). So we do ddr frequency scaling with
>>> following flow:
>>>
>>>          kernel                                bl31
>>>
>>>     monitor ddr load
>>>         |
>>>         |
>>>     get_target_rate
>>>         |
>>>         |           pass rate to bl31
>>>     clk_set_rate(ddr) --------------------->run dcf flow
>>>         |                                   |
>>>         |                                   |
>>>     wait dcf interrupt<-------------------trigger dcf interrupt
>>>         |
>>>         |
>>>           return
>>>
>>> Lin Huang (6):
>>>    clk: rockchip: add new clock-type for the ddrclk
>>>    clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>>>    clk: rockchip: rk3399: add ddrc clock support
>>>    PM / devfreq: event: support rockchip dfi controller
>>>    PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>>>    drm/rockchip: Add dmc notifier in vop driver
>>>
>>>
>>> Heiko Stübner (1):
>>>    clk: rockchip: add clock flag parameter when register pll
>>>
>>> Lin Huang (6):
>>>    clk: rockchip: add new clock-type for the ddrclk
>>>    clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>>>    clk: rockchip: rk3399: add ddrc clock support
>>>    PM / devfreq: event: support rockchip dfi controller
>>>    PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>>>    drm/rockchip: Add dmc notifier in vop driver
>> The cover-letter includes the duplicate list of patches.
>>
>> Also, I want to test the build test. but, When I apply these patches,
>> merge conflict happen. Could you give the information about base git repository?
>>
>> Regards,
>> Chanwoo Choi
>>
>>
>>>   drivers/clk/rockchip/Makefile               |   1 +
>>>   drivers/clk/rockchip/clk-ddr.c              | 146 +++++++++
>>>   drivers/clk/rockchip/clk-pll.c              |   4 +-
>>>   drivers/clk/rockchip/clk-rk3399.c           |  19 ++
>>>   drivers/clk/rockchip/clk.c                  |  11 +-
>>>   drivers/clk/rockchip/clk.h                  |  29 +-
>>>   drivers/devfreq/Kconfig                     |   1 +
>>>   drivers/devfreq/Makefile                    |   1 +
>>>   drivers/devfreq/event/Kconfig               |   7 +
>>>   drivers/devfreq/event/Makefile              |   1 +
>>>   drivers/devfreq/event/rockchip-dfi.c        | 253 +++++++++++++++
>>>   drivers/devfreq/rockchip/Kconfig            |   8 +
>>>   drivers/devfreq/rockchip/Makefile           |   1 +
>>>   drivers/devfreq/rockchip/rk3399_dmc.c       | 473 ++++++++++++++++++++++++++++
>>>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 124 +++++++-
>>>   include/dt-bindings/clock/rk3399-cru.h      |   1 +
>>>   include/soc/rockchip/rockchip_sip.h         |  27 ++
>>>   17 files changed, 1098 insertions(+), 9 deletions(-)
>>>   create mode 100644 drivers/clk/rockchip/clk-ddr.c
>>>   create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>>>   create mode 100644 drivers/devfreq/rockchip/Kconfig
>>>   create mode 100644 drivers/devfreq/rockchip/Makefile
>>>   create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c
>>>   create mode 100644 include/soc/rockchip/rockchip_sip.h
>>>
>>
>>
>>
>

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#1453026

FromChanwoo Choi <cw00.choi@samsung.com>
Date2016-08-01 09:50 +0200
Message-ID<s1g94-3mB-21@gated-at.bofh.it>
In reply to#1452293
Hi Lin,

On 2016년 07월 29일 16:56, Lin Huang wrote:
> rk3399 platform have dfi controller can monitor ddr load,
> and dcf controller to handle ddr register so we can get the
> right ddr frequency and make ddr controller happy work(which
> will implement in bl31). So we do ddr frequency scaling with
> following flow:
> 
> 	     kernel                                bl31
> 
> 	monitor ddr load
> 		|
> 		|
> 	get_target_rate
> 		|
> 		|           pass rate to bl31
> 	clk_set_rate(ddr) --------------------->run dcf flow
> 		|                                   |
> 		|                                   |
> 	wait dcf interrupt<-------------------trigger dcf interrupt  
> 		|
> 		|
> 	      return
> 
> Lin Huang (6):
>   clk: rockchip: add new clock-type for the ddrclk
>   clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>   clk: rockchip: rk3399: add ddrc clock support
>   PM / devfreq: event: support rockchip dfi controller
>   PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>   drm/rockchip: Add dmc notifier in vop driver
> 
> 
> Heiko Stübner (1):
>   clk: rockchip: add clock flag parameter when register pll
> 
> Lin Huang (6):
>   clk: rockchip: add new clock-type for the ddrclk
>   clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>   clk: rockchip: rk3399: add ddrc clock support
>   PM / devfreq: event: support rockchip dfi controller
>   PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>   drm/rockchip: Add dmc notifier in vop driver

The cover-letter includes the duplicate list of patches.

Also, I want to test the build test. but, When I apply these patches,
merge conflict happen. Could you give the information about base git repository?

Regards,
Chanwoo Choi


>  drivers/clk/rockchip/Makefile               |   1 +
>  drivers/clk/rockchip/clk-ddr.c              | 146 +++++++++
>  drivers/clk/rockchip/clk-pll.c              |   4 +-
>  drivers/clk/rockchip/clk-rk3399.c           |  19 ++
>  drivers/clk/rockchip/clk.c                  |  11 +-
>  drivers/clk/rockchip/clk.h                  |  29 +-
>  drivers/devfreq/Kconfig                     |   1 +
>  drivers/devfreq/Makefile                    |   1 +
>  drivers/devfreq/event/Kconfig               |   7 +
>  drivers/devfreq/event/Makefile              |   1 +
>  drivers/devfreq/event/rockchip-dfi.c        | 253 +++++++++++++++
>  drivers/devfreq/rockchip/Kconfig            |   8 +
>  drivers/devfreq/rockchip/Makefile           |   1 +
>  drivers/devfreq/rockchip/rk3399_dmc.c       | 473 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 124 +++++++-
>  include/dt-bindings/clock/rk3399-cru.h      |   1 +
>  include/soc/rockchip/rockchip_sip.h         |  27 ++
>  17 files changed, 1098 insertions(+), 9 deletions(-)
>  create mode 100644 drivers/clk/rockchip/clk-ddr.c
>  create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>  create mode 100644 drivers/devfreq/rockchip/Kconfig
>  create mode 100644 drivers/devfreq/rockchip/Makefile
>  create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c
>  create mode 100644 include/soc/rockchip/rockchip_sip.h
>

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#1457112

FromTomeu Vizoso <tomeu@tomeuvizoso.net>
Date2016-08-05 15:50 +0200
Message-ID<s2NFE-8dj-33@gated-at.bofh.it>
In reply to#1452293
On 29 July 2016 at 09:56, Lin Huang <hl@rock-chips.com> wrote:
> rk3399 platform have dfi controller can monitor ddr load,
> and dcf controller to handle ddr register so we can get the
> right ddr frequency and make ddr controller happy work(which
> will implement in bl31). So we do ddr frequency scaling with
> following flow:
>
>              kernel                                bl31
>
>         monitor ddr load
>                 |
>                 |
>         get_target_rate
>                 |
>                 |           pass rate to bl31
>         clk_set_rate(ddr) --------------------->run dcf flow
>                 |                                   |
>                 |                                   |
>         wait dcf interrupt<-------------------trigger dcf interrupt
>                 |
>                 |
>               return

Hi Lin,

can you confirm that the hardware isn't capable of raising interrupts
when programmable load thresholds are trespassed? From reading the
TRM, looks like it should be possible.

Or is there any reason to merge now a driver that polls for load stats?

Thanks,

Tomeu

> Lin Huang (6):
>   clk: rockchip: add new clock-type for the ddrclk
>   clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>   clk: rockchip: rk3399: add ddrc clock support
>   PM / devfreq: event: support rockchip dfi controller
>   PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>   drm/rockchip: Add dmc notifier in vop driver
>
>
> Heiko Stübner (1):
>   clk: rockchip: add clock flag parameter when register pll
>
> Lin Huang (6):
>   clk: rockchip: add new clock-type for the ddrclk
>   clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
>   clk: rockchip: rk3399: add ddrc clock support
>   PM / devfreq: event: support rockchip dfi controller
>   PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
>   drm/rockchip: Add dmc notifier in vop driver
>
>  drivers/clk/rockchip/Makefile               |   1 +
>  drivers/clk/rockchip/clk-ddr.c              | 146 +++++++++
>  drivers/clk/rockchip/clk-pll.c              |   4 +-
>  drivers/clk/rockchip/clk-rk3399.c           |  19 ++
>  drivers/clk/rockchip/clk.c                  |  11 +-
>  drivers/clk/rockchip/clk.h                  |  29 +-
>  drivers/devfreq/Kconfig                     |   1 +
>  drivers/devfreq/Makefile                    |   1 +
>  drivers/devfreq/event/Kconfig               |   7 +
>  drivers/devfreq/event/Makefile              |   1 +
>  drivers/devfreq/event/rockchip-dfi.c        | 253 +++++++++++++++
>  drivers/devfreq/rockchip/Kconfig            |   8 +
>  drivers/devfreq/rockchip/Makefile           |   1 +
>  drivers/devfreq/rockchip/rk3399_dmc.c       | 473 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 124 +++++++-
>  include/dt-bindings/clock/rk3399-cru.h      |   1 +
>  include/soc/rockchip/rockchip_sip.h         |  27 ++
>  17 files changed, 1098 insertions(+), 9 deletions(-)
>  create mode 100644 drivers/clk/rockchip/clk-ddr.c
>  create mode 100644 drivers/devfreq/event/rockchip-dfi.c
>  create mode 100644 drivers/devfreq/rockchip/Kconfig
>  create mode 100644 drivers/devfreq/rockchip/Makefile
>  create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c
>  create mode 100644 include/soc/rockchip/rockchip_sip.h
>
> --
> 1.9.1
>

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