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Groups > linux.kernel > #1450873 > unrolled thread
| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2016-07-26 22:40 +0200 |
| Last post | 2016-08-01 11:20 +0200 |
| Articles | 20 on this page of 21 — 6 participants |
Back to article view | Back to linux.kernel
[PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 12/13] arm64: dts: add Allwinner A64 SoC .dtsi Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 03/13] clk: sunxi-ng: sun8i: Rename DDR and video plls Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 09/13] arm64: sunxi: Kconfig: add essential pinctrl driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 13/13] arm64: dts: add Pine64 support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 02/13] clk: sunxi-ng: mux: Add mux table support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
[PATCH 08/13] clk: sunxi-ng: Add A64 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
Re: [PATCH 08/13] clk: sunxi-ng: Add A64 clocks Rob Herring <robh@kernel.org> - 2016-07-29 23:20 +0200
[PATCH 10/13] arm64: Kconfig: sunxi: add PINCTRL Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-26 22:40 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Jean-Francois Moine <moinejf@free.fr> - 2016-07-27 10:50 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-28 22:10 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Jean-Francois Moine <moinejf@free.fr> - 2016-07-29 07:50 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-31 22:30 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng André Przywara <andre.przywara@arm.com> - 2016-08-01 03:50 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Jean-Francois Moine <moinejf@free.fr> - 2016-08-01 10:40 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Chen-Yu Tsai <wens@csie.org> - 2016-08-01 11:20 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Jean-Francois Moine <moinejf@free.fr> - 2016-08-01 14:10 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Chen-Yu Tsai <wens@csie.org> - 2016-08-01 14:10 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Jean-Francois Moine <moinejf@free.fr> - 2016-08-01 14:20 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Andre Przywara <andre.przywara@arm.com> - 2016-08-01 12:50 +0200
Re: [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng Chen-Yu Tsai <wens@csie.org> - 2016-08-01 11:20 +0200
Page 1 of 2 [1] 2 Next page →
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 00/13] arm64: Allwinner A64 support based on sunxi-ng |
| Message-ID | <rZhiV-6Jx-3@gated-at.bofh.it> |
Hi, Here is the previous A64 patches made by Andre [1], reworked to use the new sunxi-ng clock framework. This uses the current H3 clock code, as both are really similar. The first patches are just meant to rework slightly the H3 code, before introducing the A64-related patches. Some WiP stuff have been removed, such as the MMC part, but this serie already has a decent amount of devices supported: uart, i2c, rsb, etc. Let me know what you think, Maxime 1: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/410338.html Andre Przywara (5): arm64: sunxi: Kconfig: add essential pinctrl driver arm64: Kconfig: sunxi: add PINCTRL Documentation: devicetree: add vendor prefix for Pine64 arm64: dts: add Allwinner A64 SoC .dtsi arm64: dts: add Pine64 support Maxime Ripard (8): clk: sunxi-ng: mux: Rename mux macro to be consistent clk: sunxi-ng: mux: Add mux table support clk: sunxi-ng: sun8i: Rename DDR and video plls clk: sunxi-ng: sun8i: Fix register offset clk: sunxi-ng: sun8i: Rename H3 only clocks clk: sunxi-ng: sun8i: Move fixed factors around clk: sunxi-ng: sun8i: Prefix clock defines by SoC Name clk: sunxi-ng: Add A64 clocks Documentation/devicetree/bindings/arm/sunxi.txt | 1 + .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 1 + arch/arm/boot/dts/sun8i-h3.dtsi | 62 +- arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 + .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 273 +++++++ drivers/clk/sunxi-ng/Kconfig | 13 +- drivers/clk/sunxi-ng/Makefile | 2 +- drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 896 ++++++++++++++++----- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 44 +- drivers/clk/sunxi-ng/ccu_div.h | 2 +- drivers/clk/sunxi-ng/ccu_mp.h | 2 +- drivers/clk/sunxi-ng/ccu_mux.c | 14 + drivers/clk/sunxi-ng/ccu_mux.h | 29 +- include/dt-bindings/clock/sun50i-a64-ccu.h | 132 +++ include/dt-bindings/clock/sun8i-h3-ccu.h | 188 ++--- include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ 23 files changed, 1588 insertions(+), 366 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h -- 2.9.2
[toc] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 12/13] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <rZhiW-6Jx-41@gated-at.bofh.it> |
| In reply to | #1450873 |
From: Andre Przywara <andre.przywara@arm.com>
The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
and the typical tablet / TV box peripherals.
The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
the peripherals and the memory map.
Although the cores are proper 64-bit ones, the whole SoC is actually
limited to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
[Maxime: Convert to CCU binding, drop the MMC support for now]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
MAINTAINERS | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 273 ++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 7e79fcc36b0d..7e59d8ba86af 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,3 +14,4 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
+ allwinner,sun50i-a64
diff --git a/MAINTAINERS b/MAINTAINERS
index 7304d2e37a98..440490126bfb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -955,6 +955,7 @@ M: Chen-Yu Tsai <wens@csie.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: sun[x456789]i
+F: arch/arm64/boot/dts/allwinner/
ARM/Allwinner SoC Clock Support
M: Emilio López <emilio@elopez.com.ar>
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
new file mode 100644
index 000000000000..636165d75373
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -0,0 +1,273 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ccu: clock@01c20000 {
+ compatible = "allwinner,sun50i-a64-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,sun50i-a64-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_A64_BUS_PIO>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ i2c1_pins: i2c1_pins {
+ allwinner,pins = "PH2", "PH3";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB8", "PB9";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ uart0: serial@1c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_A64_BUS_UART0>;
+ resets = <&ccu RST_A64_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_A64_BUS_UART1>;
+ resets = <&ccu RST_A64_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_A64_BUS_UART2>;
+ resets = <&ccu RST_A64_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_A64_BUS_UART3>;
+ resets = <&ccu RST_A64_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@1c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_A64_BUS_UART4>;
+ resets = <&ccu RST_A64_BUS_UART4>;
+ status = "disabled";
+ };
+
+ rtc: rtc@1f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_A64_BUS_I2C0>;
+ resets = <&ccu RST_A64_BUS_I2C0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_A64_BUS_I2C1>;
+ resets = <&ccu RST_A64_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_A64_BUS_I2C2>;
+ resets = <&ccu RST_A64_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
--
2.9.2
[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 03/13] clk: sunxi-ng: sun8i: Rename DDR and video plls |
| Message-ID | <rZhiW-6Jx-23@gated-at.bofh.it> |
| In reply to | #1450873 |
In order to deal with the A64 that will have several video and ddr plls,
rename the first ones to add an index.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 9af359544110..68492808e5fc 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -57,8 +57,8 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
0);
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
- "osc24M", 0x0010,
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
+ "osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
@@ -81,7 +81,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
BIT(28), /* lock */
0);
-static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
@@ -422,7 +422,7 @@ static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
0x0cc, BIT(19), 0);
-static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
+static const char * const dram_parents[] = { "pll-ddr0", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
@@ -439,7 +439,7 @@ static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31), 0);
-static const char * const tcon_parents[] = { "pll-video" };
+static const char * const tcon_parents[] = { "pll-video0" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);
@@ -458,7 +458,7 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
-static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
@@ -470,14 +470,14 @@ static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
-static const char * const hdmi_parents[] = { "pll-video" };
+static const char * const hdmi_parents[] = { "pll-video0" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0x150, 0, 4, 24, 2, BIT(31), 0);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
-static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
+static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr0" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
@@ -487,9 +487,9 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
static struct ccu_common *sun8i_h3_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
- &pll_video_clk.common,
+ &pll_video0_clk.common,
&pll_ve_clk.common,
- &pll_ddr_clk.common,
+ &pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_gpu_clk.common,
&pll_periph1_clk.common,
--
2.9.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 09/13] arm64: sunxi: Kconfig: add essential pinctrl driver |
| Message-ID | <rZhiW-6Jx-29@gated-at.bofh.it> |
| In reply to | #1450873 |
From: Andre Przywara <andre.przywara@arm.com> The pinctrl driver is essential for the Allwinner SoCs to work. Add the driver's config symbol to the Kconfig entry to always compile it in. We can't use the arm approach to make the _driver's_ Kconfig symbol def_bool, because we lack the MACH_* symbols in arm64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 7ef1d05859ae..4cc444c3c2e9 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -3,6 +3,7 @@ menu "Platform selection" config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select GENERIC_IRQ_CHIP + select PINCTRL_SUN50I_A64 help This enables support for Allwinner sunxi based SoCs like the A64. -- 2.9.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 13/13] arm64: dts: add Pine64 support |
| Message-ID | <rZhiW-6Jx-31@gated-at.bofh.it> |
| In reply to | #1450873 |
From: Andre Przywara <andre.przywara@arm.com>
The Pine64 is a cost-efficient development board based on the
Allwinner A64 SoC.
There are three models: the basic version with Fast Ethernet and
512 MB of DRAM (Pine64) and two Pine64+ versions, which both
feature Gigabit Ethernet and additional connectors for touchscreens
and a camera. Or as my son put it: "Those are smaller and these are
missing." ;-)
The two Pine64+ models just differ in the amount of DRAM
(1GB vs. 2GB). Since U-Boot will figure out the right size for us and
patches the DT accordingly we just need to provide one DT for the
Pine64+.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Maxime: Removed the common DTSI and include directly the pine64 DTS]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/allwinner/Makefile | 5 ++
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++
4 files changed, 126 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 6e199c903676..ddcbf5a2c17e 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,4 +1,5 @@
dts-dirs += al
+dts-dirs += allwinner
dts-dirs += altera
dts-dirs += amd
dts-dirs += amlogic
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
new file mode 100644
index 000000000000..1e29a5ae8282
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
new file mode 100644
index 000000000000..790d14daaa6a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun50i-a64-pine64.dts"
+
+/ {
+ model = "Pine64+";
+ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
+
+ /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
new file mode 100644
index 000000000000..da9bca51f5a9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+/ {
+ model = "Pine64";
+ compatible = "pine64,pine64", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
--
2.9.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 02/13] clk: sunxi-ng: mux: Add mux table support |
| Message-ID | <rZhiW-6Jx-37@gated-at.bofh.it> |
| In reply to | #1450873 |
Add support for the table based muxes, and add macros to register them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi-ng/ccu_mux.c | 14 ++++++++++++++
drivers/clk/sunxi-ng/ccu_mux.h | 27 ++++++++++++++++++++-------
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 58fc36e7dcce..f942044b038a 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -100,6 +100,7 @@ out:
u8 ccu_mux_helper_get_parent(struct ccu_common *common,
struct ccu_mux_internal *cm)
{
+ int num_parents = clk_hw_get_num_parents(&common->hw);
u32 reg;
u8 parent;
@@ -107,6 +108,16 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
parent = reg >> cm->shift;
parent &= (1 << cm->width) - 1;
+ if (cm->table) {
+ int i;
+
+ for (i = 0; i < num_parents; i++)
+ if (cm->table[i] == parent)
+ return i;
+
+ return -EINVAL;
+ }
+
return parent;
}
@@ -117,6 +128,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
unsigned long flags;
u32 reg;
+ if (cm->table)
+ index = cm->table[index];
+
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 95cfecec3c39..00cec8ac6ae3 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -9,6 +9,8 @@ struct ccu_mux_internal {
u8 shift;
u8 width;
+ const u8 *table;
+
struct {
u8 index;
u8 div;
@@ -21,12 +23,16 @@ struct ccu_mux_internal {
} variable_prediv;
};
-#define _SUNXI_CCU_MUX(_shift, _width) \
- { \
- .shift = _shift, \
- .width = _width, \
+#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \
+ { \
+ .shift = _shift, \
+ .width = _width, \
+ .table = _table, \
}
+#define _SUNXI_CCU_MUX(_shift, _width) \
+ _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
+
struct ccu_mux {
u16 reg;
u32 enable;
@@ -47,11 +53,12 @@ struct ccu_mux {
} \
}
-#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
- _shift, _width, _gate, _flags) \
+#define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \
+ _reg, _shift, _width, _gate, \
+ _flags) \
struct ccu_mux _struct = { \
.enable = _gate, \
- .mux = _SUNXI_CCU_MUX(_shift, _width), \
+ .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_PARENTS(_name, \
@@ -61,6 +68,12 @@ struct ccu_mux {
} \
}
+#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
+ _shift, _width, _gate, _flags) \
+ SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
+ _reg, _shift, _width, _gate, \
+ _flags)
+
static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
--
2.9.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 08/13] clk: sunxi-ng: Add A64 clocks |
| Message-ID | <rZhiX-6Jx-47@gated-at.bofh.it> |
| In reply to | #1450873 |
Add the A64 CCU clocks set.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
drivers/clk/sunxi-ng/Kconfig | 13 +-
drivers/clk/sunxi-ng/Makefile | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 +++
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 483 +++++++++++++++++++++
include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++++
include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++++
7 files changed, 793 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index cb91507ffb1e..1502fc6a4aae 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -4,6 +4,7 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatible:
- "allwinner,sun8i-h3-ccu"
+ - "allwinner,sun50i-a64-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 2afcbd39e41e..81419f63730f 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -51,8 +51,8 @@ config SUNXI_CCU_MP
# SoC Drivers
-config SUN8I_H3_CCU
- bool "Support for the Allwinner H3 CCU"
+config SUNXI_H3_A64_CCU_SUPPORT
+ bool
select SUNXI_CCU_DIV
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
@@ -60,6 +60,15 @@ config SUN8I_H3_CCU
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
+
+config SUN8I_H3_CCU
+ bool "Support for the Allwinner H3 CCU"
+ select SUNXI_H3_A64_CCU_SUPPORT
default MACH_SUN8I
+config SUN50I_A64_CCU
+ bool "Support for the Allwinner A64 CCU"
+ select SUNXI_H3_A64_CCU_SUPPORT
+ default ARM64 && ARCH_SUNXI
+
endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 633ce642ffae..d46c460a2cd9 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -17,4 +17,4 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
# SoC support
-obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
+obj-$(CONFIG_SUNXI_H3_A64_CCU_SUPPORT) += ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
new file mode 100644
index 000000000000..127817ace780
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN50I_A64_H_
+#define _CCU_SUN50I_A64_H_
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+#define CLK_A64_OSC_12M 0
+#define CLK_A64_PLL_CPUX 1
+#define CLK_A64_PLL_AUDIO_BASE 2
+#define CLK_A64_PLL_AUDIO 3
+#define CLK_A64_PLL_AUDIO_2X 4
+#define CLK_A64_PLL_AUDIO_4X 5
+#define CLK_A64_PLL_AUDIO_8X 6
+#define CLK_A64_PLL_VIDEO0 7
+#define CLK_A64_PLL_VIDEO0_2X 8
+#define CLK_A64_PLL_VE 9
+#define CLK_A64_PLL_DDR0 10
+#define CLK_A64_PLL_PERIPH0 11
+#define CLK_A64_PLL_PERIPH0_2X 12
+#define CLK_A64_PLL_PERIPH1 13
+#define CLK_A64_PLL_PERIPH1_2X 14
+#define CLK_A64_PLL_VIDEO1 15
+#define CLK_A64_PLL_GPU 16
+#define CLK_A64_PLL_MIPI 17
+#define CLK_A64_PLL_HSIC 18
+#define CLK_A64_PLL_DE 19
+#define CLK_A64_PLL_DDR1 20
+#define CLK_A64_CPUX 21
+#define CLK_A64_AXI 22
+#define CLK_A64_APB 23
+#define CLK_A64_AHB1 24
+#define CLK_A64_APB1 25
+#define CLK_A64_APB2 26
+#define CLK_A64_AHB2 27
+
+/* All the bus gates are exported */
+
+/* The first bunch of module clocks are exported */
+
+#define CLK_A64_DRAM 92
+
+/* All the DRAM gates are exported */
+
+/* Some more module clocks are exported */
+
+#define CLK_A64_MBUS 110
+
+/* And the DSI and GPU module clock is exported */
+
+#define CLK_A64_NUMBER (CLK_A64_GPU + 1)
+
+#endif /* _CCU_SUN50I_A64_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 2e91f43937c8..cb0dbeb386b0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -27,6 +27,7 @@
#include "ccu_nm.h"
#include "ccu_phase.h"
+#include "ccu-sun50i-a64.h"
#include "ccu-sun8i-h3.h"
static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
@@ -99,6 +100,27 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
2, /* post-div */
0);
+static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_a64_clk, "pll-periph1",
+ "osc24M", 0x02c,
+ 8, 5, /* N */
+ 4, 2, /* K */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_a64_clk, "pll-video1",
+ "osc24M", 0x030,
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 0);
+
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
@@ -111,6 +133,35 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
BIT(28), /* lock */
0);
+/*
+ * The output function can be changed to something more complex that
+ * we do not handle yet.
+ *
+ * Hardcode the mode so that we don't fall in that case.
+ */
+#define SUN50I_A64_PLL_MIPI_REG 0x040
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_a64_clk, "pll-mipi",
+ "pll-video0", 0x040,
+ 8, 4, /* N */
+ 4, 2, /* K */
+ 0, 4, /* M */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_a64_clk, "pll-hsic",
+ "osc24M", 0x044,
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 0);
+
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_h3_clk, "pll-periph1",
"osc24M", 0x044,
8, 5, /* N */
@@ -132,6 +183,14 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
BIT(28), /* lock */
0);
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_a64_clk, "pll-ddr1",
+ "osc24M", 0x04c,
+ 8, 7, /* N */
+ 0, 2, /* M */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 0);
+
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
@@ -175,6 +234,15 @@ static struct clk_div_table apb1_div_table[] = {
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
+static const char * const apb2_a64_parents[] = { "osc32k", "osc24M",
+ "pll-periph0-2x" ,
+ "pll-periph0-2x" };
+static SUNXI_CCU_MP_WITH_MUX(apb2_a64_clk, "apb2", apb2_a64_parents, 0x058,
+ 0, 5, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
static const char * const apb2_h3_parents[] = { "osc32k", "osc24M",
"pll-periph0" , "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(apb2_h3_clk, "apb2", apb2_h3_parents, 0x058,
@@ -205,6 +273,8 @@ static struct ccu_mux ahb2_clk = {
},
};
+static SUNXI_CCU_GATE(bus_mipi_dsi_a64_clk, "bus-mipi-dsi", "ahb1",
+ 0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
@@ -292,6 +362,8 @@ static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_scr_a64_clk, "bus-scr", "apb2",
+ 0x06c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
@@ -300,6 +372,8 @@ static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_uart4_a64_clk, "bus-uart4", "apb2",
+ 0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(bus_scr_h3_clk, "bus-scr", "apb2",
0x06c, BIT(20), 0);
@@ -326,6 +400,15 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
BIT(31), /* gate */
0);
+static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
+ "pll-periph1-2x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_a64_clk, "mmc0", mmc_default_parents, 0x088,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_h3_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
@@ -338,6 +421,13 @@ static SUNXI_CCU_PHASE(mmc0_sample_h3_clk, "mmc0_sample", "mmc0",
static SUNXI_CCU_PHASE(mmc0_output_h3_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_a64_clk, "mmc1", mmc_default_parents, 0x08c,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_h3_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
@@ -350,6 +440,13 @@ static SUNXI_CCU_PHASE(mmc1_sample_h3_clk, "mmc1_sample", "mmc1",
static SUNXI_CCU_PHASE(mmc1_output_h3_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_a64_clk, "mmc2", mmc_default_parents, 0x090,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_h3_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
@@ -370,6 +467,14 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
BIT(31), /* gate */
0);
+static SUNXI_CCU_MP_WITH_MUX_GATE(ce_a64_clk, "ce", mmc_default_parents, 0x09c,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_h3_clk, "ce", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
@@ -409,12 +514,20 @@ static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
+static SUNXI_CCU_GATE(usb_hsic_a64_clk, "usb-hsic", "pll-hsic",
+ 0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_phy2_h3_clk, "usb-phy2", "osc24M",
0x0cc, BIT(10), 0);
+static SUNXI_CCU_GATE(usb_hsic_12m_a64_clk, "usb-hsic-12M", "osc12M",
+ 0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_phy3_h3_clk, "usb-phy3", "osc24M",
0x0cc, BIT(11), 0);
+static SUNXI_CCU_GATE(usb_ohci0_a64_clk, "usb-ohci0", "osc12M",
+ 0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(usb_ohci0_h3_clk, "usb-ohci0", "osc24M",
0x0cc, BIT(16), 0);
+static SUNXI_CCU_GATE(usb_ohci1_a64_clk, "usb-ohci1", "usb-ohci0",
+ 0x0cc, BIT(17), 0);
static SUNXI_CCU_GATE(usb_ohci1_h3_clk, "usb-ohci1", "osc24M",
0x0cc, BIT(17), 0);
static SUNXI_CCU_GATE(usb_ohci2_h3_clk, "usb-ohci2", "osc24M",
@@ -422,6 +535,10 @@ static SUNXI_CCU_GATE(usb_ohci2_h3_clk, "usb-ohci2", "osc24M",
static SUNXI_CCU_GATE(usb_ohci3_h3_clk, "usb-ohci3", "osc24M",
0x0cc, BIT(19), 0);
+static const char * const dram_a64_parents[] = { "pll-ddr0", "pll-ddr1" };
+static SUNXI_CCU_M_WITH_MUX(dram_a64_clk, "dram", dram_a64_parents,
+ 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
+
static const char * const dram_h3_parents[] = { "pll-ddr0", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(dram_h3_clk, "dram", dram_h3_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
@@ -439,10 +556,30 @@ static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31), 0);
+static const char * const tcon0_a64_parents[] = { "pll-mipi", "pll-video0-2x" };
+static const u8 tcon0_a64_table[] = { 0, 2, };
+static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_a64_clk, "tcon0", tcon0_a64_parents,
+ tcon0_a64_table, 0x118, 24, 3, BIT(31), 0);
+
static const char * const tcon0_h3_parents[] = { "pll-video0" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_h3_clk, "tcon0", tcon0_h3_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);
+static const char * const tcon1_a64_parents[] = { "pll-video0", "pll-video1" };
+static const u8 tcon1_a64_table[] = { 0, 2, };
+struct ccu_div tcon1_a64_clk = {
+ .enable = BIT(31),
+ .div = _SUNXI_CCU_DIV(0, 4),
+ .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_a64_table),
+ .common = {
+ .reg = 0x11c,
+ .hw.init = CLK_HW_INIT_PARENTS("tcon1",
+ tcon1_a64_parents,
+ &ccu_div_ops,
+ 0),
+ },
+};
+
static const char * const tve_h3_parents[] = { "pll-de", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(tve_h3_clk, "tve", tve_h3_parents,
0x120, 0, 4, 24, 3, BIT(31), 0);
@@ -458,6 +595,10 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
+static const char * const csi_mclk_a64_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_a64_clk, "csi-mclk", csi_mclk_a64_parents,
+ 0x134, 0, 5, 8, 3, BIT(15), 0);
+
static const char * const csi_mclk_h3_parents[] = { "osc24M", "pll-video0", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_h3_clk, "csi-mclk", csi_mclk_h3_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
@@ -467,9 +608,17 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), 0);
+
+static SUNXI_CCU_GATE(ac_dig_4x_a64_clk, "ac-dig-4x", "pll-audio-4x",
+ 0x140, BIT(30), 0);
+
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
+static const char * const hdmi_a64_parents[] = { "pll-video0", "pll-video1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_a64_clk, "hdmi", hdmi_a64_parents,
+ 0x150, 0, 4, 24, 2, BIT(31), 0);
+
static const char * const hdmi_h3_parents[] = { "pll-video0" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_h3_clk, "hdmi", hdmi_h3_parents,
0x150, 0, 4, 24, 2, BIT(31), 0);
@@ -477,14 +626,25 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_h3_clk, "hdmi", hdmi_h3_parents,
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
+static const char * const mbus_a64_parents[] = { "osc24M", "pll-periph0-2x",
+ "pll-ddr0", "pll-ddr1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(mbus_a64_clk, "mbus", mbus_a64_parents,
+ 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
+
static const char * const mbus_h3_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr0" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_h3_clk, "mbus", mbus_h3_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
+static const char * const dsi_dphy_a64_parents[] = { "pll-video0", "pll-periph0" };
+static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_a64_clk, "dsi-dphy", dsi_dphy_a64_parents,
+ 0x168, 0, 3, 24, 2, BIT(31), 0);
+
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), 0);
/* Fixed Factor clocks */
+static CLK_FIXED_FACTOR(osc12M_a64_clk, "osc12M", "osc24M", 1, 2, 0);
+
/* We hardcode the divider to 4 for now */
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
@@ -496,6 +656,10 @@ static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
"pll-periph0", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
+ "pll-periph1", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
+ "pll-video0", 1, 2, 0);
static struct ccu_common *sun8i_h3_ccu_clks[] = {
&pll_cpux_clk.common,
@@ -825,3 +989,322 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
}
CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
sun8i_h3_ccu_setup);
+
+static struct ccu_common *sun50i_a64_ccu_clks[] = {
+ &pll_cpux_clk.common,
+ &pll_audio_base_clk.common,
+ &pll_video0_clk.common,
+ &pll_ve_clk.common,
+ &pll_ddr0_clk.common,
+ &pll_periph0_clk.common,
+ &pll_periph1_a64_clk.common,
+ &pll_video1_a64_clk.common,
+ &pll_gpu_clk.common,
+ &pll_mipi_a64_clk.common,
+ &pll_hsic_a64_clk.common,
+ &pll_de_clk.common,
+ &pll_ddr1_a64_clk.common,
+ &cpux_clk.common,
+ &axi_clk.common,
+ &ahb1_clk.common,
+ &apb1_clk.common,
+ &apb2_a64_clk.common,
+ &ahb2_clk.common,
+ &bus_mipi_dsi_a64_clk.common,
+ &bus_ce_clk.common,
+ &bus_dma_clk.common,
+ &bus_mmc0_clk.common,
+ &bus_mmc1_clk.common,
+ &bus_mmc2_clk.common,
+ &bus_nand_clk.common,
+ &bus_dram_clk.common,
+ &bus_emac_clk.common,
+ &bus_ts_clk.common,
+ &bus_hstimer_clk.common,
+ &bus_spi0_clk.common,
+ &bus_spi1_clk.common,
+ &bus_otg_clk.common,
+ &bus_ehci0_clk.common,
+ &bus_ehci1_clk.common,
+ &bus_ohci0_clk.common,
+ &bus_ohci1_clk.common,
+ &bus_ve_clk.common,
+ &bus_tcon0_clk.common,
+ &bus_tcon1_clk.common,
+ &bus_deinterlace_clk.common,
+ &bus_csi_clk.common,
+ &bus_hdmi_clk.common,
+ &bus_de_clk.common,
+ &bus_gpu_clk.common,
+ &bus_msgbox_clk.common,
+ &bus_spinlock_clk.common,
+ &bus_codec_clk.common,
+ &bus_spdif_clk.common,
+ &bus_pio_clk.common,
+ &bus_ths_clk.common,
+ &bus_i2s0_clk.common,
+ &bus_i2s1_clk.common,
+ &bus_i2s2_clk.common,
+ &bus_i2c0_clk.common,
+ &bus_i2c1_clk.common,
+ &bus_i2c2_clk.common,
+ &bus_scr_a64_clk.common,
+ &bus_uart0_clk.common,
+ &bus_uart1_clk.common,
+ &bus_uart2_clk.common,
+ &bus_uart3_clk.common,
+ &bus_uart4_a64_clk.common,
+ &bus_dbg_clk.common,
+ &ths_clk.common,
+ &nand_clk.common,
+ &mmc0_a64_clk.common,
+ &mmc1_a64_clk.common,
+ &mmc2_a64_clk.common,
+ &ts_clk.common,
+ &ce_a64_clk.common,
+ &spi0_clk.common,
+ &spi1_clk.common,
+ &i2s0_clk.common,
+ &i2s1_clk.common,
+ &i2s2_clk.common,
+ &spdif_clk.common,
+ &usb_phy0_clk.common,
+ &usb_phy1_clk.common,
+ &usb_hsic_a64_clk.common,
+ &usb_hsic_12m_a64_clk.common,
+ &usb_ohci0_a64_clk.common,
+ &usb_ohci1_a64_clk.common,
+ &dram_a64_clk.common,
+ &dram_ve_clk.common,
+ &dram_csi_clk.common,
+ &dram_deinterlace_clk.common,
+ &dram_ts_clk.common,
+ &de_clk.common,
+ &tcon0_a64_clk.common,
+ &tcon1_a64_clk.common,
+ &deinterlace_clk.common,
+ &csi_misc_clk.common,
+ &csi_sclk_clk.common,
+ &csi_mclk_a64_clk.common,
+ &ve_clk.common,
+ &ac_dig_clk.common,
+ &ac_dig_4x_a64_clk.common,
+ &avs_clk.common,
+ &hdmi_a64_clk.common,
+ &hdmi_ddc_clk.common,
+ &mbus_a64_clk.common,
+ &dsi_dphy_a64_clk.common,
+ &gpu_clk.common,
+};
+
+static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
+ .hws = {
+ [CLK_A64_OSC_12M] = &osc12M_a64_clk.hw,
+ [CLK_A64_PLL_CPUX] = &pll_cpux_clk.common.hw,
+ [CLK_A64_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
+ [CLK_A64_PLL_AUDIO] = &pll_audio_clk.hw,
+ [CLK_A64_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
+ [CLK_A64_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
+ [CLK_A64_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
+ [CLK_A64_PLL_VIDEO0] = &pll_video0_clk.common.hw,
+ [CLK_A64_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
+ [CLK_A64_PLL_VE] = &pll_ve_clk.common.hw,
+ [CLK_A64_PLL_DDR0] = &pll_ddr0_clk.common.hw,
+ [CLK_A64_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
+ [CLK_A64_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
+ [CLK_A64_PLL_PERIPH1] = &pll_periph1_a64_clk.common.hw,
+ [CLK_A64_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
+ [CLK_A64_PLL_VIDEO1] = &pll_video1_a64_clk.common.hw,
+ [CLK_A64_PLL_GPU] = &pll_gpu_clk.common.hw,
+ [CLK_A64_PLL_MIPI] = &pll_mipi_a64_clk.common.hw,
+ [CLK_A64_PLL_HSIC] = &pll_hsic_a64_clk.common.hw,
+ [CLK_A64_PLL_DE] = &pll_de_clk.common.hw,
+ [CLK_A64_PLL_DDR1] = &pll_ddr1_a64_clk.common.hw,
+ [CLK_A64_CPUX] = &cpux_clk.common.hw,
+ [CLK_A64_AXI] = &axi_clk.common.hw,
+ [CLK_A64_AHB1] = &ahb1_clk.common.hw,
+ [CLK_A64_APB1] = &apb1_clk.common.hw,
+ [CLK_A64_APB2] = &apb2_a64_clk.common.hw,
+ [CLK_A64_AHB2] = &ahb2_clk.common.hw,
+ [CLK_A64_BUS_MIPI_DSI] = &bus_mipi_dsi_a64_clk.common.hw,
+ [CLK_A64_BUS_CE] = &bus_ce_clk.common.hw,
+ [CLK_A64_BUS_DMA] = &bus_dma_clk.common.hw,
+ [CLK_A64_BUS_MMC0] = &bus_mmc0_clk.common.hw,
+ [CLK_A64_BUS_MMC1] = &bus_mmc1_clk.common.hw,
+ [CLK_A64_BUS_MMC2] = &bus_mmc2_clk.common.hw,
+ [CLK_A64_BUS_NAND] = &bus_nand_clk.common.hw,
+ [CLK_A64_BUS_DRAM] = &bus_dram_clk.common.hw,
+ [CLK_A64_BUS_EMAC] = &bus_emac_clk.common.hw,
+ [CLK_A64_BUS_TS] = &bus_ts_clk.common.hw,
+ [CLK_A64_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
+ [CLK_A64_BUS_SPI0] = &bus_spi0_clk.common.hw,
+ [CLK_A64_BUS_SPI1] = &bus_spi1_clk.common.hw,
+ [CLK_A64_BUS_OTG] = &bus_otg_clk.common.hw,
+ [CLK_A64_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
+ [CLK_A64_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
+ [CLK_A64_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
+ [CLK_A64_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
+ [CLK_A64_BUS_VE] = &bus_ve_clk.common.hw,
+ [CLK_A64_BUS_TCON0] = &bus_tcon0_clk.common.hw,
+ [CLK_A64_BUS_TCON1] = &bus_tcon1_clk.common.hw,
+ [CLK_A64_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
+ [CLK_A64_BUS_CSI] = &bus_csi_clk.common.hw,
+ [CLK_A64_BUS_HDMI] = &bus_hdmi_clk.common.hw,
+ [CLK_A64_BUS_DE] = &bus_de_clk.common.hw,
+ [CLK_A64_BUS_GPU] = &bus_gpu_clk.common.hw,
+ [CLK_A64_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
+ [CLK_A64_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
+ [CLK_A64_BUS_CODEC] = &bus_codec_clk.common.hw,
+ [CLK_A64_BUS_SPDIF] = &bus_spdif_clk.common.hw,
+ [CLK_A64_BUS_PIO] = &bus_pio_clk.common.hw,
+ [CLK_A64_BUS_THS] = &bus_ths_clk.common.hw,
+ [CLK_A64_BUS_I2S0] = &bus_i2s0_clk.common.hw,
+ [CLK_A64_BUS_I2S1] = &bus_i2s1_clk.common.hw,
+ [CLK_A64_BUS_I2S2] = &bus_i2s2_clk.common.hw,
+ [CLK_A64_BUS_I2C0] = &bus_i2c0_clk.common.hw,
+ [CLK_A64_BUS_I2C1] = &bus_i2c1_clk.common.hw,
+ [CLK_A64_BUS_I2C2] = &bus_i2c2_clk.common.hw,
+ [CLK_A64_BUS_UART0] = &bus_uart0_clk.common.hw,
+ [CLK_A64_BUS_UART1] = &bus_uart1_clk.common.hw,
+ [CLK_A64_BUS_UART2] = &bus_uart2_clk.common.hw,
+ [CLK_A64_BUS_UART3] = &bus_uart3_clk.common.hw,
+ [CLK_A64_BUS_UART4] = &bus_uart4_a64_clk.common.hw,
+ [CLK_A64_BUS_SCR] = &bus_scr_a64_clk.common.hw,
+ [CLK_A64_BUS_DBG] = &bus_dbg_clk.common.hw,
+ [CLK_A64_THS] = &ths_clk.common.hw,
+ [CLK_A64_NAND] = &nand_clk.common.hw,
+ [CLK_A64_MMC0] = &mmc0_a64_clk.common.hw,
+ [CLK_A64_MMC1] = &mmc1_a64_clk.common.hw,
+ [CLK_A64_MMC2] = &mmc2_a64_clk.common.hw,
+ [CLK_A64_TS] = &ts_clk.common.hw,
+ [CLK_A64_CE] = &ce_a64_clk.common.hw,
+ [CLK_A64_SPI0] = &spi0_clk.common.hw,
+ [CLK_A64_SPI1] = &spi1_clk.common.hw,
+ [CLK_A64_I2S0] = &i2s0_clk.common.hw,
+ [CLK_A64_I2S1] = &i2s1_clk.common.hw,
+ [CLK_A64_I2S2] = &i2s2_clk.common.hw,
+ [CLK_A64_SPDIF] = &spdif_clk.common.hw,
+ [CLK_A64_USB_PHY0] = &usb_phy0_clk.common.hw,
+ [CLK_A64_USB_PHY1] = &usb_phy1_clk.common.hw,
+ [CLK_A64_USB_HSIC] = &usb_hsic_a64_clk.common.hw,
+ [CLK_A64_USB_HSIC_12M] = &usb_hsic_12m_a64_clk.common.hw,
+ [CLK_A64_USB_OHCI0] = &usb_ohci0_a64_clk.common.hw,
+ [CLK_A64_USB_OHCI1] = &usb_ohci1_a64_clk.common.hw,
+ [CLK_A64_DRAM] = &dram_a64_clk.common.hw,
+ [CLK_A64_DRAM_VE] = &dram_ve_clk.common.hw,
+ [CLK_A64_DRAM_CSI] = &dram_csi_clk.common.hw,
+ [CLK_A64_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
+ [CLK_A64_DRAM_TS] = &dram_ts_clk.common.hw,
+ [CLK_A64_DE] = &de_clk.common.hw,
+ [CLK_A64_TCON0] = &tcon0_a64_clk.common.hw,
+ [CLK_A64_TCON1] = &tcon1_a64_clk.common.hw,
+ [CLK_A64_DEINTERLACE] = &deinterlace_clk.common.hw,
+ [CLK_A64_CSI_MISC] = &csi_misc_clk.common.hw,
+ [CLK_A64_CSI_SCLK] = &csi_sclk_clk.common.hw,
+ [CLK_A64_CSI_MCLK] = &csi_mclk_a64_clk.common.hw,
+ [CLK_A64_VE] = &ve_clk.common.hw,
+ [CLK_A64_AC_DIG] = &ac_dig_clk.common.hw,
+ [CLK_A64_AC_DIG_4X] = &ac_dig_4x_a64_clk.common.hw,
+ [CLK_A64_AVS] = &avs_clk.common.hw,
+ [CLK_A64_HDMI] = &hdmi_a64_clk.common.hw,
+ [CLK_A64_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
+ [CLK_A64_MBUS] = &mbus_a64_clk.common.hw,
+ [CLK_A64_DSI_DPHY] = &dsi_dphy_a64_clk.common.hw,
+ [CLK_A64_GPU] = &gpu_clk.common.hw,
+ },
+ .num = CLK_A64_NUMBER,
+};
+
+static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
+ [RST_A64_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_A64_USB_PHY1] = { 0x0cc, BIT(1) },
+ [RST_A64_USB_HSIC] = { 0x0cc, BIT(2) },
+
+
+ [RST_A64_MBUS] = { 0x0fc, BIT(31) },
+
+ [RST_A64_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
+ [RST_A64_BUS_CE] = { 0x2c0, BIT(5) },
+ [RST_A64_BUS_DMA] = { 0x2c0, BIT(6) },
+ [RST_A64_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_A64_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_A64_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_A64_BUS_NAND] = { 0x2c0, BIT(13) },
+ [RST_A64_BUS_DRAM] = { 0x2c0, BIT(14) },
+ [RST_A64_BUS_EMAC] = { 0x2c0, BIT(17) },
+ [RST_A64_BUS_TS] = { 0x2c0, BIT(18) },
+ [RST_A64_BUS_HSTIMER] = { 0x2c0, BIT(19) },
+ [RST_A64_BUS_SPI0] = { 0x2c0, BIT(20) },
+ [RST_A64_BUS_SPI1] = { 0x2c0, BIT(21) },
+ [RST_A64_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_A64_BUS_EHCI0] = { 0x2c0, BIT(24) },
+ [RST_A64_BUS_EHCI1] = { 0x2c0, BIT(25) },
+ [RST_A64_BUS_OHCI0] = { 0x2c0, BIT(28) },
+ [RST_A64_BUS_OHCI1] = { 0x2c0, BIT(29) },
+
+ [RST_A64_BUS_VE] = { 0x2c4, BIT(0) },
+ [RST_A64_BUS_TCON0] = { 0x2c4, BIT(3) },
+ [RST_A64_BUS_TCON1] = { 0x2c4, BIT(4) },
+ [RST_A64_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
+ [RST_A64_BUS_CSI] = { 0x2c4, BIT(8) },
+ [RST_A64_BUS_HDMI0] = { 0x2c4, BIT(10) },
+ [RST_A64_BUS_HDMI1] = { 0x2c4, BIT(11) },
+ [RST_A64_BUS_DE] = { 0x2c4, BIT(12) },
+ [RST_A64_BUS_GPU] = { 0x2c4, BIT(20) },
+ [RST_A64_BUS_MSGBOX] = { 0x2c4, BIT(21) },
+ [RST_A64_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
+ [RST_A64_BUS_DBG] = { 0x2c4, BIT(31) },
+
+ [RST_A64_BUS_LVDS] = { 0x2c8, BIT(0) },
+
+ [RST_A64_BUS_CODEC] = { 0x2d0, BIT(0) },
+ [RST_A64_BUS_SPDIF] = { 0x2d0, BIT(1) },
+ [RST_A64_BUS_THS] = { 0x2d0, BIT(8) },
+ [RST_A64_BUS_I2S0] = { 0x2d0, BIT(12) },
+ [RST_A64_BUS_I2S1] = { 0x2d0, BIT(13) },
+ [RST_A64_BUS_I2S2] = { 0x2d0, BIT(14) },
+
+ [RST_A64_BUS_I2C0] = { 0x2d4, BIT(0) },
+ [RST_A64_BUS_I2C1] = { 0x2d4, BIT(1) },
+ [RST_A64_BUS_I2C2] = { 0x2d4, BIT(2) },
+ [RST_A64_BUS_SCR] = { 0x2d4, BIT(5) },
+ [RST_A64_BUS_UART0] = { 0x2d4, BIT(16) },
+ [RST_A64_BUS_UART1] = { 0x2d4, BIT(17) },
+ [RST_A64_BUS_UART2] = { 0x2d4, BIT(18) },
+ [RST_A64_BUS_UART3] = { 0x2d4, BIT(19) },
+ [RST_A64_BUS_UART4] = { 0x2d4, BIT(20) },
+};
+
+static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
+ .ccu_clks = sun50i_a64_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
+
+ .hw_clks = &sun50i_a64_hw_clks,
+
+ .resets = sun50i_a64_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
+};
+
+static void __init sun50i_a64_ccu_setup(struct device_node *node)
+{
+ void __iomem *reg;
+ u32 val;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%s: Could not map the clock registers\n",
+ of_node_full_name(node));
+ return;
+ }
+
+ /* Force the PLL-Audio-1x divider to 4 */
+ val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
+ val &= ~GENMASK(19, 16);
+ writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
+
+ writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+
+ sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu",
+ sun50i_a64_ccu_setup);
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 000000000000..192fafc4b443
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_A64_BUS_MIPI_DSI 28
+#define CLK_A64_BUS_CE 29
+#define CLK_A64_BUS_DMA 30
+#define CLK_A64_BUS_MMC0 31
+#define CLK_A64_BUS_MMC1 32
+#define CLK_A64_BUS_MMC2 33
+#define CLK_A64_BUS_NAND 34
+#define CLK_A64_BUS_DRAM 35
+#define CLK_A64_BUS_EMAC 36
+#define CLK_A64_BUS_TS 37
+#define CLK_A64_BUS_HSTIMER 38
+#define CLK_A64_BUS_SPI0 39
+#define CLK_A64_BUS_SPI1 40
+#define CLK_A64_BUS_OTG 41
+#define CLK_A64_BUS_EHCI0 42
+#define CLK_A64_BUS_EHCI1 43
+#define CLK_A64_BUS_OHCI0 44
+#define CLK_A64_BUS_OHCI1 45
+#define CLK_A64_BUS_VE 46
+#define CLK_A64_BUS_TCON0 47
+#define CLK_A64_BUS_TCON1 48
+#define CLK_A64_BUS_DEINTERLACE 49
+#define CLK_A64_BUS_CSI 50
+#define CLK_A64_BUS_HDMI 51
+#define CLK_A64_BUS_DE 52
+#define CLK_A64_BUS_GPU 53
+#define CLK_A64_BUS_MSGBOX 54
+#define CLK_A64_BUS_SPINLOCK 55
+#define CLK_A64_BUS_CODEC 56
+#define CLK_A64_BUS_SPDIF 57
+#define CLK_A64_BUS_PIO 58
+#define CLK_A64_BUS_THS 59
+#define CLK_A64_BUS_I2S0 60
+#define CLK_A64_BUS_I2S1 61
+#define CLK_A64_BUS_I2S2 62
+#define CLK_A64_BUS_I2C0 63
+#define CLK_A64_BUS_I2C1 64
+#define CLK_A64_BUS_I2C2 65
+#define CLK_A64_BUS_SCR 66
+#define CLK_A64_BUS_UART0 67
+#define CLK_A64_BUS_UART1 68
+#define CLK_A64_BUS_UART2 69
+#define CLK_A64_BUS_UART3 70
+#define CLK_A64_BUS_UART4 71
+#define CLK_A64_BUS_DBG 72
+#define CLK_A64_THS 73
+#define CLK_A64_NAND 74
+#define CLK_A64_MMC0 75
+#define CLK_A64_MMC1 76
+#define CLK_A64_MMC2 77
+#define CLK_A64_TS 78
+#define CLK_A64_CE 79
+#define CLK_A64_SPI0 80
+#define CLK_A64_SPI1 81
+#define CLK_A64_I2S0 82
+#define CLK_A64_I2S1 83
+#define CLK_A64_I2S2 84
+#define CLK_A64_SPDIF 85
+#define CLK_A64_USB_PHY0 86
+#define CLK_A64_USB_PHY1 87
+#define CLK_A64_USB_HSIC 88
+#define CLK_A64_USB_HSIC_12M 89
+#define CLK_A64_USB_OHCI0 90
+#define CLK_A64_USB_OHCI1 91
+
+#define CLK_A64_DRAM_VE 93
+#define CLK_A64_DRAM_CSI 94
+#define CLK_A64_DRAM_DEINTERLACE 95
+#define CLK_A64_DRAM_TS 96
+#define CLK_A64_DE 97
+#define CLK_A64_TCON0 98
+#define CLK_A64_TCON1 99
+#define CLK_A64_DEINTERLACE 100
+#define CLK_A64_CSI_MISC 101
+#define CLK_A64_CSI_SCLK 102
+#define CLK_A64_CSI_MCLK 103
+#define CLK_A64_VE 104
+#define CLK_A64_AC_DIG 105
+#define CLK_A64_AC_DIG_4X 106
+#define CLK_A64_AVS 107
+#define CLK_A64_HDMI 108
+#define CLK_A64_HDMI_DDC 109
+
+#define CLK_A64_DSI_DPHY 111
+#define CLK_A64_GPU 112
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_A64_H_ */
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 000000000000..bf5932a7725c
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_A64_USB_PHY0 0
+#define RST_A64_USB_PHY1 1
+#define RST_A64_USB_HSIC 2
+#define RST_A64_MBUS 3
+#define RST_A64_BUS_MIPI_DSI 4
+#define RST_A64_BUS_CE 5
+#define RST_A64_BUS_DMA 6
+#define RST_A64_BUS_MMC0 7
+#define RST_A64_BUS_MMC1 8
+#define RST_A64_BUS_MMC2 9
+#define RST_A64_BUS_NAND 10
+#define RST_A64_BUS_DRAM 11
+#define RST_A64_BUS_EMAC 12
+#define RST_A64_BUS_TS 13
+#define RST_A64_BUS_HSTIMER 14
+#define RST_A64_BUS_SPI0 15
+#define RST_A64_BUS_SPI1 16
+#define RST_A64_BUS_OTG 17
+#define RST_A64_BUS_EHCI0 18
+#define RST_A64_BUS_EHCI1 19
+#define RST_A64_BUS_OHCI0 20
+#define RST_A64_BUS_OHCI1 21
+#define RST_A64_BUS_VE 22
+#define RST_A64_BUS_TCON0 23
+#define RST_A64_BUS_TCON1 24
+#define RST_A64_BUS_DEINTERLACE 25
+#define RST_A64_BUS_CSI 26
+#define RST_A64_BUS_HDMI0 27
+#define RST_A64_BUS_HDMI1 28
+#define RST_A64_BUS_DE 29
+#define RST_A64_BUS_GPU 30
+#define RST_A64_BUS_MSGBOX 31
+#define RST_A64_BUS_SPINLOCK 32
+#define RST_A64_BUS_DBG 33
+#define RST_A64_BUS_LVDS 34
+#define RST_A64_BUS_CODEC 35
+#define RST_A64_BUS_SPDIF 36
+#define RST_A64_BUS_THS 37
+#define RST_A64_BUS_I2S0 38
+#define RST_A64_BUS_I2S1 39
+#define RST_A64_BUS_I2S2 40
+#define RST_A64_BUS_I2C0 41
+#define RST_A64_BUS_I2C1 42
+#define RST_A64_BUS_I2C2 43
+#define RST_A64_BUS_SCR 44
+#define RST_A64_BUS_UART0 45
+#define RST_A64_BUS_UART1 46
+#define RST_A64_BUS_UART2 47
+#define RST_A64_BUS_UART3 48
+#define RST_A64_BUS_UART4 49
+
+#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
--
2.9.2
[toc] | [prev] | [next] | [standalone]
| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-07-29 23:20 +0200 |
| Subject | Re: [PATCH 08/13] clk: sunxi-ng: Add A64 clocks |
| Message-ID | <s0nmh-1FG-1@gated-at.bofh.it> |
| In reply to | #1450882 |
On Tue, Jul 26, 2016 at 10:30:36PM +0200, Maxime Ripard wrote: > Add the A64 CCU clocks set. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + Acked-by: Rob Herring <robh@kernel.org> > drivers/clk/sunxi-ng/Kconfig | 13 +- > drivers/clk/sunxi-ng/Makefile | 2 +- > drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 +++ > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 483 +++++++++++++++++++++ > include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++++ > include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++++ > 7 files changed, 793 insertions(+), 3 deletions(-) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h > create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h > create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-26 22:40 +0200 |
| Subject | [PATCH 10/13] arm64: Kconfig: sunxi: add PINCTRL |
| Message-ID | <rZhiX-6Jx-49@gated-at.bofh.it> |
| In reply to | #1450873 |
From: Andre Przywara <andre.przywara@arm.com> Add required PINCTRL symbol to cover non-defconfig setups. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4cc444c3c2e9..83bc4bf3513b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -3,6 +3,7 @@ menu "Platform selection" config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select GENERIC_IRQ_CHIP + select PINCTRL select PINCTRL_SUN50I_A64 help This enables support for Allwinner sunxi based SoCs like the A64. -- 2.9.2
[toc] | [prev] | [next] | [standalone]
| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-07-27 10:50 +0200 |
| Message-ID | <rZsHo-5to-15@gated-at.bofh.it> |
| In reply to | #1450873 |
On Tue, 26 Jul 2016 22:30:28 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > ere is the previous A64 patches made by Andre [1], reworked to use > the new sunxi-ng clock framework. > > This uses the current H3 clock code, as both are really similar. The > first patches are just meant to rework slightly the H3 code, before > introducing the A64-related patches. > > Some WiP stuff have been removed, such as the MMC part, but this serie > already has a decent amount of devices supported: uart, i2c, rsb, etc. > > Let me know what you think, I don't see the interest to have common code for 32bits and 64bits. The clock driver of a SoC will never evolve, so, it is simpler to copy the source common with the H3 into a clean A64 clock driver. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-28 22:10 +0200 |
| Message-ID | <rZZMZ-2Fu-15@gated-at.bofh.it> |
| In reply to | #1451126 |
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On Wed, Jul 27, 2016 at 10:46:23AM +0200, Jean-Francois Moine wrote: > On Tue, 26 Jul 2016 22:30:28 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > ere is the previous A64 patches made by Andre [1], reworked to use > > the new sunxi-ng clock framework. > > > > This uses the current H3 clock code, as both are really similar. The > > first patches are just meant to rework slightly the H3 code, before > > introducing the A64-related patches. > > > > Some WiP stuff have been removed, such as the MMC part, but this serie > > already has a decent amount of devices supported: uart, i2c, rsb, etc. > > > > Let me know what you think, > > I don't see the interest to have common code for 32bits and 64bits. > The clock driver of a SoC will never evolve, so, it is simpler to > copy the source common with the H3 into a clean A64 clock driver. I'm not sure why 32 bits vs 64 bits matters here. We're going to share a significant number of drivers already between armv7 and armv8, like MMC, EMAC, I2C, and so on. And I expect to share the data in other SoCs for the A10, A13 and A20 for example, or A23/A33, which have a lot of clocks in common too. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-07-29 07:50 +0200 |
| Message-ID | <s08Qh-sV-1@gated-at.bofh.it> |
| In reply to | #1452085 |
On Thu, 28 Jul 2016 22:07:05 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > Let me know what you think, > > > > I don't see the interest to have common code for 32bits and 64bits. > > The clock driver of a SoC will never evolve, so, it is simpler to > > copy the source common with the H3 into a clean A64 clock driver. > > I'm not sure why 32 bits vs 64 bits matters here. We're going to share > a significant number of drivers already between armv7 and armv8, like > MMC, EMAC, I2C, and so on. > > And I expect to share the data in other SoCs for the A10, A13 and A20 > for example, or A23/A33, which have a lot of clocks in common too. The interest of your sunxi-ng approach is that the clocks of each SoC is described in one file. Here you are mixing 2 SoCs in the same source file. The advantage is lost. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-07-31 22:30 +0200 |
| Message-ID | <s15wZ-4QP-11@gated-at.bofh.it> |
| In reply to | #1452264 |
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On Fri, Jul 29, 2016 at 07:48:00AM +0200, Jean-Francois Moine wrote: > On Thu, 28 Jul 2016 22:07:05 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > > > Let me know what you think, > > > > > > I don't see the interest to have common code for 32bits and 64bits. > > > The clock driver of a SoC will never evolve, so, it is simpler to > > > copy the source common with the H3 into a clean A64 clock driver. > > > > I'm not sure why 32 bits vs 64 bits matters here. We're going to share > > a significant number of drivers already between armv7 and armv8, like > > MMC, EMAC, I2C, and so on. > > > > And I expect to share the data in other SoCs for the A10, A13 and A20 > > for example, or A23/A33, which have a lot of clocks in common too. > > The interest of your sunxi-ng approach is that the clocks of each SoC > is described in one file. Here you are mixing 2 SoCs in the same source > file. The advantage is lost. Because (and only because) the huge majority of those clocks are shared between these SoCs. If it differs in a significant way (like for the A31 that is currently submitted), there's of course no reason to merge it in the same file. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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| From | André Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-08-01 03:50 +0200 |
| Message-ID | <s1awF-7Zx-1@gated-at.bofh.it> |
| In reply to | #1450873 |
Hi Maxime, On 26/07/16 21:30, Maxime Ripard wrote: > Hi, > > Here is the previous A64 patches made by Andre [1], reworked to use > the new sunxi-ng clock framework. > > This uses the current H3 clock code, as both are really similar. The > first patches are just meant to rework slightly the H3 code, before > introducing the A64-related patches. > > Some WiP stuff have been removed, such as the MMC part, but this serie > already has a decent amount of devices supported: uart, i2c, rsb, etc. Thanks very much for looking into this and compiling this series! In general this looks good to me - apart from the sunxi-ng clock usage. I think I have some small fixes to the DT (have to compare against my latest local branch), I will comment on this later. As I think I never officially expressed my concerns about the new sunxi clock system, so I use that opportunity here ;-) As this became quite a long read, here a TL;DR: - We consider using an SCPI based clock system for the A64, alongside allwinner,simple-gates and fixed clocks. We try to avoid any Allwinner specific clocks (apart from the simple-gates). - ARM Trusted Firmware provides the SCPI implementation - for now, later we may move this into a possible arisc firmware. - We upstream some basic DT first, possibly omitting any controversial clock parts at all. Let me know what you think! Now the long part .... Basically I see those issues with the new clocks: - sunxi-ng requires a complicated SoC specific source file in the kernel. Although that makes the DT pretty easy (and avoids breaking it the future), it ultimately requires an explicit code drop for every new SoC, even if they share 95% of the clocks (as H3 and A64 do, for instance). - This code file does not actually contain any code, instead it's just data and looks like it should really be presented in DT - which brings us back to something like the old sunxi clock scheme, which is apparently not considered good enough. I still wonder if we could create a generic sunxi-ng user, which explains the needed clocks in the DT instead of in code. I admit that looks like quite some work. - It makes it quite hard for any other DT user (*BSD, U-Boot) to use the clocks, since they would have to copy quite verbatim the Linux implementation choice. This is admittedly also true for the old clock framework, but still unfortunate. So as mentioned several times before, I am looking into a more firmware driven clock system using the SCPI[1] framework. The idea is: - The basic clocks (OSC24M, OSC32K, AHB1, APB1, APB2, PERIPH0) are expressed as fixed clocks. If I am not mistaken, Allwinner recommends certain frequencies for them anyway, so we just use that and set them up before booting Linux, for instance in ATF. - The gates clocks are expressed as before, but by defining a generic DT compatible fallback name. I have no idea why every SoC enters its name into the simple_gates.c source file, while just mentioning the compatible string in the DT bindings and using the SoC specific name together with a generic fallback like "allwinner,sunxi-simple-gates" would suffice. This means that we don't need to touch simple-gates.c anymore most of the time. - Any clock that can (and has to) be programmed with a variable frequency is expressed as an SCPI clock. This interface allows basically querying and setting a frequency - not very powerful, but sufficient for the clocks I checked. Firmware then takes the burden of programming the respective clock register - which is not rocket science if we lock the base clocks to a certain frequency. The advantage of this approach would be: - The impact to Linux code is minimized. Normally there would be no need to touch the kernel at all when we introduce a new SoC. - Any other DT user can quite easily make use of the clock system without adding tons of complicated Allwinner specific clock code. The simple-gates driver is almost trivial to implement, and chances are SCPI is already around anyway. - If there are any peculiarities with a certain clock (implementation), we can solve this in firmware. Fixes to code would immediately benefit all users - existing kernels (from distributions), newer kernels and other OSes. - Having SCPI gives us simple regulators and sensors (temperature, power) for free (in terms of no Linux code required). It also allows for DVFS support, though this may require more work on the firmware side. - This approach matches many of the more serious ARM64 machines out there, which refrain from exposing all of their clock framework to Linux. Also this opens the door to much easier support for new SoCs - up to a point where any new chip would actually run out of the box on existing distributions (thinking of LTS releases here). The pinctrl driver is a nasty guy around here - but let's not make it worse and try to fix that guy later ;-) So I managed to finish a first prototype this weekend. SCPI requires a mailbox and a shared memory region to work. The latter is trivial, but we are lacking a proper mailbox driver for sunxi. Besides that the Allwinner mailbox only works between the arisc and the ARM cores, not between ARM cores or within one core in different exception levels. So signalling a mailbox in EL1 and taking the IRQ in EL3 does not work. As a quick solution I implemented a synchronous "smc" mailbox, which uses the ARM smc instruction to transfer control into firmware. Firmware then reads the payload from the shared memory region, handles the request and returns to EL1. We then advertise this mailbox in the SCPI DT node, and the rest of the SCPI framework can happily work with that. I described the clocks as mentioned above and put the MMC clocks under SCPI control. I put a draft DT here [2] to illustrate my ideas. I know this is quite controversial, so what about these following steps: - I polish my existing patches and send a prototype this week. We can then discuss the merits and drawbacks of this approach based on the code. - It it turns out that sunxi-ng is the way to go, I will test and comment on this series. - If we are not sure yet, we can try to go with an almost clock-less DT for now (drop I2C and make UART0 use osc24M directly, for a start). This would leave the door open for either approach. Or we use the simple-gates only for now. I am happy to discuss this here on the list. Cheers, Andre [1] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922g/scp_message_interface_v1_2_DUI0922G_en.pdf [2] https://gist.github.com/apritzel/faa3dc5cbe7591be8c55a439f725578e > > Let me know what you think, > Maxime > > 1: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/410338.html > > Andre Przywara (5): > arm64: sunxi: Kconfig: add essential pinctrl driver > arm64: Kconfig: sunxi: add PINCTRL > Documentation: devicetree: add vendor prefix for Pine64 > arm64: dts: add Allwinner A64 SoC .dtsi > arm64: dts: add Pine64 support > > Maxime Ripard (8): > clk: sunxi-ng: mux: Rename mux macro to be consistent > clk: sunxi-ng: mux: Add mux table support > clk: sunxi-ng: sun8i: Rename DDR and video plls > clk: sunxi-ng: sun8i: Fix register offset > clk: sunxi-ng: sun8i: Rename H3 only clocks > clk: sunxi-ng: sun8i: Move fixed factors around > clk: sunxi-ng: sun8i: Prefix clock defines by SoC Name > clk: sunxi-ng: Add A64 clocks > > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + > .../devicetree/bindings/vendor-prefixes.txt | 1 + > MAINTAINERS | 1 + > arch/arm/boot/dts/sun8i-h3.dtsi | 62 +- > arch/arm64/Kconfig.platforms | 2 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/allwinner/Makefile | 5 + > .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++ > .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++ > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 273 +++++++ > drivers/clk/sunxi-ng/Kconfig | 13 +- > drivers/clk/sunxi-ng/Makefile | 2 +- > drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 896 ++++++++++++++++----- > drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 44 +- > drivers/clk/sunxi-ng/ccu_div.h | 2 +- > drivers/clk/sunxi-ng/ccu_mp.h | 2 +- > drivers/clk/sunxi-ng/ccu_mux.c | 14 + > drivers/clk/sunxi-ng/ccu_mux.h | 29 +- > include/dt-bindings/clock/sun50i-a64-ccu.h | 132 +++ > include/dt-bindings/clock/sun8i-h3-ccu.h | 188 ++--- > include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ > 23 files changed, 1588 insertions(+), 366 deletions(-) > create mode 100644 arch/arm64/boot/dts/allwinner/Makefile > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h > create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h > create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h >
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| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-08-01 10:40 +0200 |
| Message-ID | <s1gVs-3TO-7@gated-at.bofh.it> |
| In reply to | #1452929 |
On Mon, 1 Aug 2016 02:43:06 +0100 André Przywara <andre.przywara@arm.com> wrote: > As this became quite a long read, here a TL;DR: > - We consider using an SCPI based clock system for the A64, alongside > allwinner,simple-gates and fixed clocks. We try to avoid any Allwinner > specific clocks (apart from the simple-gates). > - ARM Trusted Firmware provides the SCPI implementation - for now, later > we may move this into a possible arisc firmware. > - We upstream some basic DT first, possibly omitting any controversial > clock parts at all. > > Let me know what you think! Hi André, This looks interesting. As I understand, the clock enable/rate setting functions would be in the arisc. The arisc firmware would be loaded only once in the Soc and would contain the code for handling this specific SoC. From my calculations, this would save about 1Mb of clock descriptions in the kernel for a universal Allwinner kernel. But I don't see why you are keeping the simple-gates. The bus gate may be ungated/gated when the clock is enabled/disabled, and that's what Allwinner's software does. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-08-01 11:20 +0200 |
| Message-ID | <s1hy9-4ou-19@gated-at.bofh.it> |
| In reply to | #1453037 |
On Mon, Aug 1, 2016 at 4:30 PM, Jean-Francois Moine <moinejf@free.fr> wrote: > On Mon, 1 Aug 2016 02:43:06 +0100 > André Przywara <andre.przywara@arm.com> wrote: > >> As this became quite a long read, here a TL;DR: >> - We consider using an SCPI based clock system for the A64, alongside >> allwinner,simple-gates and fixed clocks. We try to avoid any Allwinner >> specific clocks (apart from the simple-gates). >> - ARM Trusted Firmware provides the SCPI implementation - for now, later >> we may move this into a possible arisc firmware. >> - We upstream some basic DT first, possibly omitting any controversial >> clock parts at all. >> >> Let me know what you think! > > Hi André, > > This looks interesting. > As I understand, the clock enable/rate setting functions would be in > the arisc. The arisc firmware would be loaded only once in the Soc and > would contain the code for handling this specific SoC. > From my calculations, this would save about 1Mb of clock descriptions > in the kernel for a universal Allwinner kernel. > > But I don't see why you are keeping the simple-gates. The bus gate may > be ungated/gated when the clock is enabled/disabled, and that's what > Allwinner's software does. For peripherals that have a separate mod clock, having them separate is a good thing. One example might be the audio codecs. You could ungate the bus gate to access its registers to program it, but only enable the mod clock when you actually play something. Regards ChenYu
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| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-08-01 14:10 +0200 |
| Message-ID | <s1kcG-68q-27@gated-at.bofh.it> |
| In reply to | #1453055 |
On Mon, 1 Aug 2016 17:13:34 +0800 Chen-Yu Tsai <wens@csie.org> wrote: > > But I don't see why you are keeping the simple-gates. The bus gate may > > be ungated/gated when the clock is enabled/disabled, and that's what > > Allwinner's software does. > > For peripherals that have a separate mod clock, having them separate > is a good thing. One example might be the audio codecs. You could ungate > the bus gate to access its registers to program it, but only enable > the mod clock when you actually play something. The roles of the bus gate and the clock gate are the same. I don't see any reason to set one gate without setting the other one. More, the spec says what the bus gate must be enabled before the clock gate (and reverse order while disabling). So, setting both gates in one function call seems safer. Then, if you want to save some power while not playing anything, just do clk_disable() of the (main and only) i2s clock. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-08-01 14:10 +0200 |
| Message-ID | <s1kcG-68q-37@gated-at.bofh.it> |
| In reply to | #1453167 |
On Mon, Aug 1, 2016 at 8:00 PM, Jean-Francois Moine <moinejf@free.fr> wrote: > On Mon, 1 Aug 2016 17:13:34 +0800 > Chen-Yu Tsai <wens@csie.org> wrote: > >> > But I don't see why you are keeping the simple-gates. The bus gate may >> > be ungated/gated when the clock is enabled/disabled, and that's what >> > Allwinner's software does. >> >> For peripherals that have a separate mod clock, having them separate >> is a good thing. One example might be the audio codecs. You could ungate >> the bus gate to access its registers to program it, but only enable >> the mod clock when you actually play something. > > The roles of the bus gate and the clock gate are the same. I don't see > any reason to set one gate without setting the other one. More, the > spec says what the bus gate must be enabled before the clock gate (and > reverse order while disabling). So, setting both gates in one function > call seems safer. Wha? Aren't bus gates and clock gates the same thing in this context? ChenYu > Then, if you want to save some power while not playing anything, just do > clk_disable() of the (main and only) i2s clock. > > -- > Ken ar c'hentañ | ** Breizh ha Linux atav! ** > Jef | http://moinejf.free.fr/
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| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-08-01 14:20 +0200 |
| Message-ID | <s1kmm-6cP-11@gated-at.bofh.it> |
| In reply to | #1453168 |
On Mon, 1 Aug 2016 20:01:49 +0800 Chen-Yu Tsai <wens@csie.org> wrote: > On Mon, Aug 1, 2016 at 8:00 PM, Jean-Francois Moine <moinejf@free.fr> wrote: > > On Mon, 1 Aug 2016 17:13:34 +0800 > > Chen-Yu Tsai <wens@csie.org> wrote: > > > >> > But I don't see why you are keeping the simple-gates. The bus gate may > >> > be ungated/gated when the clock is enabled/disabled, and that's what > >> > Allwinner's software does. > >> > >> For peripherals that have a separate mod clock, having them separate > >> is a good thing. One example might be the audio codecs. You could ungate > >> the bus gate to access its registers to program it, but only enable > >> the mod clock when you actually play something. > > > > The roles of the bus gate and the clock gate are the same. I don't see > > any reason to set one gate without setting the other one. More, the > > spec says what the bus gate must be enabled before the clock gate (and > > reverse order while disabling). So, setting both gates in one function > > call seems safer. > > Wha? Aren't bus gates and clock gates the same thing in this context? Yes. What is the problem? -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-08-01 12:50 +0200 |
| Message-ID | <s1iXf-5ai-9@gated-at.bofh.it> |
| In reply to | #1453037 |
Hi Jean-Francois, On 01/08/16 09:30, Jean-Francois Moine wrote: > On Mon, 1 Aug 2016 02:43:06 +0100 > André Przywara <andre.przywara@arm.com> wrote: > >> As this became quite a long read, here a TL;DR: >> - We consider using an SCPI based clock system for the A64, alongside >> allwinner,simple-gates and fixed clocks. We try to avoid any Allwinner >> specific clocks (apart from the simple-gates). >> - ARM Trusted Firmware provides the SCPI implementation - for now, later >> we may move this into a possible arisc firmware. >> - We upstream some basic DT first, possibly omitting any controversial >> clock parts at all. >> >> Let me know what you think! > > Hi André, > > This looks interesting. > As I understand, the clock enable/rate setting functions would be in > the arisc. The arisc firmware would be loaded only once in the Soc and > would contain the code for handling this specific SoC. > From my calculations, this would save about 1Mb of clock descriptions > in the kernel for a universal Allwinner kernel. This is the rough idea, yes. In the moment the clock code sits in the ARM Trusted Firmware part, but in fact this is an implementation detail. Theoretically we could also move that clock code to U-Boot on 32-bit SoCs to sit next to the PSCI implementation, which uses the same smc call mechanism as I do in this first implementation. But unfortunately we cannot remove the existing code from the kernel, since that would break all existing users (unless they upgrade their firmware). So I am not sure if supporting older SoCs with this mechanism is worthwhile. But: yes, I want to avoid adding tedious clock descriptions for each and every new SoC to the kernel. What really worries me is that sunxi-ng makes this situation probably worse, as we now have to add SoC specific "code" (in fact: clock descriptions) for every SoC, even if that chip doesn't introduce any new clock type. > But I don't see why you are keeping the simple-gates. The bus gate may > be ungated/gated when the clock is enabled/disabled, and that's what > Allwinner's software does. We could do. But SCPI does not have an explicit enable/disable interface, it only describes that setting the frequency to 0 disables the clock. For enabling it one would have to set some frequency (!= 0), which the firmware could then translate into a "set that bit in the gate register" for any gate-only clock, which sounds rather hackish to me. Also it would require to alter the SCPI clock driver to implement the enable/disable ops, since I think we never call set_rate for those clocks. So having the quite straight forward "simple-gates" driver around seems more sane. In the end this driver just translates "clock number x" into "bit number x" in that register, which is very generic. That's why I urged to introduce a fallback compatible name to express this very feature. Cheers, Andre.
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