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[PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

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  [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-06 17:20 +0200
    [PATCH v5 01/11] dmaengine: dw: keep copy of custom slave config in dwc Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-06 17:30 +0200
    [PATCH v5 04/11] dmaengine: dw: override LLP support if asked in platform data Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-06 17:30 +0200
    Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-12 17:10 +0200
      Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Vinod Koul <vinod.koul@intel.com> - 2016-05-12 18:00 +0200
      Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Bryan O'Donoghue <pure.logic@nexus-software.ie> - 2016-05-19 03:20 +0200
        Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-24 19:40 +0200
          Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-05-24 20:10 +0200
            Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Bryan O'Donoghue <pure.logic@nexus-software.ie> - 2016-05-26 18:40 +0200
          Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable  DMA on Quark Bryan O'Donoghue <pure.logic@nexus-software.ie> - 2016-05-26 18:20 +0200

#1395934 — [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

This is combined series of two things:
- split out the Intel LPSS specific driver from 8250_pci into 8250_lpss
- enable DMA support on Intel Quark UART

The patch has been tested on few Intel SoCs / platforms. In any case I would
like to ask Bryan to do independent test.

This is targeting serial subsystem, thus it would be nice to get and Ack from
Vinod first. Moreover, the series depends on [1] that is now in Vinod's
slave-dma tree.

That's why I asked Vinod to create immutable tag / branch for the [1] and the
dependants (at least one more, which is sata_dwc_460ex) can use it.

The series can be reached in the branch located at [2].

[1] http://www.spinics.net/lists/kernel/msg2244475.html
[2] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fqrk

Since v4:
- fix an issue what kernel test bot reported (lkp)
- add a list of supported SoC to Kconfig (Bryan)
- rename polarity -> hs_polarity (Bryan)

Since v3:
- rebase on top of recent tty-next branch
- add Reviewed-by tag from Bryan

Since v2:
- add tags
- rebase on top of new version of [1]

Since v1:
- address most of Peter's comments (mostly changelog to patch 8)
- add tag to patch 5
- drop patch 6 from the series to be separately dealt with

Andy Shevchenko (11):
  dmaengine: dw: keep copy of custom slave config in dwc
  dmaengine: dw: provide probe(), remove() stubs for users
  dmaengine: dw: set polarity of handshake interface
  dmaengine: dw: override LLP support if asked in platform data
  serial: 8250_dma: switch to new dmaengine_terminate_* API
  serial: 8250_dma: adjust DMA address of the UART
  serial: 8250: enable AFE on ports where FIFO is 16 bytes
  serial: 8250_lpss: split LPSS driver to separate module
  serial: 8250_lpss: move Quark code from PCI driver
  serial: 8250_lpss: enable MSI for Intel Quark
  serial: 8250_lpss: enable DMA on Intel Quark UART

 drivers/dma/dw/core.c                |  43 +++--
 drivers/dma/dw/regs.h                |   5 +-
 drivers/tty/serial/8250/8250.h       |   5 +
 drivers/tty/serial/8250/8250_dma.c   |  14 +-
 drivers/tty/serial/8250/8250_lpss.c  | 357 +++++++++++++++++++++++++++++++++++
 drivers/tty/serial/8250/8250_pci.c   | 257 +------------------------
 drivers/tty/serial/8250/8250_port.c  |   9 +-
 drivers/tty/serial/8250/Kconfig      |  16 +-
 drivers/tty/serial/8250/Makefile     |   1 +
 include/linux/dma/dw.h               |   5 +
 include/linux/platform_data/dma-dw.h |   4 +
 11 files changed, 430 insertions(+), 286 deletions(-)
 create mode 100644 drivers/tty/serial/8250/8250_lpss.c

-- 
2.8.1

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#1395939 — [PATCH v5 01/11] dmaengine: dw: keep copy of custom slave config in dwc

It seems we need to extend custom slave configuration by one more member to
support Intel Quart UART. It becomes a burden to manage all members of struct
dw_dma_slave one-by-one.

Replace set of fields by embedding struct dw_dma_slave into struct dw_dma_chan.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/dw/core.c | 29 ++++++++++-------------------
 drivers/dma/dw/regs.h |  5 +----
 2 files changed, 11 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index edf053f..81b06df 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -46,9 +46,9 @@
 		u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :	\
 			DW_DMA_MSIZE_16;			\
 		u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ?		\
-			_dwc->p_master : _dwc->m_master;		\
+			_dwc->dws.p_master : _dwc->dws.m_master;	\
 		u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ?		\
-			_dwc->p_master : _dwc->m_master;		\
+			_dwc->dws.p_master : _dwc->dws.m_master;	\
 								\
 		(DWC_CTLL_DST_MSIZE(_dmsize)			\
 		 | DWC_CTLL_SRC_MSIZE(_smsize)			\
@@ -147,8 +147,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
 	if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
 		return;
 
-	cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
-	cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
+	cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
+	cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
 
 	channel_writel(dwc, CFG_LO, cfglo);
 	channel_writel(dwc, CFG_HI, cfghi);
@@ -209,7 +209,7 @@ static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 {
 	struct dw_dma	*dw = to_dw_dma(dwc->chan.device);
-	u8		lms = DWC_LLP_LMS(dwc->m_master);
+	u8		lms = DWC_LLP_LMS(dwc->dws.m_master);
 	unsigned long	was_soft_llp;
 
 	/* ASSERT:  channel is idle */
@@ -662,7 +662,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 	struct dw_desc		*prev;
 	size_t			xfer_count;
 	size_t			offset;
-	u8			m_master = dwc->m_master;
+	u8			m_master = dwc->dws.m_master;
 	unsigned int		src_width;
 	unsigned int		dst_width;
 	unsigned int		data_width = dw->pdata->data_width[m_master];
@@ -740,7 +740,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	struct dw_desc		*prev;
 	struct dw_desc		*first;
 	u32			ctllo;
-	u8			m_master = dwc->m_master;
+	u8			m_master = dwc->dws.m_master;
 	u8			lms = DWC_LLP_LMS(m_master);
 	dma_addr_t		reg;
 	unsigned int		reg_width;
@@ -895,12 +895,7 @@ bool dw_dma_filter(struct dma_chan *chan, void *param)
 		return false;
 
 	/* We have to copy data since dws can be temporary storage */
-
-	dwc->src_id = dws->src_id;
-	dwc->dst_id = dws->dst_id;
-
-	dwc->m_master = dws->m_master;
-	dwc->p_master = dws->p_master;
+	memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
 
 	return true;
 }
@@ -1167,11 +1162,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&dwc->lock, flags);
 
 	/* Clear custom channel configuration */
-	dwc->src_id = 0;
-	dwc->dst_id = 0;
-
-	dwc->m_master = 0;
-	dwc->p_master = 0;
+	memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
 
 	clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
 
@@ -1264,7 +1255,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
 	struct dw_cyclic_desc		*retval = NULL;
 	struct dw_desc			*desc;
 	struct dw_desc			*last = NULL;
-	u8				lms = DWC_LLP_LMS(dwc->m_master);
+	u8				lms = DWC_LLP_LMS(dwc->dws.m_master);
 	unsigned long			was_cyclic;
 	unsigned int			reg_width;
 	unsigned int			periods;
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 4b7bd78..f65dd10 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -245,10 +245,7 @@ struct dw_dma_chan {
 	bool			nollp;
 
 	/* custom slave configuration */
-	u8			src_id;
-	u8			dst_id;
-	u8			m_master;
-	u8			p_master;
+	struct dw_dma_slave	dws;
 
 	/* configuration passed via .device_config */
 	struct dma_slave_config dma_sconfig;
-- 
2.8.1

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#1395940 — [PATCH v5 04/11] dmaengine: dw: override LLP support if asked in platform data

There is at least one known device, i.e. UART on Intel Galileo, that works
unreliably in case of use of multi block transfer support in DMA mode.

Override autodetection by user provided data.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/dw/core.c                | 10 +++++++---
 include/linux/platform_data/dma-dw.h |  2 ++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 59f571c..d2d1d51 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1573,9 +1573,13 @@ int dw_dma_probe(struct dw_dma_chip *chip)
 			dwc->block_size = pdata->block_size;
 
 			/* Check if channel supports multi block transfer */
-			channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
-			dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
-			channel_writel(dwc, LLP, 0);
+			if (pdata->is_nollp) {
+				dwc->nollp = pdata->is_nollp;
+			} else {
+				channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
+				dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
+				channel_writel(dwc, LLP, 0);
+			}
 		}
 	}
 
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 4636c93..5f0e11e 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -40,6 +40,7 @@ struct dw_dma_slave {
  * @is_private: The device channels should be marked as private and not for
  *	by the general purpose DMA channel allocator.
  * @is_memcpy: The device channels do support memory-to-memory transfers.
+ * @is_nollp: The device channels does not support multi block transfers.
  * @chan_allocation_order: Allocate channels starting from 0 or 7
  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  * @block_size: Maximum block size supported by the controller
@@ -51,6 +52,7 @@ struct dw_dma_platform_data {
 	unsigned int	nr_channels;
 	bool		is_private;
 	bool		is_memcpy;
+	bool		is_nollp;
 #define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
 #define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */
 	unsigned char	chan_allocation_order;
-- 
2.8.1

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#1400137 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> This is combined series of two things:
> - split out the Intel LPSS specific driver from 8250_pci into
> 8250_lpss
> - enable DMA support on Intel Quark UART
> 
> The patch has been tested on few Intel SoCs / platforms. In any case I
> would
> like to ask Bryan to do independent test.
> 
> This is targeting serial subsystem, thus it would be nice to get and
> Ack from
> Vinod first. Moreover, the series depends on [1] that is now in
> Vinod's
> slave-dma tree.
> 
> That's why I asked Vinod to create immutable tag / branch for the [1]
> and the
> dependants (at least one more, which is sata_dwc_460ex) can use it.
> 
> The series can be reached in the branch located at [2].
> 
> [1] http://www.spinics.net/lists/kernel/msg2244475.html
> [2] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fqrk
> 

Do we have a chance to get this? Requirement, i.e. topic/dw branch of
Vinod's slave-dma tree is available and has all prerequisites.

> Since v4:
> - fix an issue what kernel test bot reported (lkp)
> - add a list of supported SoC to Kconfig (Bryan)
> - rename polarity -> hs_polarity (Bryan)
> 
> Since v3:
> - rebase on top of recent tty-next branch
> - add Reviewed-by tag from Bryan
> 
> Since v2:
> - add tags
> - rebase on top of new version of [1]
> 
> Since v1:
> - address most of Peter's comments (mostly changelog to patch 8)
> - add tag to patch 5
> - drop patch 6 from the series to be separately dealt with
> 
> Andy Shevchenko (11):
>   dmaengine: dw: keep copy of custom slave config in dwc
>   dmaengine: dw: provide probe(), remove() stubs for users
>   dmaengine: dw: set polarity of handshake interface
>   dmaengine: dw: override LLP support if asked in platform data
>   serial: 8250_dma: switch to new dmaengine_terminate_* API
>   serial: 8250_dma: adjust DMA address of the UART
>   serial: 8250: enable AFE on ports where FIFO is 16 bytes
>   serial: 8250_lpss: split LPSS driver to separate module
>   serial: 8250_lpss: move Quark code from PCI driver
>   serial: 8250_lpss: enable MSI for Intel Quark
>   serial: 8250_lpss: enable DMA on Intel Quark UART
> 
>  drivers/dma/dw/core.c                |  43 +++--
>  drivers/dma/dw/regs.h                |   5 +-
>  drivers/tty/serial/8250/8250.h       |   5 +
>  drivers/tty/serial/8250/8250_dma.c   |  14 +-
>  drivers/tty/serial/8250/8250_lpss.c  | 357
> +++++++++++++++++++++++++++++++++++
>  drivers/tty/serial/8250/8250_pci.c   | 257 +------------------------
>  drivers/tty/serial/8250/8250_port.c  |   9 +-
>  drivers/tty/serial/8250/Kconfig      |  16 +-
>  drivers/tty/serial/8250/Makefile     |   1 +
>  include/linux/dma/dw.h               |   5 +
>  include/linux/platform_data/dma-dw.h |   4 +
>  11 files changed, 430 insertions(+), 286 deletions(-)
>  create mode 100644 drivers/tty/serial/8250/8250_lpss.c
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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#1400200 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Thu, May 12, 2016 at 06:06:41PM +0300, Andy Shevchenko wrote:
> On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> > This is combined series of two things:
> > - split out the Intel LPSS specific driver from 8250_pci into
> > 8250_lpss
> > - enable DMA support on Intel Quark UART
> > 
> > The patch has been tested on few Intel SoCs / platforms. In any case I
> > would
> > like to ask Bryan to do independent test.
> > 
> > This is targeting serial subsystem, thus it would be nice to get and
> > Ack from
> > Vinod first. Moreover, the series depends on [1] that is now in
> > Vinod's
> > slave-dma tree.
> > 
> > That's why I asked Vinod to create immutable tag / branch for the [1]
> > and the
> > dependants (at least one more, which is sata_dwc_460ex) can use it.
> > 
> > The series can be reached in the branch located at [2].
> > 
> > [1] http://www.spinics.net/lists/kernel/msg2244475.html
> > [2] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fqrk
> > 
> 
> Do we have a chance to get this? Requirement, i.e. topic/dw branch of
> Vinod's slave-dma tree is available and has all prerequisites.

All dmaengine patches

Acked-by: Vinod Koul <vinod.koul@intel.com>

Thanks
-- 
~Vinod

> 
> > Since v4:
> > - fix an issue what kernel test bot reported (lkp)
> > - add a list of supported SoC to Kconfig (Bryan)
> > - rename polarity -> hs_polarity (Bryan)
> > 
> > Since v3:
> > - rebase on top of recent tty-next branch
> > - add Reviewed-by tag from Bryan
> > 
> > Since v2:
> > - add tags
> > - rebase on top of new version of [1]
> > 
> > Since v1:
> > - address most of Peter's comments (mostly changelog to patch 8)
> > - add tag to patch 5
> > - drop patch 6 from the series to be separately dealt with
> > 
> > Andy Shevchenko (11):
> >   dmaengine: dw: keep copy of custom slave config in dwc
> >   dmaengine: dw: provide probe(), remove() stubs for users
> >   dmaengine: dw: set polarity of handshake interface
> >   dmaengine: dw: override LLP support if asked in platform data
> >   serial: 8250_dma: switch to new dmaengine_terminate_* API
> >   serial: 8250_dma: adjust DMA address of the UART
> >   serial: 8250: enable AFE on ports where FIFO is 16 bytes
> >   serial: 8250_lpss: split LPSS driver to separate module
> >   serial: 8250_lpss: move Quark code from PCI driver
> >   serial: 8250_lpss: enable MSI for Intel Quark
> >   serial: 8250_lpss: enable DMA on Intel Quark UART
> > 
> >  drivers/dma/dw/core.c                |  43 +++--
> >  drivers/dma/dw/regs.h                |   5 +-
> >  drivers/tty/serial/8250/8250.h       |   5 +
> >  drivers/tty/serial/8250/8250_dma.c   |  14 +-
> >  drivers/tty/serial/8250/8250_lpss.c  | 357
> > +++++++++++++++++++++++++++++++++++
> >  drivers/tty/serial/8250/8250_pci.c   | 257 +------------------------
> >  drivers/tty/serial/8250/8250_port.c  |   9 +-
> >  drivers/tty/serial/8250/Kconfig      |  16 +-
> >  drivers/tty/serial/8250/Makefile     |   1 +
> >  include/linux/dma/dw.h               |   5 +
> >  include/linux/platform_data/dma-dw.h |   4 +
> >  11 files changed, 430 insertions(+), 286 deletions(-)
> >  create mode 100644 drivers/tty/serial/8250/8250_lpss.c
> > 
> 
> -- 
> Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Intel Finland Oy
> 

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#1403379 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Thu, 2016-05-12 at 18:06 +0300, Andy Shevchenko wrote:
> On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> > This is combined series of two things:
> > - split out the Intel LPSS specific driver from 8250_pci into
> > 8250_lpss
> > - enable DMA support on Intel Quark UART
> > 
> > The patch has been tested on few Intel SoCs / platforms. In any
> > case I
> > would
> > like to ask Bryan to do independent test.

Andy.

It looks as though there's a performance drop when enabling the DMA
here (v) stock PIO mode with the 8250 driver.

Test setup Galileo Gen1 transmitter - Galileo Gen2 receiver. TX/RX
cross-wired between the Arduino UART headers respectively (pins 0 & 1
on the "Digital PWM" header), GND pin14 similarly cross-wired.

User-space:
    Receiver: Stock on-flash yocto-tiny kernel 3.8.7
    Transmitter: Galileo Debian image :
                 https://sourceforge.net/projects/galileodebian/
    3.8.7 kernel: On SPI-flash BSP kernel
    andy-v4: From your tree
             d13ffcf ('serial: 8250: attempt to keep Kconfig and
                       Makefile in order')
    tip-of-tree : 97f0090 ('Merge tag 'rproc-v4.7' of
                            git://github.com/andersson/remoteproc')

Results:

### Test0 ###

galileo dma andy-v4 9600 8n1 

root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
/dev/ttyS0

real    0m0.060s
user    0m0.000s
sys     0m0.000s


galileo non-dma Linux 3.8.7 9600 8n1:

9600 8n1
root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
/dev/ttyS0

real    0m0.051s
user    0m0.000s
sys     0m0.000s

galileo non-dma tip-of-tree 9600 8n1:

root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
/dev/ttyS0

real    0m0.048s
user    0m0.000s
sys     0m0.000s


### Test1 ###

galileo dma andy-v4 9600 8n1:

root@galileo:~# time echo
"abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234567
89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0

real    0m0.209s
user    0m0.000s
sys     0m0.000s

galileo non-dma Linux 3.8.7 9600 8n1:

root@galileo:~# time echo
"abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234567
89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0

real    0m0.206s
user    0m0.000s
sys     0m0.000s


galileo non-dma tip-of-tree 9600 8n1:

root@galileo:~# time echo
"abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234567
89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0

real    0m0.199s
user    0m0.010s
sys     0m0.000s


---
bod

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#1406305 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Thu, 2016-05-19 at 02:18 +0100, Bryan O'Donoghue wrote:
> On Thu, 2016-05-12 at 18:06 +0300, Andy Shevchenko wrote:
> > On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> > > This is combined series of two things:
> > > - split out the Intel LPSS specific driver from 8250_pci into
> > > 8250_lpss
> > > - enable DMA support on Intel Quark UART
> > > 
> > > The patch has been tested on few Intel SoCs / platforms. In any
> > > case I
> > > would
> > > like to ask Bryan to do independent test.
> 
> Andy.
> 
> It looks as though there's a performance drop when enabling the DMA
> here (v) stock PIO mode with the 8250 driver.

Below results doesn't show DMA case (by the way, how did you disable DMA
in 3.8.7?) for stock kernel.

Anyway, I added preliminary support to change DMA mode run-time. Check
my today topic/dw/qrk branch. It would be nice to see all 4 cases: DMA
vs non-DMA on stock kernel (Yocto) and mine.

P.S. What is the point to test arbitrary tip branch?

> 
> Test setup Galileo Gen1 transmitter - Galileo Gen2 receiver. TX/RX
> cross-wired between the Arduino UART headers respectively (pins 0 & 1
> on the "Digital PWM" header), GND pin14 similarly cross-wired.
> 
> User-space:
>     Receiver: Stock on-flash yocto-tiny kernel 3.8.7
>     Transmitter: Galileo Debian image :
>                  https://sourceforge.net/projects/galileodebian/
>     3.8.7 kernel: On SPI-flash BSP kernel
>     andy-v4: From your tree
>              d13ffcf ('serial: 8250: attempt to keep Kconfig and
>                        Makefile in order')
>     tip-of-tree : 97f0090 ('Merge tag 'rproc-v4.7' of
>                             git://github.com/andersson/remoteproc')
> 
> Results:
> 
> ### Test0 ###
> 
> galileo dma andy-v4 9600 8n1 
> 
> root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> /dev/ttyS0
> 
> real    0m0.060s
> user    0m0.000s
> sys     0m0.000s
> 
> 
> galileo non-dma Linux 3.8.7 9600 8n1:
> 
> 9600 8n1
> root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> /dev/ttyS0
> 
> real    0m0.051s
> user    0m0.000s
> sys     0m0.000s
> 
> galileo non-dma tip-of-tree 9600 8n1:
> 
> root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> /dev/ttyS0
> 
> real    0m0.048s
> user    0m0.000s
> sys     0m0.000s
> 
> 
> ### Test1 ###
> 
> galileo dma andy-v4 9600 8n1:
> 
> root@galileo:~# time echo
> "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
> 7
> 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz012345
> 6
> 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> 
> real    0m0.209s
> user    0m0.000s
> sys     0m0.000s
> 
> galileo non-dma Linux 3.8.7 9600 8n1:
> 
> root@galileo:~# time echo
> "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
> 7
> 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz012345
> 6
> 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> 
> real    0m0.206s
> user    0m0.000s
> sys     0m0.000s
> 
> 
> galileo non-dma tip-of-tree 9600 8n1:
> 
> root@galileo:~# time echo
> "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123456
> 7
> 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz012345
> 6
> 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> 
> real    0m0.199s
> user    0m0.010s
> sys     0m0.000s
> 
> 
> ---
> bod

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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#1406345 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Tue, 2016-05-24 at 20:37 +0300, Andy Shevchenko wrote:
> On Thu, 2016-05-19 at 02:18 +0100, Bryan O'Donoghue wrote:
> > On Thu, 2016-05-12 at 18:06 +0300, Andy Shevchenko wrote:
> > > On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> > > > This is combined series of two things:
> > > > - split out the Intel LPSS specific driver from 8250_pci into
> > > > 8250_lpss
> > > > - enable DMA support on Intel Quark UART
> > > > 
> > > > The patch has been tested on few Intel SoCs / platforms. In any
> > > > case I
> > > > would
> > > > like to ask Bryan to do independent test.
> > 
> > Andy.
> > 
> > It looks as though there's a performance drop when enabling the DMA
> > here (v) stock PIO mode with the 8250 driver.

Wait, the time measurement you done is unrelated to DMA/non-DMA mode.
It's significantly depend to the speed of the port.

It would be better to have 1000(s) of iterations to see any steady
difference out of statistical error. Below result doesn't show anything
like this.

I also tried on my Galileo board, I used longer data stream, i.e. output
of dmesg (since your data pattern makes 0:s in statistics) and got
something quite near to each other:

###
Size of the data (it actually become few dozens of bytes (55 bytes to be
precise) bigger since one message had been printed in the second part of
high speed test
###

% dmesg | wc -c
34965

### Low speed, DMA mode enabled by default ###
% stty -F /dev/ttyS0 9600

% time dmesg > /dev/ttyS0
real    0m 34.22s
user    0m 0.01s
sys     0m 0.02s

NOTE: Transfer speed: 34965b/34.22s ~= 1021.77b/s (9600 baud)

### non-DMA mode ###
% echo 3 > /sys/class/tty/ttyS0/dma_mode 

% time dmesg > /dev/ttyS0
real    0m 36.09s
user    0m 0.01s
sys     0m 0.02s

### Higher speed ###

% stty -F /dev/ttyS0 921600

% time dmesg > /dev/ttyS0
real    0m 0.41s
user    0m 0.01s
sys     0m 0.03s

NOTE: Transfer speed: 34965b/0.41s ~= 85280.49b/s (921600 baud)

### DMA mode enabled ###
% echo 0 > /sys/class/tty/ttyS0/dma_mode 

% time dmesg > /dev/ttyS0
real    0m 0.41s
user    0m 0.01s
sys     0m 0.02s

> 
> Below results doesn't show DMA case (by the way, how did you disable
> DMA
> in 3.8.7?) for stock kernel.
> 
> Anyway, I added preliminary support to change DMA mode run-time. Check
> my today topic/dw/qrk branch. It would be nice to see all 4 cases: DMA
> vs non-DMA on stock kernel (Yocto) and mine.
> 
> P.S. What is the point to test arbitrary tip branch?
> 
> > 
> > Test setup Galileo Gen1 transmitter - Galileo Gen2 receiver. TX/RX
> > cross-wired between the Arduino UART headers respectively (pins 0 &
> > 1
> > on the "Digital PWM" header), GND pin14 similarly cross-wired.
> > 
> > User-space:
> >     Receiver: Stock on-flash yocto-tiny kernel 3.8.7
> >     Transmitter: Galileo Debian image :
> >                  https://sourceforge.net/projects/galileodebian/
> >     3.8.7 kernel: On SPI-flash BSP kernel
> >     andy-v4: From your tree
> >              d13ffcf ('serial: 8250: attempt to keep Kconfig and
> >                        Makefile in order')
> >     tip-of-tree : 97f0090 ('Merge tag 'rproc-v4.7' of
> >                             git://github.com/andersson/remoteproc')
> > 
> > Results:
> > 
> > ### Test0 ###
> > 
> > galileo dma andy-v4 9600 8n1 
> > 
> > root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> > /dev/ttyS0
> > 
> > real    0m0.060s
> > user    0m0.000s
> > sys     0m0.000s
> > 
> > 
> > galileo non-dma Linux 3.8.7 9600 8n1:
> > 
> > 9600 8n1
> > root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> > /dev/ttyS0
> > 
> > real    0m0.051s
> > user    0m0.000s
> > sys     0m0.000s
> > 
> > galileo non-dma tip-of-tree 9600 8n1:
> > 
> > root@galileo:~# time echo "abcdefghijklmnopqrstuvwxyz0123456789" >
> > /dev/ttyS0
> > 
> > real    0m0.048s
> > user    0m0.000s
> > sys     0m0.000s
> > 
> > 
> > ### Test1 ###
> > 
> > galileo dma andy-v4 9600 8n1:
> > 
> > root@galileo:~# time echo
> > "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234
> > 56
> > 7
> > 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123
> > 45
> > 6
> > 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> > 
> > real    0m0.209s
> > user    0m0.000s
> > sys     0m0.000s
> > 
> > galileo non-dma Linux 3.8.7 9600 8n1:
> > 
> > root@galileo:~# time echo
> > "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234
> > 56
> > 7
> > 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123
> > 45
> > 6
> > 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> > 
> > real    0m0.206s
> > user    0m0.000s
> > sys     0m0.000s
> > 
> > 
> > galileo non-dma tip-of-tree 9600 8n1:
> > 
> > root@galileo:~# time echo
> > "abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz01234
> > 56
> > 7
> > 89abcdefghijklmnopqrstuvwxyz0123456789abcdefghijklmnopqrstuvwxyz0123
> > 45
> > 6
> > 789abcdefghijklmnopqrstuvwxyz0123456789" > /dev/ttyS0
> > 
> > real    0m0.199s
> > user    0m0.010s
> > sys     0m0.000s



-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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#1407632 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Tue, 2016-05-24 at 21:08 +0300, Andy Shevchenko wrote:
> On Tue, 2016-05-24 at 20:37 +0300, Andy Shevchenko wrote:
> > On Thu, 2016-05-19 at 02:18 +0100, Bryan O'Donoghue wrote:
> > > On Thu, 2016-05-12 at 18:06 +0300, Andy Shevchenko wrote:
> > > > On Fri, 2016-05-06 at 18:17 +0300, Andy Shevchenko wrote:
> > > > > This is combined series of two things:
> > > > > - split out the Intel LPSS specific driver from 8250_pci into
> > > > > 8250_lpss
> > > > > - enable DMA support on Intel Quark UART
> > > > > 
> > > > > The patch has been tested on few Intel SoCs / platforms. In
> > > > > any
> > > > > case I
> > > > > would
> > > > > like to ask Bryan to do independent test.
> > > 
> > > Andy.
> > > 
> > > It looks as though there's a performance drop when enabling the
> > > DMA
> > > here (v) stock PIO mode with the 8250 driver.
> 
> Wait, the time measurement you done is unrelated to DMA/non-DMA mode.
> It's significantly depend to the speed of the port.

Does it ? The size of the FIFO is what - 16 bytes ? Max burst size is 8
bytes - so for 37 bytes you'd expect to see five DMA transactions {8,
8, 8, 5}, for the second test 183 bytes you'd expect to see 23 eight
byte transactions followed by one 7 byte transaction. The flip side to
add data to the FIFO in PIO mode is a pretty different pattern.

> I also tried on my Galileo board, I used longer data stream, i.e.
> output
> of dmesg (since your data pattern makes 0:s in statistics) and got
> something quite near to each other:

I'll find some time to look at both a short stream and a long stream,
based on the branch you've indicated and maybe against the latest
stable kernel.

---
bod

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#1407620 — Re: [PATCH v5 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark

On Tue, 2016-05-24 at 20:37 +0300, Andy Shevchenko wrote:
> Below results doesn't show DMA case (by the way, how did you disable
> DMA
> in 3.8.7?) for stock kernel.

The stock kernel on SPI flash for my early Gen1 is a non-DMA 8250
driver, so nothing needs to be done to that, it's basically just the
3.8.7 8250 in PIO mode.

> Anyway, I added preliminary support to change DMA mode run-time.
> Check
> my today topic/dw/qrk branch. It would be nice to see all 4 cases:
> DMA
> vs non-DMA on stock kernel (Yocto) and mine.

I'll have another look at your latest branch and run the same tests.

> 
> P.S. What is the point to test arbitrary tip branch?

Just tip-of-tree, we can benchmark against the 4.6 tag if you prefer.


---
bod

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