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Groups > linux.kernel > #1398057 > unrolled thread
| Started by | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| First post | 2016-05-10 14:50 +0200 |
| Last post | 2016-05-11 21:20 +0200 |
| Articles | 4 — 2 participants |
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Re: [PATCH 00/12] TLB/XPA fixes & cleanups Ralf Baechle <ralf@linux-mips.org> - 2016-05-10 14:50 +0200
Re: [PATCH 00/12] TLB/XPA fixes & cleanups Florian Fainelli <f.fainelli@gmail.com> - 2016-05-10 19:50 +0200
Re: [PATCH 00/12] TLB/XPA fixes & cleanups Ralf Baechle <ralf@linux-mips.org> - 2016-05-11 12:10 +0200
Re: [PATCH 00/12] TLB/XPA fixes & cleanups Florian Fainelli <f.fainelli@gmail.com> - 2016-05-11 21:20 +0200
| From | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Date | 2016-05-10 14:50 +0200 |
| Subject | Re: [PATCH 00/12] TLB/XPA fixes & cleanups |
| Message-ID | <rxfgS-2rD-11@gated-at.bofh.it> |
On Fri, Apr 15, 2016 at 11:36:48AM +0100, Paul Burton wrote:
> This series fixes up a number of issues introduced by commit
> c5b367835cfc ("MIPS: Add support for XPA."), including breakage of the
> MIPS32 with 36 bit physical addressing case & clobbering of $1 upon TLB
> refill exceptions. Along the way a number of cleanups are made, which
> leaves pgtable-bits.h in particular much more readable than before.
>
> The series applies atop v4.6-rc3.
>
> James Hogan (4):
> MIPS: Separate XPA CPU feature into LPA and MVH
> MIPS: Fix HTW config on XPA kernel without LPA enabled
> MIPS: mm: Don't clobber $1 on XPA TLB refill
> MIPS: mm: Don't do MTHC0 if XPA not present
>
> Paul Burton (8):
> MIPS: Remove redundant asm/pgtable-bits.h inclusions
> MIPS: Use enums to make asm/pgtable-bits.h readable
> MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ
> MIPS: mm: Unify pte_page definition
> MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)
> MIPS: mm: Pass scratch register through to iPTE_SW
> MIPS: mm: Be more explicit about PTE mode bit handling
> MIPS: mm: Simplify build_update_entries
Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes
a massive conflict with Florian's RIXI patches
[3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core
[4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe
[5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI
I figured unapplying those three, applying Paul's series then re-applying
Florian's patch on top of the whole series will be the easier path as in
leaving me with the smaller rejects to manage.
Ralf
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| From | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| Date | 2016-05-10 19:50 +0200 |
| Message-ID | <rxjXb-7jo-3@gated-at.bofh.it> |
| In reply to | #1398057 |
On 05/10/2016 05:44 AM, Ralf Baechle wrote:
> On Fri, Apr 15, 2016 at 11:36:48AM +0100, Paul Burton wrote:
>
>> This series fixes up a number of issues introduced by commit
>> c5b367835cfc ("MIPS: Add support for XPA."), including breakage of the
>> MIPS32 with 36 bit physical addressing case & clobbering of $1 upon TLB
>> refill exceptions. Along the way a number of cleanups are made, which
>> leaves pgtable-bits.h in particular much more readable than before.
>>
>> The series applies atop v4.6-rc3.
>>
>> James Hogan (4):
>> MIPS: Separate XPA CPU feature into LPA and MVH
>> MIPS: Fix HTW config on XPA kernel without LPA enabled
>> MIPS: mm: Don't clobber $1 on XPA TLB refill
>> MIPS: mm: Don't do MTHC0 if XPA not present
>>
>> Paul Burton (8):
>> MIPS: Remove redundant asm/pgtable-bits.h inclusions
>> MIPS: Use enums to make asm/pgtable-bits.h readable
>> MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ
>> MIPS: mm: Unify pte_page definition
>> MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)
>> MIPS: mm: Pass scratch register through to iPTE_SW
>> MIPS: mm: Be more explicit about PTE mode bit handling
>> MIPS: mm: Simplify build_update_entries
>
> Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes
> a massive conflict with Florian's RIXI patches
>
> [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core
> [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe
> [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI
>
> I figured unapplying those three, applying Paul's series then re-applying
> Florian's patch on top of the whole series will be the easier path as in
> leaving me with the smaller rejects to manage.
Did you already push that to mips-for-linux-next? I can give it a quick
spin once you do so.
--
Florian
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| From | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Date | 2016-05-11 12:10 +0200 |
| Message-ID | <rxzfz-6aG-7@gated-at.bofh.it> |
| In reply to | #1398355 |
On Tue, May 10, 2016 at 10:47:48AM -0700, Florian Fainelli wrote: > > Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes > > a massive conflict with Florian's RIXI patches > > > > [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core > > [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe > > [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI > > > > I figured unapplying those three, applying Paul's series then re-applying > > Florian's patch on top of the whole series will be the easier path as in > > leaving me with the smaller rejects to manage. > > Did you already push that to mips-for-linux-next? I can give it a quick > spin once you do so. I just pushed a tree with everything applied. HEAD of tree is 22702a86997c5aed2e479bfe0b24d10d66b09604 dated May 11 11:58:06; a version from earlier today was broken. Ralf
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| From | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| Date | 2016-05-11 21:20 +0200 |
| Message-ID | <rxHPQ-6gz-19@gated-at.bofh.it> |
| In reply to | #1398890 |
On 05/11/2016 03:03 AM, Ralf Baechle wrote: > On Tue, May 10, 2016 at 10:47:48AM -0700, Florian Fainelli wrote: > >>> Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes >>> a massive conflict with Florian's RIXI patches >>> >>> [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core >>> [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe >>> [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI >>> >>> I figured unapplying those three, applying Paul's series then re-applying >>> Florian's patch on top of the whole series will be the easier path as in >>> leaving me with the smaller rejects to manage. >> >> Did you already push that to mips-for-linux-next? I can give it a quick >> spin once you do so. > > I just pushed a tree with everything applied. HEAD of tree is > 22702a86997c5aed2e479bfe0b24d10d66b09604 dated May 11 11:58:06; a version > from earlier today was broken. Boot tested on BMIPS5000 (BCM7425): Tested-by: Florian Fainelli <f.fainelli@gmail.com> Thanks! -- Florian
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