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| Started by | Horia Ioan Geanta Neag <horia.geanta@nxp.com> |
|---|---|
| First post | 2016-05-09 11:10 +0200 |
| Last post | 2016-05-09 11:10 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCH v2 8/8] arm64: dts: ls1043a: add crypto node Horia Ioan Geanta Neag <horia.geanta@nxp.com> - 2016-05-09 11:10 +0200
| From | Horia Ioan Geanta Neag <horia.geanta@nxp.com> |
|---|---|
| Date | 2016-05-09 11:10 +0200 |
| Subject | Re: [PATCH v2 8/8] arm64: dts: ls1043a: add crypto node |
| Message-ID | <rwPmq-2eW-9@gated-at.bofh.it> |
+Shawn
On 5/5/2016 6:39 PM, Horia Geantă wrote:
> LS1043A has a SEC v5.4 security engine.
> For now don't add rtic or sec_mon subnodes, since these features
> haven't been tested yet.
>
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Shawn,
IIUC, you are the de facto maintainer of arch/arm64/boot/dts/freescale
entry, thus adding you to the loop.
I'd like to get the Ack for this patch.
As stated in the cover letter: https://lkml.org/lkml/2016/5/5/340
my intent is to go with the whole patch set via cryptodev-2.6 tree.
Thanks,
Horia
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 4 +++
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 43 +++++++++++++++++++++++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> index ce235577e90f..9b5b75a4f02a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> @@ -49,6 +49,10 @@
>
> / {
> model = "LS1043A RDB Board";
> +
> + aliases {
> + crypto = &crypto;
> + };
> };
>
> &i2c0 {
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index be72bf5b58b5..529c198494d5 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -159,6 +159,49 @@
> big-endian;
> };
>
> + crypto: crypto@1700000 {
> + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
> + "fsl,sec-v4.0";
> + fsl,sec-era = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x00 0x1700000 0x100000>;
> + reg = <0x00 0x1700000 0x0 0x100000>;
> + interrupts = <0 75 0x4>;
> +
> + sec_jr0: jr@10000 {
> + compatible = "fsl,sec-v5.4-job-ring",
> + "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x10000 0x10000>;
> + interrupts = <0 71 0x4>;
> + };
> +
> + sec_jr1: jr@20000 {
> + compatible = "fsl,sec-v5.4-job-ring",
> + "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x20000 0x10000>;
> + interrupts = <0 72 0x4>;
> + };
> +
> + sec_jr2: jr@30000 {
> + compatible = "fsl,sec-v5.4-job-ring",
> + "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x30000 0x10000>;
> + interrupts = <0 73 0x4>;
> + };
> +
> + sec_jr3: jr@40000 {
> + compatible = "fsl,sec-v5.4-job-ring",
> + "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x40000 0x10000>;
> + interrupts = <0 74 0x4>;
> + };
> + };
> +
> dcfg: dcfg@1ee0000 {
> compatible = "fsl,ls1043a-dcfg", "syscon";
> reg = <0x0 0x1ee0000 0x0 0x10000>;
>
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