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Groups > linux.kernel > #1396461 > unrolled thread
| Started by | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| First post | 2016-05-08 21:10 +0200 |
| Last post | 2016-05-10 00:10 +0200 |
| Articles | 20 on this page of 32 — 4 participants |
Back to article view | Back to linux.kernel
[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
[PATCH v2 21/22] ARM: dts: exynos: Add USB to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
[PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
[PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
Re: [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 22:30 +0200
Re: [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-10 07:30 +0200
[PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
Re: [PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 23:40 +0200
[PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
[PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
Re: [PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 21:40 +0200
[PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-10 00:00 +0200
Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-10 07:40 +0200
Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-10 15:00 +0200
[PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:10 +0200
Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board Rob Herring <robh@kernel.org> - 2016-05-09 22:10 +0200
Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-10 00:10 +0200
Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-10 07:40 +0200
[PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:20 +0200
Re: [PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 22:30 +0200
Re: [PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-10 07:30 +0200
[PATCH v2 09/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:20 +0200
[PATCH v2 11/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:20 +0200
[PATCH v2 14/22] ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:20 +0200
[PATCH v2 02/22] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-08 21:20 +0200
Re: [PATCH v2 02/22] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 21:50 +0200
Re: [PATCH v2 16/22] ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-09 23:40 +0200
Re: [PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-10 00:10 +0200
Re: [PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-10 07:20 +0200
Re: [PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-10 16:10 +0200
Re: [PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU Stephen Boyd <sboyd@codeaurora.org> - 2016-05-10 00:10 +0200
Page 1 of 2 [1] 2 Next page →
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU |
| Message-ID | <rwCfv-49F-3@gated-at.bofh.it> |
Hi,
Patchset adds necessary clocks, reorganizes existing stuff and finally
adds Odroid XU support.
Merging strategy
================
Complicated! The clock dt-bindings and driver changes can go to clock
tree. However there are three DTS patches in the middle.
a. This has to go in before adding "fin_pll_new" to clock driver:
- [PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver
b. This should go in before renaming "fin_pll_new" back to original name:
- [PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock
- [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410
The order of patches in the patchset is really how it should go in
to reduce any bisectability glitches.
Changes since v1
================
1. A lot of new patches.
2. Removed some TODO notes (eMMC 4.5 so no RCLK pin).
3. New clocks, more reorganization.
4. New common DTSI: exynos54xx.dtsi. I know, it is getting more
and more complicated but this might help removing duplications
and keeping everything under control.
Best regards,
Krzysztof
Krzysztof Kozlowski (22):
dt-bindings: clock: Add license and reformat Exynos5410 clock IDs
dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410
ARM: dts: exynos: Add fin_pll node for clock driver
clk: samsung: exynos5410: Provide fin_pll external fixed clock
ARM: dts: exynos: Switch MCT node to a new fin_pll clock
ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410
clk: samsung: exynos5410: Rename fin_pll from temporary to regular
name
clk: samsung: exynos5410: Add serial3, USB and PWM clocks
ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl
nodes
ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels
ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card
ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
ARM: dts: exynos: Move common nodes to exynos5.dtsi
ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in
exynos5410.dtsi
ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
ARM: dts: exynos: Enable UART3 on Exynos5410
ARM: dts: exynos: MCT is not an interrupt controller and extend length
of iomap
ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
ARM: dts: exynos: Add USB to Exynos5410
ARM: dts: exynos: Add initial support for Odroid XU board
.../bindings/arm/samsung/samsung-boards.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5.dtsi | 171 +-
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 2 +-
arch/arm/boot/dts/exynos5250.dtsi | 1718 +++++++++--------
arch/arm/boot/dts/exynos5410-odroidxu.dts | 166 ++
arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 77 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 16 +-
arch/arm/boot/dts/exynos5410.dtsi | 204 +-
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 12 +-
arch/arm/boot/dts/exynos5420.dtsi | 1981 ++++++++++----------
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 35 +-
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 35 +-
arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 50 +
arch/arm/boot/dts/exynos54xx.dtsi | 142 ++
drivers/clk/samsung/clk-exynos5410.c | 52 +
include/dt-bindings/clock/exynos5410.h | 64 +-
17 files changed, 2519 insertions(+), 2208 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts
create mode 100644 arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
create mode 100644 arch/arm/boot/dts/exynos54xx.dtsi
--
2.5.0
[toc] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 21/22] ARM: dts: exynos: Add USB to Exynos5410 |
| Message-ID | <rwCfw-49F-37@gated-at.bofh.it> |
| In reply to | #1396461 |
Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
should not have functional impact but for Exynos5410 this effectively
adds USB support.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
TODO: lack of regulator causes errors:
usb usb4-port1: over-current condition
?
---
arch/arm/boot/dts/exynos5410.dtsi | 39 ++++++++++++
arch/arm/boot/dts/exynos5420.dtsi | 131 ++++++++++++--------------------------
arch/arm/boot/dts/exynos54xx.dtsi | 74 +++++++++++++++++++++
3 files changed, 152 insertions(+), 92 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 850343d3c2af..dd4d6d752865 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -185,4 +185,43 @@
3 0 0x07000000 0x20000>;
};
+&usbdrd3_0 {
+ clocks = <&clock CLK_USBD300>;
+ clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+ clocks = <&clock CLK_USBD301>;
+ clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+ clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+};
+
+&usbhost2 {
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+};
+
+&usb2_phy {
+ clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,sysreg-phandle = <&sysreg_system_controller>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
#include "exynos5410-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 750571f838f2..ebf1dbec5070 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -829,98 +829,6 @@
clock-names = "secss";
};
- usbdrd3_0: usb3-0 {
- compatible = "samsung,exynos5250-dwusb3";
- clocks = <&clock CLK_USBD300>;
- clock-names = "usbdrd30";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbdrd_dwc3_0: dwc3@12000000 {
- compatible = "snps,dwc3";
- reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
- phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
- phy-names = "usb2-phy", "usb3-phy";
- };
- };
-
- usbdrd_phy0: phy@12100000 {
- compatible = "samsung,exynos5420-usbdrd-phy";
- reg = <0x12100000 0x100>;
- clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
- clock-names = "phy", "ref";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- };
-
- usbdrd3_1: usb3-1 {
- compatible = "samsung,exynos5250-dwusb3";
- clocks = <&clock CLK_USBD301>;
- clock-names = "usbdrd30";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbdrd_dwc3_1: dwc3@12400000 {
- compatible = "snps,dwc3";
- reg = <0x12400000 0x10000>;
- interrupts = <0 73 0>;
- phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
- phy-names = "usb2-phy", "usb3-phy";
- };
- };
-
- usbdrd_phy1: phy@12500000 {
- compatible = "samsung,exynos5420-usbdrd-phy";
- reg = <0x12500000 0x100>;
- clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
- clock-names = "phy", "ref";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- };
-
- usbhost2: usb@12110000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
-
- clocks = <&clock CLK_USBH20>;
- clock-names = "usbhost";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&usb2_phy 1>;
- };
- };
-
- usbhost1: usb@12120000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
-
- clocks = <&clock CLK_USBH20>;
- clock-names = "usbhost";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&usb2_phy 1>;
- };
- };
-
- usb2_phy: phy@12130000 {
- compatible = "samsung,exynos5250-usb2-phy";
- reg = <0x12130000 0x100>;
- clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- samsung,sysreg-phandle = <&sysreg_system_controller>;
- samsung,pmureg-phandle = <&pmu_system_controller>;
- };
-
sysmmu_g2dr: sysmmu@0x10A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
@@ -1184,4 +1092,43 @@
clock-names = "uart", "clk_uart_baud0";
};
+&usbdrd3_0 {
+ clocks = <&clock CLK_USBD300>;
+ clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+ clocks = <&clock CLK_USBD301>;
+ clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+ clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+};
+
+&usbhost2 {
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+};
+
+&usb2_phy {
+ clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,sysreg-phandle = <&sysreg_system_controller>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
#include "exynos5420-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9ce625bd79c1..0f3b8735849e 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -64,5 +64,79 @@
<11 &gic 0 131 0>;
};
};
+
+ usbdrd3_0: usb3-0 {
+ compatible = "samsung,exynos5250-dwusb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbdrd_dwc3_0: dwc3@12000000 {
+ compatible = "snps,dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ usbdrd_phy0: phy@12100000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12100000 0x100>;
+ #phy-cells = <1>;
+ };
+
+ usbdrd3_1: usb3-1 {
+ compatible = "samsung,exynos5250-dwusb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbdrd_dwc3_1: dwc3@12400000 {
+ compatible = "snps,dwc3";
+ reg = <0x12400000 0x10000>;
+ interrupts = <0 73 0>;
+ phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ usbdrd_phy1: phy@12500000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12500000 0x100>;
+ #phy-cells = <1>;
+ };
+
+ usbhost2: usb@12110000 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&usb2_phy 1>;
+ };
+ };
+
+ usbhost1: usb@12120000 {
+ compatible = "samsung,exynos4210-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <0 71 0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&usb2_phy 1>;
+ };
+ };
+
+ usb2_phy: phy@12130000 {
+ compatible = "samsung,exynos5250-usb2-phy";
+ reg = <0x12130000 0x100>;
+ #phy-cells = <1>;
+ };
};
};
--
2.5.0
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock |
| Message-ID | <rwCfw-49F-39@gated-at.bofh.it> |
| In reply to | #1396461 |
The clk-exynos5410 driver now provides the "fin_pll" external fixed
clock. Switch the Multi-Core Timer to this clock.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 7a56aec2c5ba..233149abfb62 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -125,7 +125,7 @@
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
- clocks = <&fin_pll>, <&clock CLK_MCT>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupt_map: interrupt-map {
--
2.5.0
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 |
| Message-ID | <rwCfw-49F-35@gated-at.bofh.it> |
| In reply to | #1396461 |
All "fin_pll" clock users are switched to the new one, provided by
Exynos5410 clock driver. Remove old DT node.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index d7d658deeff4..377a679b454b 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -24,13 +24,6 @@
bootargs = "console=ttySAC2,115200";
};
- fin_pll: xxti {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
-
fixed-rate-clocks {
oscclk {
compatible = "samsung,exynos5420-oscclk";
--
2.5.0
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| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-09 22:30 +0200 |
| Subject | Re: [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 |
| Message-ID | <rwZYw-4gl-51@gated-at.bofh.it> |
| In reply to | #1396464 |
Hello Krzysztof, On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote: > All "fin_pll" clock users are switched to the new one, provided by s/are switched/were switched > Exynos5410 clock driver. Remove old DT node. > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-10 07:30 +0200 |
| Subject | Re: [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 |
| Message-ID | <rx8p4-46L-7@gated-at.bofh.it> |
| In reply to | #1397369 |
On 05/09/2016 10:24 PM, Javier Martinez Canillas wrote: > Hello Krzysztof, > > On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote: >> All "fin_pll" clock users are switched to the new one, provided by > > s/are switched/were switched Thanks for spotting this, Krzysztof
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| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow |
| Message-ID | <rwCfx-49F-43@gated-at.bofh.it> |
| In reply to | #1396461 |
The i2c-arbitrator node in exynos5250-snow-common used absolute path to
reference other node (the i2c parent). Use phandle instead, because the
depth of the other node may be changed (like moving it under 'soc'
node).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index ddfe1f558c10..419d59da1751 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -61,7 +61,7 @@
#address-cells = <1>;
#size-cells = <0>;
- i2c-parent = <&{/i2c@12CA0000}>;
+ i2c-parent = <&i2c_4>;
our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
--
2.5.0
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| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-09 23:40 +0200 |
| Subject | Re: [PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow |
| Message-ID | <rx14f-5rm-9@gated-at.bofh.it> |
| In reply to | #1396466 |
Hello Krzysztof, On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: > The i2c-arbitrator node in exynos5250-snow-common used absolute path to > reference other node (the i2c parent). Use phandle instead, because the > depth of the other node may be changed (like moving it under 'soc' > node). > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver |
| Message-ID | <rwCfx-49F-45@gated-at.bofh.it> |
| In reply to | #1396461 |
For consistency between Exynos5410 and Exynos542x/5800 switch to similar
way of defining fin_pll/oscclk. Add a node early, before implementing
this in driver to preserve bisectability.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 0f6429e1b75c..d7d658deeff4 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -31,6 +31,13 @@
#clock-cells = <0>;
};
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5420-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+
firmware@02037000 {
compatible = "samsung,secure-firmware";
reg = <0x02037000 0x1000>;
--
2.5.0
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| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs |
| Message-ID | <rwCfx-49F-47@gated-at.bofh.it> |
| In reply to | #1396461 |
Add license and copyrights (file introduced in 2014) to header with Exynos5410 clock IDs. Additionally reformat it to improve readability. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> --- include/dt-bindings/clock/exynos5410.h | 54 ++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 9b180f032e2d..213f19e02870 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,33 +1,43 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5421 clock controller. +*/ + #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H /* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_BPLL 5 -#define CLK_FOUT_KPLL 6 +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 /* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 /* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_MCT 315 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_MCT 315 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 -#define CLK_NR_CLKS 512 +#define CLK_NR_CLKS 512 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ -- 2.5.0
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| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-09 21:40 +0200 |
| Subject | Re: [PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs |
| Message-ID | <rwZc5-3qZ-15@gated-at.bofh.it> |
| In reply to | #1396468 |
Hello Krzysztof, On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote: > Add license and copyrights (file introduced in 2014) to header with > Exynos5410 clock IDs. Additionally reformat it to improve readability. > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI |
| Message-ID | <rwCfx-49F-49@gated-at.bofh.it> |
| In reply to | #1396461 |
The Exynos5410/542x/5800 are very similar designs. Create new new
DTSI with common nodes to remove DTS duplication. Although currently
only MCT and SysRAM are shared but in future more nodes will be added to
common file.
The patch should not have functional impact.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410.dtsi | 55 ++++---------------------------
arch/arm/boot/dts/exynos5420.dtsi | 54 ++++---------------------------
arch/arm/boot/dts/exynos54xx.dtsi | 68 +++++++++++++++++++++++++++++++++++++++
3 files changed, 80 insertions(+), 97 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos54xx.dtsi
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 62dc3b4aef93..850343d3c2af 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -13,8 +13,7 @@
* published by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
-#include "exynos5.dtsi"
+#include "exynos54xx.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h>
@@ -73,53 +72,6 @@
reg = <0x10040000 0x5000>;
};
- mct: mct@101C0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0xB00>;
- interrupt-parent = <&interrupt_map>;
- interrupts = <0>, <1>, <2>, <3>,
- <4>, <5>, <6>, <7>,
- <8>, <9>, <10>, <11>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
- clock-names = "fin_pll", "mct";
-
- interrupt_map: interrupt-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &combiner 23 3>,
- <1 &combiner 23 4>,
- <2 &combiner 25 2>,
- <3 &combiner 25 3>,
- <4 &gic 0 120 0>,
- <5 &gic 0 121 0>,
- <6 &gic 0 122 0>,
- <7 &gic 0 123 0>,
- <8 &gic 0 128 0>,
- <9 &gic 0 129 0>,
- <10 &gic 0 130 0>,
- <11 &gic 0 131 0>;
- };
- };
-
- sysram@02020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x54000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x54000>;
-
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
-
- smp-sysram@53000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x53000 0x1000>;
- };
- };
-
clock: clock-controller@10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
@@ -194,6 +146,11 @@
};
};
+&mct {
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+};
+
&pwm {
clocks = <&clock CLK_PWM>;
clock-names = "timers";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ac39e3b8b0e1..750571f838f2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,9 +13,8 @@
* published by the Free Software Foundation.
*/
+#include "exynos54xx.dtsi"
#include <dt-bindings/clock/exynos5420.h>
-#include "exynos5.dtsi"
-
#include <dt-bindings/clock/exynos-audss-clk.h>
/ {
@@ -185,24 +184,6 @@
};
};
- sysram@02020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x54000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x54000>;
-
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
-
- smp-sysram@53000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x53000 0x1000>;
- };
- };
-
clock: clock-controller@10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
@@ -265,34 +246,6 @@
status = "disabled";
};
- mct: mct@101C0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0xB00>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
- <8>, <9>, <10>, <11>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &combiner 23 3>,
- <1 &combiner 23 4>,
- <2 &combiner 25 2>,
- <3 &combiner 25 3>,
- <4 &gic 0 120 0>,
- <5 &gic 0 121 0>,
- <6 &gic 0 122 0>,
- <7 &gic 0 123 0>,
- <8 &gic 0 128 0>,
- <9 &gic 0 129 0>,
- <10 &gic 0 130 0>,
- <11 &gic 0 131 0>;
- };
- };
-
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -1194,6 +1147,11 @@
iommu-names = "m0", "m1";
};
+&mct {
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+};
+
&pwm {
clocks = <&clock CLK_PWM>;
clock-names = "timers";
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
new file mode 100644
index 000000000000..9ce625bd79c1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Samsung's Exynos54xx SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
+ * Exynos 54xx SoCs should include this file and customize it further
+ * (e.g. with clocks).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include "exynos5.dtsi"
+
+/ {
+ compatible = "samsung,exynos5";
+
+ soc: soc {
+ sysram@02020000 {
+ compatible = "mmio-sram";
+ reg = <0x02020000 0x54000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x02020000 0x54000>;
+
+ smp-sysram@0 {
+ compatible = "samsung,exynos4210-sysram";
+ reg = <0x0 0x1000>;
+ };
+
+ smp-sysram@53000 {
+ compatible = "samsung,exynos4210-sysram-ns";
+ reg = <0x53000 0x1000>;
+ };
+ };
+
+ mct: mct@101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0xB00>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
+
+ mct_map: mct-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &combiner 23 3>,
+ <1 &combiner 23 4>,
+ <2 &combiner 25 2>,
+ <3 &combiner 25 3>,
+ <4 &gic 0 120 0>,
+ <5 &gic 0 121 0>,
+ <6 &gic 0 122 0>,
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
+ };
+ };
+ };
+};
--
2.5.0
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| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-10 00:00 +0200 |
| Subject | Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI |
| Message-ID | <rx1nB-5F3-21@gated-at.bofh.it> |
| In reply to | #1396469 |
Hello Krzysztof, On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: > The Exynos5410/542x/5800 are very similar designs. Create new new s/new new/a new > DTSI with common nodes to remove DTS duplication. Although currently > only MCT and SysRAM are shared but in future more nodes will be added to > common file. > > The patch should not have functional impact. > A nice way to check this is to diff the disassembled compiled DTBs with and without the patch and making sure that the resulted DTS is the same. > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
[toc] | [prev] | [next] | [standalone]
| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-10 07:40 +0200 |
| Subject | Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI |
| Message-ID | <rx8yL-4c5-17@gated-at.bofh.it> |
| In reply to | #1397428 |
On 05/09/2016 11:53 PM, Javier Martinez Canillas wrote: > Hello Krzysztof, > > On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: >> The Exynos5410/542x/5800 are very similar designs. Create new new > > s/new new/a new > >> DTSI with common nodes to remove DTS duplication. Although currently >> only MCT and SysRAM are shared but in future more nodes will be added to >> common file. >> >> The patch should not have functional impact. >> > > A nice way to check this is to diff the disassembled compiled DTBs with > and without the patch and making sure that the resulted DTS is the same. Yes, that is what I've done. Recently there is a tool making that even easier: dtx_diff. Best regards, Krzysztof
[toc] | [prev] | [next] | [standalone]
| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-10 15:00 +0200 |
| Subject | Re: [PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI |
| Message-ID | <rxfqy-2xu-9@gated-at.bofh.it> |
| In reply to | #1397706 |
Hello Krzysztof, On 05/10/2016 01:33 AM, Krzysztof Kozlowski wrote: > On 05/09/2016 11:53 PM, Javier Martinez Canillas wrote: >> Hello Krzysztof, >> >> On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: >>> The Exynos5410/542x/5800 are very similar designs. Create new new >> >> s/new new/a new >> >>> DTSI with common nodes to remove DTS duplication. Although currently >>> only MCT and SysRAM are shared but in future more nodes will be added to >>> common file. >>> >>> The patch should not have functional impact. >>> >> >> A nice way to check this is to diff the disassembled compiled DTBs with >> and without the patch and making sure that the resulted DTS is the same. > > Yes, that is what I've done. Recently there is a tool making that even > easier: dtx_diff. > I didn't know we had such a tool in mainline now. Very useful, thanks a lot for the information. > Best regards, > Krzysztof > Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
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| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:10 +0200 |
| Subject | [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board |
| Message-ID | <rwCfx-49F-51@gated-at.bofh.it> |
| In reply to | #1396461 |
The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
the differences are:
1. Exynos5410 instead of 5422,
2. DisplayPort,
3. Main PMIC: Maxim 77802 instead of S2MPS11,
4. USB3503+LAN9730 instead of integrated LAN9514,
5. eMMC 4.5 instead of eMMC 5.0,
This patch adds initial support for the XU board with working basic
functions, eMMC/SD and USB (including attached ethernet adapter).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/arm/samsung/samsung-boards.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-odroidxu.dts | 166 +++++++++++++++++++++
3 files changed, 168 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index f5deace2b380..0ea7f14ef294 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -47,6 +47,7 @@ Required root node properties:
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
+ - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
Odroid XU3 Lite board.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5aeb10674370..9ed1c7abedb1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5250-snow-rev5.dtb \
exynos5250-spring.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-odroidxu.dtb \
exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
new file mode 100644
index 000000000000..b0cbd53aeea9
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -0,0 +1,166 @@
+/*
+ * Hardkernel Odroid XU3 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "exynos54xx-odroidxu-leds.dtsi"
+
+/ {
+ model = "Hardkernel Odroid XU";
+ compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
+
+ memory {
+ reg = <0x40000000 0x7EA00000>;
+ };
+
+ chosen {
+ linux,stdout-path = &serial_2;
+ };
+
+ /* TODO: these will be the same as in XU3-common file */
+ emmc_pwrseq: pwrseq {
+ pinctrl-0 = <&emmc_nrst_pin>;
+ pinctrl-names = "default";
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm 0 20972 0>;
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ #cooling-cells = <2>;
+ cooling-levels = <0 130 170 230>;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5420-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ firmware@02073000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x02073000 0x1000>;
+ };
+};
+
+/* TODO:
+&i2c_4 {
+ status = "okay";
+
+ ina231@40 {
+ compatible = "ti,ina231";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ };
+
+ ina231@41 {
+ compatible = "ti,ina231";
+ reg = <0x41>;
+ shunt-resistor = <10000>;
+ };
+
+ ina231@44 {
+ compatible = "ti,ina231";
+ reg = <0x44>;
+ shunt-resistor = <10000>;
+ };
+
+ ina231@45 {
+ compatible = "ti,ina231";
+ reg = <0x45>;
+ shunt-resistor = <10000>;
+ };
+};
+*/
+
+&mmc_0 {
+ status = "okay";
+ mmc-pwrseq = <&emmc_pwrseq>;
+ cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ samsung,dw-mshc-hs400-timing = <0 2>;
+ samsung,read-strobe-delay = <90>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ //vmmc-supply = <&ldo18_reg>; // FIXME
+ //vqmmc-supply = <&ldo3_reg>; // FIXME
+};
+
+&mmc_2 {
+ status = "okay";
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ //vmmc-supply = <&ldo19_reg>; // FIXME
+ //vqmmc-supply = <&ldo13_reg>; // Thats gonna be different than XU3 // FIXME
+};
+
+&pinctrl_0 {
+ emmc_nrst_pin: emmc-nrst {
+ samsung,pins = "gpd1-0";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
+
+&serial_3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd3_0 {
+// vdd33-supply = <&ldo9_reg>;
+// vdd10-supply = <&ldo11_reg>;
+};
+
+&usbdrd3_1 {
+// vdd33-supply = <&ldo9_reg>;
+// vdd10-supply = <&ldo11_reg>;
+};
--
2.5.0
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-05-09 22:10 +0200 |
| Subject | Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board |
| Message-ID | <rwZFa-42D-51@gated-at.bofh.it> |
| In reply to | #1396470 |
On Sun, May 08, 2016 at 09:06:07PM +0200, Krzysztof Kozlowski wrote:
> The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
> from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
> the differences are:
> 1. Exynos5410 instead of 5422,
> 2. DisplayPort,
> 3. Main PMIC: Maxim 77802 instead of S2MPS11,
> 4. USB3503+LAN9730 instead of integrated LAN9514,
> 5. eMMC 4.5 instead of eMMC 5.0,
>
> This patch adds initial support for the XU board with working basic
> functions, eMMC/SD and USB (including attached ethernet adapter).
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 1 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos5410-odroidxu.dts | 166 +++++++++++++++++++++
> 3 files changed, 168 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index f5deace2b380..0ea7f14ef294 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -47,6 +47,7 @@ Required root node properties:
> - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
> - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
> - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
> + - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
> - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
> - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
> Odroid XU3 Lite board.
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 5aeb10674370..9ed1c7abedb1 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
> exynos5250-snow-rev5.dtb \
> exynos5250-spring.dtb \
> exynos5260-xyref5260.dtb \
> + exynos5410-odroidxu.dtb \
> exynos5410-smdk5410.dtb \
> exynos5420-arndale-octa.dtb \
> exynos5420-peach-pit.dtb \
> diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
> new file mode 100644
> index 000000000000..b0cbd53aeea9
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
> @@ -0,0 +1,166 @@
> +/*
> + * Hardkernel Odroid XU3 board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + * Copyright (c) 2016 Krzysztof Kozlowski
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5410.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "exynos54xx-odroidxu-leds.dtsi"
> +
> +/ {
> + model = "Hardkernel Odroid XU";
> + compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
> +
> + memory {
> + reg = <0x40000000 0x7EA00000>;
lowercase hex please.
With that,
Acked-by: Rob Herring <robh@kernel.org>
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| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Date | 2016-05-10 00:10 +0200 |
| Subject | Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board |
| Message-ID | <rx1xg-6ah-17@gated-at.bofh.it> |
| In reply to | #1396470 |
Hello Krzysztof, On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: > The Hardkernel's Odroid XU board was first design with big.LITTLE SoC > from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3 > the differences are: > 1. Exynos5410 instead of 5422, > 2. DisplayPort, > 3. Main PMIC: Maxim 77802 instead of S2MPS11, > 4. USB3503+LAN9730 instead of integrated LAN9514, > 5. eMMC 4.5 instead of eMMC 5.0, > > This patch adds initial support for the XU board with working basic > functions, eMMC/SD and USB (including attached ethernet adapter). > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- This DTS has some TODO's, FIXME's and commented input supplies. Probably this patch should had been an RFC? or you should mention about these in the commit message to understand why are there. Best regards, -- Javier Martinez Canillas Open Source Group Samsung Research America
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| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-10 07:40 +0200 |
| Subject | Re: [PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board |
| Message-ID | <rx8yL-4c5-13@gated-at.bofh.it> |
| In reply to | #1397439 |
On 05/10/2016 12:02 AM, Javier Martinez Canillas wrote: > Hello Krzysztof, > > On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote: >> The Hardkernel's Odroid XU board was first design with big.LITTLE SoC >> from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3 >> the differences are: >> 1. Exynos5410 instead of 5422, >> 2. DisplayPort, >> 3. Main PMIC: Maxim 77802 instead of S2MPS11, >> 4. USB3503+LAN9730 instead of integrated LAN9514, >> 5. eMMC 4.5 instead of eMMC 5.0, >> >> This patch adds initial support for the XU board with working basic >> functions, eMMC/SD and USB (including attached ethernet adapter). >> >> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> >> --- > > This DTS has some TODO's, FIXME's and commented input supplies. Probably > this patch should had been an RFC? or you should mention about these in > the commit message to understand why are there. I have to clean it up or fix these notes. Actually I was quite surprised that board worked fine with this basic setup. Best regards, Krzysztof
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| From | Krzysztof Kozlowski <krzk@kernel.org> |
|---|---|
| Date | 2016-05-08 21:20 +0200 |
| Subject | [PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock |
| Message-ID | <rwCpb-4eI-1@gated-at.bofh.it> |
| In reply to | #1396461 |
Just like clock driver for Exynos542x/5800, provide the fixed clock here
so the clock bindings and their consumers would be consistent and
similar.
However a clock named "fin_pll" is already provided by generic
fixed-clock and it is both referenced in the clock driver (by name) and
in DT (by phandle). To make the transition smooth, first introduce the
new external fixed clock here under temporary, different name and switch
internal users to it.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/clk/samsung/clk-exynos5410.c | 42 +++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..35f2cb36f7ef 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -59,23 +59,29 @@ enum exynos5410_plls {
};
/* list of all parent clocks */
-PNAME(apll_p) = { "fin_pll", "fout_apll", };
-PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
-PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
-PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
-PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+PNAME(apll_p) = { "fin_pll_new", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll_new", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll_new", "fout_cpll" };
+PNAME(mpll_p) = { "fin_pll_new", "fout_mpll", };
+PNAME(kpll_p) = { "fin_pll_new", "fout_kpll", };
PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
-PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
-PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
+PNAME(mpll_user_p) = { "fin_pll_new", "sclk_mpll", };
+PNAME(bpll_user_p) = { "fin_pll_new", "sclk_bpll", };
PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
-PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
+PNAME(group2_p) = { "fin_pll_new", "fin_pll_new", "none", "none",
"none", "none", "sclk_mpll_bpll",
"none", "none", "sclk_cpll" };
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock
+ exynos5x_fixed_rate_ext_clks[] __initdata = {
+ FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0),
+};
+
static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
@@ -168,18 +174,24 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
};
static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
- [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK,
APLL_CON0, NULL),
- [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK,
CPLL_CON0, NULL),
- [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK,
MPLL_CON0, NULL),
- [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK,
BPLL_CON0, NULL),
- [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK,
KPLL_CON0, NULL),
};
+/* Same as in Exynos5420 */
+static const struct of_device_id ext_clk_match[] __initconst = {
+ { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+ { },
+};
+
/* register exynos5410 clocks */
static void __init exynos5410_clk_init(struct device_node *np)
{
@@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
+ ext_clk_match);
+
samsung_clk_register_pll(ctx, exynos5410_plls,
ARRAY_SIZE(exynos5410_plls), reg_base);
--
2.5.0
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