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Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div

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  Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div Tero Kristo <t-kristo@ti.com> - 2016-04-27 13:30 +0200
    Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div Tony Lindgren <tony@atomide.com> - 2016-04-27 18:40 +0200
      Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div Tony Lindgren <tony@atomide.com> - 2016-04-27 19:20 +0200

#1388915 — Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div

On 26/04/16 20:54, J.D. Schroeder wrote:
> From: "J.D. Schroeder" <jay.schroeder@garmin.com>
>
> This commit fixes the clock data inside the DRA7xx clocks device tree
> structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> the GMAC_MAIN_CLK and has nothing to do with the register at address
> 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> set to 1 in order to use the GMAC_RMII_CLK instead of the
> GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
>      WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
>      gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
>
> By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> resolved and the clock tree is fixed up.
>
> Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> source clock for the RMII_50MHZ_CLK.
>
> Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com>
> Reviewed-by: Trenton Andres <trenton.andres@garmin.com>

Looks like something weird happened with the clock data conversion tool 
with this specific clock. Seems to be the only buggy instance in our 
clock data across SoCs. Good catch.

Acked-by: Tero Kristo <t-kristo@ti.com>

> ---
>   arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++----
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index d0bae06..9d1a583 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -1710,13 +1710,20 @@
>   		reg = <0x0c00>;
>   	};
>
> -	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
> +	rmii_50mhz_clk_mux: rmii_50mhz_clk_mux {
>   		#clock-cells = <0>;
> -		compatible = "ti,divider-clock";
> -		clocks = <&dpll_gmac_m2_ck>;
> +		compatible = "ti,mux-clock";
> +		clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
>   		ti,bit-shift = <24>;
>   		reg = <0x13d0>;
> -		ti,dividers = <2>;
> +	};
> +
> +	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
> +		#clock-cells = <0>;
> +		compatible = "fixed-factor-clock";
> +		clocks = <&dpll_gmac_m2_ck>;
> +		clock-mult = <1>;
> +		clock-div = <2>;
>   	};
>
>   	gmac_rft_clk_mux: gmac_rft_clk_mux {
>

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#1389345

* Tero Kristo <t-kristo@ti.com> [160427 04:22]:
> On 26/04/16 20:54, J.D. Schroeder wrote:
> >From: "J.D. Schroeder" <jay.schroeder@garmin.com>
> >
> >This commit fixes the clock data inside the DRA7xx clocks device tree
> >structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> >the GMAC_MAIN_CLK and has nothing to do with the register at address
> >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> >set to 1 in order to use the GMAC_RMII_CLK instead of the
> >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
> >     WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
> >     gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> >
> >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> >resolved and the clock tree is fixed up.
> >
> >Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> >source clock for the RMII_50MHZ_CLK.
> >
> >Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com>
> >Reviewed-by: Trenton Andres <trenton.andres@garmin.com>
> 
> Looks like something weird happened with the clock data conversion tool with
> this specific clock. Seems to be the only buggy instance in our clock data
> across SoCs. Good catch.
> 
> Acked-by: Tero Kristo <t-kristo@ti.com>

Applying into omap-for-v4.6/fixes thanks.

Tony

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#1389385

* Tony Lindgren <tony@atomide.com> [160427 09:39]:
> * Tero Kristo <t-kristo@ti.com> [160427 04:22]:
> > On 26/04/16 20:54, J.D. Schroeder wrote:
> > >From: "J.D. Schroeder" <jay.schroeder@garmin.com>
> > >
> > >This commit fixes the clock data inside the DRA7xx clocks device tree
> > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> > >the GMAC_MAIN_CLK and has nothing to do with the register at address
> > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> > >set to 1 in order to use the GMAC_RMII_CLK instead of the
> > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
> > >     WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
> > >     gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> > >
> > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> > >resolved and the clock tree is fixed up.
> > >
> > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> > >source clock for the RMII_50MHZ_CLK.
> > >
> > >Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com>
> > >Reviewed-by: Trenton Andres <trenton.andres@garmin.com>
> > 
> > Looks like something weird happened with the clock data conversion tool with
> > this specific clock. Seems to be the only buggy instance in our clock data
> > across SoCs. Good catch.
> > 
> > Acked-by: Tero Kristo <t-kristo@ti.com>
> 
> Applying into omap-for-v4.6/fixes thanks.

Actually then we end up creating self-inflicted merge conflict
here with next. So let's wait a bit on this one as it's harmless.

J.D. can you please rebase this against current Linux next?

Note the recent unit name and unit address fixes for warnings
with make W=1 dtbs.

Regards,

Tony

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