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[PATCH 0/6] Fix the clock controller driver for the RK3399

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  [PATCH 0/6] Fix the clock controller driver for the RK3399 Xing Zheng <zhengxing@rock-chips.com> - 2016-04-20 13:10 +0200
    [PATCH 4/6] clk: rockchip: rk3399: update necessary critical clocks Xing Zheng <zhengxing@rock-chips.com> - 2016-04-20 13:10 +0200
      Re: [PATCH 4/6] clk: rockchip: rk3399: update necessary critical clocks Heiko Stübner <heiko@sntech.de> - 2016-04-26 00:10 +0200
    [PATCH 6/6] clk: rockchip: rk3399: fix the gate bit for i2c4 and i2c8 Xing Zheng <zhengxing@rock-chips.com> - 2016-04-20 13:20 +0200
      Re: [PATCH 6/6] clk: rockchip: rk3399: fix the gate bit for i2c4 and i2c8 Heiko Stübner <heiko@sntech.de> - 2016-04-25 23:10 +0200
    [PATCH 5/6] clk: rockchip: rk3399: fix the cifout clock Xing Zheng <zhengxing@rock-chips.com> - 2016-04-20 13:20 +0200
      Re: [PATCH 5/6] clk: rockchip: rk3399: fix the cifout clock Heiko Stübner <heiko@sntech.de> - 2016-04-25 23:10 +0200
    Re: [PATCH 3/6] clk: rockchip: rk3399: drop unnecessary CLK_IGNORE_UNUSED flags Heiko Stübner <heiko@sntech.de> - 2016-04-25 23:10 +0200

#1383287 — [PATCH 0/6] Fix the clock controller driver for the RK3399

Hi,
  This patchset fix some issues and optimized some features for
the RK3399 clock controller in the development process.

Thanks.


Xing Zheng (6):
  clk: rockchip: rk3399: export some necessary clock IDs
  clk: rockchip: rk3399: add some frequencies on the PLL table
  clk: rockchip: rk3399: drop unnecessary CLK_IGNORE_UNUSED flags
  clk: rockchip: rk3399: update necessary critical clocks
  clk: rockchip: rk3399: fix the cifout clock
  clk: rockchip: rk3399: fix the gate bit for i2c4 and i2c8

 drivers/clk/rockchip/clk-rk3399.c      |  416 ++++++++++++++++++--------------
 include/dt-bindings/clock/rk3399-cru.h |    5 +-
 2 files changed, 243 insertions(+), 178 deletions(-)

-- 
1.7.9.5

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#1383288 — [PATCH 4/6] clk: rockchip: rk3399: update necessary critical clocks

We need to declare that we enable all NOCs which are critical
clocks always and clearly and explicitly show that we have enabled
them at clk_summary.

We need to add some has been verified and required critical clocks
in the development process.

And the pclk_perilp1_noc is also add CLK_IGNORE_UNUSED flag.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |   72 +++++++++++++++++++++++++++++++------
 1 file changed, 62 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 232ea68..1da4fe1 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1043,7 +1043,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
 	GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
 	GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
-	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
+	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS),
 
 	/* saradc */
 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
@@ -1464,33 +1464,85 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
 };
 
 static const char *const rk3399_cru_critical_clocks[] __initconst = {
-	"aclk_cci_pre",
+	/*
+	 * We need to declare that we enable all NOCs which are critical clocks
+	 * always and clearly and explicitly show that we have enabled them at
+	 * clk_summary.
+	 */
+	"aclk_usb3_noc",
+	"aclk_gmac_noc",
+	"pclk_gmac_noc",
+	"pclk_center_main_noc",
+	"aclk_cci_noc0",
+	"aclk_cci_noc1",
+	"clk_dbg_noc",
+	"hclk_vcodec_noc",
+	"aclk_vcodec_noc",
+	"hclk_vdu_noc",
+	"aclk_vdu_noc",
+	"hclk_iep_noc",
+	"aclk_iep_noc",
+	"hclk_rga_noc",
+	"aclk_rga_noc",
+	"aclk_center_main_noc",
+	"aclk_center_peri_noc",
+	"aclk_perihp_noc",
+	"hclk_perihp_noc",
+	"pclk_perihp_noc",
+	"hclk_sdmmc_noc",
+	"aclk_emmc_noc",
+	"aclk_perilp0_noc",
+	"hclk_perilp0_noc",
+	"hclk_m0_perilp_noc",
+	"hclk_perilp1_noc",
+	"hclk_sdio_noc",
+	"hclk_sdioaudio_noc",
+	"pclk_perilp1_noc",
+	"aclk_vio_noc",
+	"aclk_hdcp_noc",
+	"hclk_hdcp_noc",
+	"pclk_hdcp_noc",
+	"pclk_edp_noc",
+	"aclk_vop0_noc",
+	"hclk_vop0_noc",
+	"aclk_vop1_noc",
+	"hclk_vop1_noc",
+	"aclk_isp0_noc",
+	"hclk_isp0_noc",
+	"aclk_isp1_noc",
+	"hclk_isp1_noc",
+	"aclk_gic_noc",
+
+	/* other critical clocks */
 	"pclk_perilp0",
 	"pclk_perilp0",
 	"hclk_perilp0",
-	"hclk_perilp0_noc",
 	"pclk_perilp1",
-	"pclk_perilp1_noc",
 	"pclk_perihp",
-	"pclk_perihp_noc",
 	"hclk_perihp",
 	"aclk_perihp",
-	"aclk_perihp_noc",
 	"aclk_perilp0",
-	"aclk_perilp0_noc",
 	"hclk_perilp1",
-	"hclk_perilp1_noc",
-	"aclk_dmac0_perilp",
-	"gpll_hclk_perilp1_src",
+	"aclk_dmac1_perilp",
 	"gpll_aclk_perilp0_src",
 	"gpll_aclk_perihp_src",
 };
 
 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
+	/*
+	 * We need to declare that we enable all NOCs which are critical clocks
+	 * always and clearly and explicitly show that we have enabled them at
+	 * clk_summary.
+	 */
+	"pclk_noc_pmu",
+	"hclk_noc_pmu",
+
+	/* other critical clocks */
 	"ppll",
 	"pclk_pmu_src",
 	"fclk_cm0s_src_pmu",
 	"clk_timer_src_pmu",
+	"pclk_rkpwm_pmu",
 };
 
 static void __init rk3399_clk_init(struct device_node *np)
-- 
1.7.9.5

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#1386950 — Re: [PATCH 4/6] clk: rockchip: rk3399: update necessary critical clocks

Am Mittwoch, 20. April 2016, 19:06:52 schrieb Xing Zheng:
> We need to declare that we enable all NOCs which are critical
> clocks always and clearly and explicitly show that we have enabled
> them at clk_summary.
> 
> We need to add some has been verified and required critical clocks
> in the development process.
> 
> And the pclk_perilp1_noc is also add CLK_IGNORE_UNUSED flag.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---
> 
>  drivers/clk/rockchip/clk-rk3399.c |   72
> +++++++++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 10
> deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3399.c
> b/drivers/clk/rockchip/clk-rk3399.c index 232ea68..1da4fe1 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -1043,7 +1043,7 @@ static struct rockchip_clk_branch
> rk3399_clk_branches[] __initdata = { GATE(PCLK_SPI2, "pclk_spi2",
> "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), GATE(PCLK_SPI4,
> "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
> GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0,
> RK3399_CLKGATE_CON(24), 13, GFLAGS), 
> -	GATE(0, "pclk_perilp1_noc",
> "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), 
> +	GATE(0,
> "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(25), 10, GFLAGS),

why do you think you need a CLK_IGNORE_UNUSED when you have pclk_perilp1_noc 
in the list of critical clocks below already? Aka as critical clock, it will 
stay enabled anyway.


> 
>  	/* saradc */
>  	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
> @@ -1464,33 +1464,85 @@ static struct rockchip_clk_branch
> rk3399_clk_pmu_branches[] __initdata = { };
> 
>  static const char *const rk3399_cru_critical_clocks[] __initconst = {
> -	"aclk_cci_pre",
> +	/*
> +	 * We need to declare that we enable all NOCs which are critical clocks
> +	 * always and clearly and explicitly show that we have enabled them at
> +	 * clk_summary.
> +	 */

I think that comment is not really helping here to explain the background.

Also, one thing I'd really like to know is what a NOC actually is. I know it's 
related to the interconnect, but so far I haven't found anything explaining 
the acronym.


Heiko

> +	"aclk_usb3_noc",
> +	"aclk_gmac_noc",
> +	"pclk_gmac_noc",
> +	"pclk_center_main_noc",
> +	"aclk_cci_noc0",
> +	"aclk_cci_noc1",
> +	"clk_dbg_noc",
> +	"hclk_vcodec_noc",
> +	"aclk_vcodec_noc",
> +	"hclk_vdu_noc",
> +	"aclk_vdu_noc",
> +	"hclk_iep_noc",
> +	"aclk_iep_noc",
> +	"hclk_rga_noc",
> +	"aclk_rga_noc",
> +	"aclk_center_main_noc",
> +	"aclk_center_peri_noc",
> +	"aclk_perihp_noc",
> +	"hclk_perihp_noc",
> +	"pclk_perihp_noc",
> +	"hclk_sdmmc_noc",
> +	"aclk_emmc_noc",
> +	"aclk_perilp0_noc",
> +	"hclk_perilp0_noc",
> +	"hclk_m0_perilp_noc",
> +	"hclk_perilp1_noc",
> +	"hclk_sdio_noc",
> +	"hclk_sdioaudio_noc",
> +	"pclk_perilp1_noc",
> +	"aclk_vio_noc",
> +	"aclk_hdcp_noc",
> +	"hclk_hdcp_noc",
> +	"pclk_hdcp_noc",
> +	"pclk_edp_noc",
> +	"aclk_vop0_noc",
> +	"hclk_vop0_noc",
> +	"aclk_vop1_noc",
> +	"hclk_vop1_noc",
> +	"aclk_isp0_noc",
> +	"hclk_isp0_noc",
> +	"aclk_isp1_noc",
> +	"hclk_isp1_noc",
> +	"aclk_gic_noc",
> +
> +	/* other critical clocks */
>  	"pclk_perilp0",
>  	"pclk_perilp0",
>  	"hclk_perilp0",
> -	"hclk_perilp0_noc",
>  	"pclk_perilp1",
> -	"pclk_perilp1_noc",
>  	"pclk_perihp",
> -	"pclk_perihp_noc",
>  	"hclk_perihp",
>  	"aclk_perihp",
> -	"aclk_perihp_noc",
>  	"aclk_perilp0",
> -	"aclk_perilp0_noc",
>  	"hclk_perilp1",
> -	"hclk_perilp1_noc",
> -	"aclk_dmac0_perilp",
> -	"gpll_hclk_perilp1_src",
> +	"aclk_dmac1_perilp",
>  	"gpll_aclk_perilp0_src",
>  	"gpll_aclk_perihp_src",
>  };
> 
>  static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
> +	/*
> +	 * We need to declare that we enable all NOCs which are critical clocks
> +	 * always and clearly and explicitly show that we have enabled them at
> +	 * clk_summary.
> +	 */
> +	"pclk_noc_pmu",
> +	"hclk_noc_pmu",
> +
> +	/* other critical clocks */
>  	"ppll",
>  	"pclk_pmu_src",
>  	"fclk_cm0s_src_pmu",
>  	"clk_timer_src_pmu",
> +	"pclk_rkpwm_pmu",
>  };
> 
>  static void __init rk3399_clk_init(struct device_node *np)

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#1383298 — [PATCH 6/6] clk: rockchip: rk3399: fix the gate bit for i2c4 and i2c8

The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index e81cc85..3c5ab39 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1411,11 +1411,11 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
 
 	COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
 			RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
-			RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
+			RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
 
 	COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
 			RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
-			RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
+			RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
 
 	DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
 			RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
-- 
1.7.9.5

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#1386893 — Re: [PATCH 6/6] clk: rockchip: rk3399: fix the gate bit for i2c4 and i2c8

Am Mittwoch, 20. April 2016, 19:12:10 schrieb Xing Zheng:
> The gate bits of the i2c4 and i2c8 are incorrect due to the manual
> error, we need to fix them.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7

Thanks
Heiko

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#1383301 — [PATCH 5/6] clk: rockchip: rk3399: fix the cifout clock

The cifout clock is incorrect due to the manual error, we need to
fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 1da4fe1..e81cc85 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -158,7 +158,7 @@ PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
 PNAME(mux_dclk_vop1_p)			= { "dclk_vop1_div",
 					    "dclk_vop1_frac" };
 
-PNAME(mux_clk_cif_p)			= { "clk_cifout_div", "xin24m" };
+PNAME(mux_clk_cif_p)				= { "clk_cifout_src", "xin24m" };
 
 PNAME(mux_pll_src_24m_usbphy480m_p)	= { "xin24m", "clk_usbphy_480m" };
 PNAME(mux_pll_src_24m_pciephy_p)	= { "xin24m", "clk_pciephy_ref100m" };
@@ -1254,11 +1254,12 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(27), 6, GFLAGS),
 
 	/* cif */
-	COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, 0,
-			RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
+	COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
+			RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
 			RK3399_CLKGATE_CON(10), 7, GFLAGS),
-	MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
-			RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
+
+	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
+			 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
 
 	/* gic */
 	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
-- 
1.7.9.5

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#1386894 — Re: [PATCH 5/6] clk: rockchip: rk3399: fix the cifout clock

Am Mittwoch, 20. April 2016, 19:11:32 schrieb Xing Zheng:
> The cifout clock is incorrect due to the manual error, we need to
> fix it.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7

Thanks
Heiko

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#1386892 — Re: [PATCH 3/6] clk: rockchip: rk3399: drop unnecessary CLK_IGNORE_UNUSED flags

Am Mittwoch, 20. April 2016, 19:06:51 schrieb Xing Zheng:
> We don't need to many clocks enable after startup, to reduce some
> power consumption.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7

Thanks
Heiko

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