Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1380851 > unrolled thread

[PATCH v4 0/2] Skylake PSys support

Back to article view | Back to linux.kernel

Contents

  [PATCH v4 0/2] Skylake PSys support Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-04-18 00:10 +0200
    [PATCH v4 2/2] powercap: intel_rapl: PSys support Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-04-18 00:10 +0200
      [tip:perf/core] powercap, perf/x86/intel/rapl: Add PSys support tip-bot for Srinivas Pandruvada <tipbot@zytor.com> - 2016-04-28 12:30 +0200
    Re: [PATCH v4 0/2] Skylake PSys support Peter Zijlstra <peterz@infradead.org> - 2016-04-20 16:00 +0200
      Re: [PATCH v4 0/2] Skylake PSys support Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-04-20 20:30 +0200
        Re: [PATCH v4 0/2] Skylake PSys support "Rafael J. Wysocki" <rafael@kernel.org> - 2016-04-20 22:30 +0200
          Re: [PATCH v4 0/2] Skylake PSys support Peter Zijlstra <peterz@infradead.org> - 2016-04-21 15:20 +0200
            Re: [PATCH v4 0/2] Skylake PSys support Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-04-21 17:00 +0200

#1380851 — [PATCH v4 0/2] Skylake PSys support

Skylake processor supports a new set of RAPL registers for controlling
entire SoC instead of just CPU package called PSys. This change adds
support in two sub systems:

x86/perf: Adds basic support for Skylake RAPL and PSys support

powercap/rapl: A new platform domain to the current power capping Intel
RAPL driver.

v4
Perf:
- Rebased the patch as msr-index file changed.
- Added a new Skylake H/L model
- Changed RAPL_IDX_SKL to RAPL_IDX_SKL_CLN to avoid clash
with SKL server domain once we add SKL server support

Powercap/rapl:
- Fix kbuild test robot compliant about invalid domain error in dmesg

v3:
As suggested by tglx adding support first in perf-rapl.
Perf RAPL was missing RAPL support for Skylake
Added support including Psys

v2:
Moved PSYS MSR defines to intel_rapl.c as suggested by Boris

Srinivas Pandruvada (2):
  perf/x86/intel/rapl: support Skylake RAPL domains
  powercap: intel_rapl: PSys support

 arch/x86/events/intel/rapl.c     | 51 +++++++++++++++++++++++++++--
 arch/x86/include/asm/msr-index.h |  2 ++
 drivers/powercap/intel_rapl.c    | 69 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 120 insertions(+), 2 deletions(-)

-- 
1.9.1

[toc] | [next] | [standalone]

#1380852 — [PATCH v4 2/2] powercap: intel_rapl: PSys support

Skylake processor supports a new set of RAPL registers for controlling
entire SoC instead of just CPU package. This is useful for thermal
and power control when source of power/thermal is not just CPU/GPU.
This change adds a new platform domain (AKA PSys) to the current
power capping Intel RAPL driver.
PSys also supports PL1 (long term) and PL2 (short term) control like
package domain. This also follows same MSRs for energy and time
units as package domain.
Unlike package domain, PSys support requires more than just processor
level implementation. The other parts in the system need additional
implementation, which OEMs needs to support. So not all Skylake
systems will support PSys.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
 drivers/powercap/intel_rapl.c | 69 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index 8fad0a7..f2201d4 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -34,6 +34,9 @@
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
 
+/* Local defines */
+#define MSR_PLATFORM_POWER_LIMIT	0x0000065C
+
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff
 
@@ -86,6 +89,7 @@ enum rapl_domain_type {
 	RAPL_DOMAIN_PP0, /* core power plane */
 	RAPL_DOMAIN_PP1, /* graphics uncore */
 	RAPL_DOMAIN_DRAM,/* DRAM control_type */
+	RAPL_DOMAIN_PLATFORM, /* PSys control_type */
 	RAPL_DOMAIN_MAX,
 };
 
@@ -251,9 +255,11 @@ static const char * const rapl_domain_names[] = {
 	"core",
 	"uncore",
 	"dram",
+	"psys",
 };
 
 static struct powercap_control_type *control_type; /* PowerCap Controller */
+static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
 
 /* caller to ensure CPU hotplug lock is held */
 static struct rapl_package *find_package_by_id(int id)
@@ -409,6 +415,14 @@ static const struct powercap_zone_ops zone_ops[] = {
 		.set_enable = set_domain_enable,
 		.get_enable = get_domain_enable,
 	},
+	/* RAPL_DOMAIN_PLATFORM */
+	{
+		.get_energy_uj = get_energy_counter,
+		.get_max_energy_range_uj = get_max_energy_counter,
+		.release = release_zone,
+		.set_enable = set_domain_enable,
+		.get_enable = get_domain_enable,
+	},
 };
 
 static int set_power_limit(struct powercap_zone *power_zone, int id,
@@ -1160,6 +1174,13 @@ static int rapl_unregister_powercap(void)
 			powercap_unregister_zone(control_type,
 						&rd_package->power_zone);
 	}
+
+	if (platform_rapl_domain) {
+		powercap_unregister_zone(control_type,
+					 &platform_rapl_domain->power_zone);
+		kfree(platform_rapl_domain);
+	}
+
 	powercap_unregister_control_type(control_type);
 
 	return 0;
@@ -1239,6 +1260,47 @@ err_cleanup:
 	return ret;
 }
 
+static int rapl_register_psys(void)
+{
+	struct rapl_domain *rd;
+	struct powercap_zone *power_zone;
+	u64 val;
+
+	if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
+		return -ENODEV;
+
+	if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
+		return -ENODEV;
+
+	rd = kzalloc(sizeof(*rd), GFP_KERNEL);
+	if (!rd)
+		return -ENOMEM;
+
+	rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
+	rd->id = RAPL_DOMAIN_PLATFORM;
+	rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
+	rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
+	rd->rpl[0].prim_id = PL1_ENABLE;
+	rd->rpl[0].name = pl1_name;
+	rd->rpl[1].prim_id = PL2_ENABLE;
+	rd->rpl[1].name = pl2_name;
+	rd->rp = find_package_by_id(0);
+
+	power_zone = powercap_register_zone(&rd->power_zone, control_type,
+					    "psys", NULL,
+					    &zone_ops[RAPL_DOMAIN_PLATFORM],
+					    2, &constraint_ops);
+
+	if (IS_ERR(power_zone)) {
+		kfree(rd);
+		return PTR_ERR(power_zone);
+	}
+
+	platform_rapl_domain = rd;
+
+	return 0;
+}
+
 static int rapl_register_powercap(void)
 {
 	struct rapl_domain *rd;
@@ -1255,6 +1317,10 @@ static int rapl_register_powercap(void)
 	list_for_each_entry(rp, &rapl_packages, plist)
 		if (rapl_package_register_powercap(rp))
 			goto err_cleanup_package;
+
+	/* Don't bail out if PSys is not supported */
+	rapl_register_psys();
+
 	return ret;
 
 err_cleanup_package:
@@ -1289,6 +1355,9 @@ static int rapl_check_domain(int cpu, int domain)
 	case RAPL_DOMAIN_DRAM:
 		msr = MSR_DRAM_ENERGY_STATUS;
 		break;
+	case RAPL_DOMAIN_PLATFORM:
+		/* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
+		return -EINVAL;
 	default:
 		pr_err("invalid domain id %d\n", domain);
 		return -EINVAL;
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1389978 — [tip:perf/core] powercap, perf/x86/intel/rapl: Add PSys support

Commit-ID:  3521ba1cc351e80488c3f85748c92c3853b75818
Gitweb:     http://git.kernel.org/tip/3521ba1cc351e80488c3f85748c92c3853b75818
Author:     Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
AuthorDate: Sun, 17 Apr 2016 15:03:01 -0700
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 28 Apr 2016 10:39:19 +0200

powercap, perf/x86/intel/rapl: Add PSys support

Skylake processor supports a new set of RAPL registers for controlling
entire SoC instead of just CPU package. This is useful for thermal
and power control when source of power/thermal is not just CPU/GPU.
This change adds a new platform domain (AKA PSys) to the current
power capping Intel RAPL driver.

PSys also supports PL1 (long term) and PL2 (short term) control like
package domain. This also follows same MSRs for energy and time
units as package domain.

Unlike package domain, PSys support requires more than just processor
level implementation. The other parts in the system need additional
implementation, which OEMs needs to support. So not all Skylake
systems will support PSys.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: bp@alien8.de
Cc: hpa@zytor.com
Cc: jacob.jun.pan@linux.intel.com
Cc: rjw@rjwysocki.net
Link: http://lkml.kernel.org/r/1460930581-29748-3-git-send-email-srinivas.pandruvada@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 drivers/powercap/intel_rapl.c | 69 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index 8fad0a7..f2201d4 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -34,6 +34,9 @@
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
 
+/* Local defines */
+#define MSR_PLATFORM_POWER_LIMIT	0x0000065C
+
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff
 
@@ -86,6 +89,7 @@ enum rapl_domain_type {
 	RAPL_DOMAIN_PP0, /* core power plane */
 	RAPL_DOMAIN_PP1, /* graphics uncore */
 	RAPL_DOMAIN_DRAM,/* DRAM control_type */
+	RAPL_DOMAIN_PLATFORM, /* PSys control_type */
 	RAPL_DOMAIN_MAX,
 };
 
@@ -251,9 +255,11 @@ static const char * const rapl_domain_names[] = {
 	"core",
 	"uncore",
 	"dram",
+	"psys",
 };
 
 static struct powercap_control_type *control_type; /* PowerCap Controller */
+static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
 
 /* caller to ensure CPU hotplug lock is held */
 static struct rapl_package *find_package_by_id(int id)
@@ -409,6 +415,14 @@ static const struct powercap_zone_ops zone_ops[] = {
 		.set_enable = set_domain_enable,
 		.get_enable = get_domain_enable,
 	},
+	/* RAPL_DOMAIN_PLATFORM */
+	{
+		.get_energy_uj = get_energy_counter,
+		.get_max_energy_range_uj = get_max_energy_counter,
+		.release = release_zone,
+		.set_enable = set_domain_enable,
+		.get_enable = get_domain_enable,
+	},
 };
 
 static int set_power_limit(struct powercap_zone *power_zone, int id,
@@ -1160,6 +1174,13 @@ static int rapl_unregister_powercap(void)
 			powercap_unregister_zone(control_type,
 						&rd_package->power_zone);
 	}
+
+	if (platform_rapl_domain) {
+		powercap_unregister_zone(control_type,
+					 &platform_rapl_domain->power_zone);
+		kfree(platform_rapl_domain);
+	}
+
 	powercap_unregister_control_type(control_type);
 
 	return 0;
@@ -1239,6 +1260,47 @@ err_cleanup:
 	return ret;
 }
 
+static int rapl_register_psys(void)
+{
+	struct rapl_domain *rd;
+	struct powercap_zone *power_zone;
+	u64 val;
+
+	if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
+		return -ENODEV;
+
+	if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
+		return -ENODEV;
+
+	rd = kzalloc(sizeof(*rd), GFP_KERNEL);
+	if (!rd)
+		return -ENOMEM;
+
+	rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
+	rd->id = RAPL_DOMAIN_PLATFORM;
+	rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
+	rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
+	rd->rpl[0].prim_id = PL1_ENABLE;
+	rd->rpl[0].name = pl1_name;
+	rd->rpl[1].prim_id = PL2_ENABLE;
+	rd->rpl[1].name = pl2_name;
+	rd->rp = find_package_by_id(0);
+
+	power_zone = powercap_register_zone(&rd->power_zone, control_type,
+					    "psys", NULL,
+					    &zone_ops[RAPL_DOMAIN_PLATFORM],
+					    2, &constraint_ops);
+
+	if (IS_ERR(power_zone)) {
+		kfree(rd);
+		return PTR_ERR(power_zone);
+	}
+
+	platform_rapl_domain = rd;
+
+	return 0;
+}
+
 static int rapl_register_powercap(void)
 {
 	struct rapl_domain *rd;
@@ -1255,6 +1317,10 @@ static int rapl_register_powercap(void)
 	list_for_each_entry(rp, &rapl_packages, plist)
 		if (rapl_package_register_powercap(rp))
 			goto err_cleanup_package;
+
+	/* Don't bail out if PSys is not supported */
+	rapl_register_psys();
+
 	return ret;
 
 err_cleanup_package:
@@ -1289,6 +1355,9 @@ static int rapl_check_domain(int cpu, int domain)
 	case RAPL_DOMAIN_DRAM:
 		msr = MSR_DRAM_ENERGY_STATUS;
 		break;
+	case RAPL_DOMAIN_PLATFORM:
+		/* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
+		return -EINVAL;
 	default:
 		pr_err("invalid domain id %d\n", domain);
 		return -EINVAL;

[toc] | [prev] | [next] | [standalone]

#1383414

On Sun, Apr 17, 2016 at 03:02:59PM -0700, Srinivas Pandruvada wrote:
> Skylake processor supports a new set of RAPL registers for controlling
> entire SoC instead of just CPU package called PSys. This change adds
> support in two sub systems:
> 
> x86/perf: Adds basic support for Skylake RAPL and PSys support
> 
> powercap/rapl: A new platform domain to the current power capping Intel
> RAPL driver.

> Srinivas Pandruvada (2):
>   perf/x86/intel/rapl: support Skylake RAPL domains
>   powercap: intel_rapl: PSys support
> 
>  arch/x86/events/intel/rapl.c     | 51 +++++++++++++++++++++++++++--
>  arch/x86/include/asm/msr-index.h |  2 ++
>  drivers/powercap/intel_rapl.c    | 69 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 120 insertions(+), 2 deletions(-)

These two patches depend on one another, right? Because the first patch
adds the MSR the second patch uses?

How should we go about merging this? The perf-rapl stuff normally goes
through tip while the powercap stuff goes through Rafael's tree.

[toc] | [prev] | [next] | [standalone]

#1383627

On Wed, 2016-04-20 at 15:59 +0200, Peter Zijlstra wrote:
> On Sun, Apr 17, 2016 at 03:02:59PM -0700, Srinivas Pandruvada wrote:
> > 
> > Skylake processor supports a new set of RAPL registers for
> > controlling
> > entire SoC instead of just CPU package called PSys. This change
> > adds
> > support in two sub systems:
> > 
> > x86/perf: Adds basic support for Skylake RAPL and PSys support
> > 
> > powercap/rapl: A new platform domain to the current power capping
> > Intel
> > RAPL driver.
> > 
> > Srinivas Pandruvada (2):
> >   perf/x86/intel/rapl: support Skylake RAPL domains
> >   powercap: intel_rapl: PSys support
> > 
> >  arch/x86/events/intel/rapl.c     | 51 +++++++++++++++++++++++++++-
> > -
> >  arch/x86/include/asm/msr-index.h |  2 ++
> >  drivers/powercap/intel_rapl.c    | 69
> > ++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 120 insertions(+), 2 deletions(-)
> These two patches depend on one another, right? 
Yes.
> Because the first patch
> adds the MSR the second patch uses?
> 
> How should we go about merging this? The perf-rapl stuff normally
> goes
> through tip while the powercap stuff goes through Rafael's tree.
Do you want me to only send PERF patch and wait for this to be merged
before sending powercap?

Thanks,
Srinivas

[toc] | [prev] | [next] | [standalone]

#1383723

On Wed, Apr 20, 2016 at 8:28 PM, Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
> On Wed, 2016-04-20 at 15:59 +0200, Peter Zijlstra wrote:
>> On Sun, Apr 17, 2016 at 03:02:59PM -0700, Srinivas Pandruvada wrote:
>> >
>> > Skylake processor supports a new set of RAPL registers for
>> > controlling
>> > entire SoC instead of just CPU package called PSys. This change
>> > adds
>> > support in two sub systems:
>> >
>> > x86/perf: Adds basic support for Skylake RAPL and PSys support
>> >
>> > powercap/rapl: A new platform domain to the current power capping
>> > Intel
>> > RAPL driver.
>> >
>> > Srinivas Pandruvada (2):
>> >   perf/x86/intel/rapl: support Skylake RAPL domains
>> >   powercap: intel_rapl: PSys support
>> >
>> >  arch/x86/events/intel/rapl.c     | 51 +++++++++++++++++++++++++++-
>> > -
>> >  arch/x86/include/asm/msr-index.h |  2 ++
>> >  drivers/powercap/intel_rapl.c    | 69
>> > ++++++++++++++++++++++++++++++++++++++++
>> >  3 files changed, 120 insertions(+), 2 deletions(-)
>> These two patches depend on one another, right?
> Yes.
>> Because the first patch
>> adds the MSR the second patch uses?
>>
>> How should we go about merging this? The perf-rapl stuff normally
>> goes
>> through tip while the powercap stuff goes through Rafael's tree.
> Do you want me to only send PERF patch and wait for this to be merged
> before sending powercap?

You can send both and they both can go in via tip as far as I'm concerned.

[toc] | [prev] | [next] | [standalone]

#1384198

On Wed, Apr 20, 2016 at 10:21:14PM +0200, Rafael J. Wysocki wrote:
> You can send both and they both can go in via tip as far as I'm concerned.

OK, thanks!

Srinivas I've munged the rapl patch to match the new style, so no need
to resend that.

[toc] | [prev] | [next] | [standalone]

#1384320

On Thu, 2016-04-21 at 15:10 +0200, Peter Zijlstra wrote:
> On Wed, Apr 20, 2016 at 10:21:14PM +0200, Rafael J. Wysocki wrote:
> > You can send both and they both can go in via tip as far as I'm
> > concerned.
> 
> OK, thanks!
> 
> Srinivas I've munged the rapl patch to match the new style, so no
> need
> to resend that.
Thanks Peter.

-Srinivas

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web