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[PATCH] ARM: dts: omap3: Fix ISP syscon register offset

Started byIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
First post2016-04-16 08:30 +0200
Last post2016-04-26 19:20 +0200
Articles 4 — 3 participants

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  [PATCH] ARM: dts: omap3: Fix ISP syscon register offset Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> - 2016-04-16 08:30 +0200
    Re: [PATCH] ARM: dts: omap3: Fix ISP syscon register offset Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> - 2016-04-22 06:40 +0200
      Re: [PATCH] ARM: dts: omap3: Fix ISP syscon register offset Sebastian Reichel <sre@kernel.org> - 2016-04-22 15:20 +0200
        Re: [PATCH] ARM: dts: omap3: Fix ISP syscon register offset Tony Lindgren <tony@atomide.com> - 2016-04-26 19:20 +0200

#1380489 — [PATCH] ARM: dts: omap3: Fix ISP syscon register offset

FromIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Date2016-04-16 08:30 +0200
Subject[PATCH] ARM: dts: omap3: Fix ISP syscon register offset
Message-ID<rorTX-7Di-3@gated-at.bofh.it>
According to the TRM, SCM CONTROL_CSIRXFE register is on offset 0x6c

Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
---
 arch/arm/boot/dts/omap34xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5cdba1f..e446562 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -46,7 +46,7 @@
 			       0x480bd800 0x017c>;
 			interrupts = <24>;
 			iommus = <&mmu_isp>;
-			syscon = <&scm_conf 0xdc>;
+			syscon = <&scm_conf 0x6c>;
 			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
 			#clock-cells = <1>;
 			ports {
-- 
1.9.1

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#1384691

FromIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Date2016-04-22 06:40 +0200
Message-ID<rqB2O-4hU-1@gated-at.bofh.it>
In reply to#1380489

On 16.04.2016 09:20, Ivaylo Dimitrov wrote:
> According to the TRM, SCM CONTROL_CSIRXFE register is on offset 0x6c
>
> Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
> ---
>   arch/arm/boot/dts/omap34xx.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
> index 5cdba1f..e446562 100644
> --- a/arch/arm/boot/dts/omap34xx.dtsi
> +++ b/arch/arm/boot/dts/omap34xx.dtsi
> @@ -46,7 +46,7 @@
>   			       0x480bd800 0x017c>;
>   			interrupts = <24>;
>   			iommus = <&mmu_isp>;
> -			syscon = <&scm_conf 0xdc>;
> +			syscon = <&scm_conf 0x6c>;
>   			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
>   			#clock-cells = <1>;
>   			ports {
>

Anyone going to review that?

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#1385154

FromSebastian Reichel <sre@kernel.org>
Date2016-04-22 15:20 +0200
Message-ID<rqJa2-2uZ-3@gated-at.bofh.it>
In reply to#1384691

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Fri, Apr 22, 2016 at 07:34:43AM +0300, Ivaylo Dimitrov wrote:
> On 16.04.2016 09:20, Ivaylo Dimitrov wrote:
> >According to the TRM, SCM CONTROL_CSIRXFE register is on offset 0x6c
> >
> >Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
> >---
> >  arch/arm/boot/dts/omap34xx.dtsi | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
> >index 5cdba1f..e446562 100644
> >--- a/arch/arm/boot/dts/omap34xx.dtsi
> >+++ b/arch/arm/boot/dts/omap34xx.dtsi
> >@@ -46,7 +46,7 @@
> >  			       0x480bd800 0x017c>;
> >  			interrupts = <24>;
> >  			iommus = <&mmu_isp>;
> >-			syscon = <&scm_conf 0xdc>;
> >+			syscon = <&scm_conf 0x6c>;
> >  			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
> >  			#clock-cells = <1>;
> >  			ports {
> >

You may want to add the hint, that 0xdc (the old, wrong "offset")
represents the last few bits of the register address. I guess
somebody didn't notice, that scm_conf does not start at a register
address ending with 00 (like most other modules).

Reviewed-By: Sebastian Reichel <sre@kernel.org>

-- Sebastian

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#1387734

FromTony Lindgren <tony@atomide.com>
Date2016-04-26 19:20 +0200
Message-ID<rseOv-2Z1-25@gated-at.bofh.it>
In reply to#1385154
* Sebastian Reichel <sre@kernel.org> [160422 06:17]:
> Hi,
> 
> On Fri, Apr 22, 2016 at 07:34:43AM +0300, Ivaylo Dimitrov wrote:
> > On 16.04.2016 09:20, Ivaylo Dimitrov wrote:
> > >According to the TRM, SCM CONTROL_CSIRXFE register is on offset 0x6c
> > >
> > >Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
> > >---
> > >  arch/arm/boot/dts/omap34xx.dtsi | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > >diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
> > >index 5cdba1f..e446562 100644
> > >--- a/arch/arm/boot/dts/omap34xx.dtsi
> > >+++ b/arch/arm/boot/dts/omap34xx.dtsi
> > >@@ -46,7 +46,7 @@
> > >  			       0x480bd800 0x017c>;
> > >  			interrupts = <24>;
> > >  			iommus = <&mmu_isp>;
> > >-			syscon = <&scm_conf 0xdc>;
> > >+			syscon = <&scm_conf 0x6c>;
> > >  			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
> > >  			#clock-cells = <1>;
> > >  			ports {
> > >
> 
> You may want to add the hint, that 0xdc (the old, wrong "offset")
> represents the last few bits of the register address. I guess
> somebody didn't notice, that scm_conf does not start at a register
> address ending with 00 (like most other modules).
> 
> Reviewed-By: Sebastian Reichel <sre@kernel.org>

Applying into omap-for-v4.6/fixes-rc5 thanks.

Tony

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